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fixup GPS on the cambria - thanks Chris
[openwrt.git] / target / linux / at91 / patches-2.6.25 / 000-at91patches.patch
1 --- a/arch/arm/mach-at91/Kconfig
2 +++ b/arch/arm/mach-at91/Kconfig
3 @@ -12,18 +12,28 @@
4
5 config ARCH_AT91SAM9260
6 bool "AT91SAM9260 or AT91SAM9XE"
7 + select GENERIC_TIME
8 + select GENERIC_CLOCKEVENTS
9
10 config ARCH_AT91SAM9261
11 bool "AT91SAM9261"
12 + select GENERIC_TIME
13 + select GENERIC_CLOCKEVENTS
14
15 config ARCH_AT91SAM9263
16 bool "AT91SAM9263"
17 + select GENERIC_TIME
18 + select GENERIC_CLOCKEVENTS
19
20 config ARCH_AT91SAM9RL
21 bool "AT91SAM9RL"
22 + select GENERIC_TIME
23 + select GENERIC_CLOCKEVENTS
24
25 config ARCH_AT91CAP9
26 bool "AT91CAP9"
27 + select GENERIC_TIME
28 + select GENERIC_CLOCKEVENTS
29
30 config ARCH_AT91X40
31 bool "AT91x40"
32 @@ -45,7 +55,7 @@
33 depends on ARCH_AT91RM9200
34 help
35 Select this if you are using Ajeco's 1ARM Single Board Computer.
36 - <http://www.ajeco.fi/products.htm>
37 + <http://www.ajeco.fi/eng/products_e.htm>
38
39 config ARCH_AT91RM9200DK
40 bool "Atmel AT91RM9200-DK Development board"
41 @@ -94,7 +104,7 @@
42 depends on ARCH_AT91RM9200
43 help
44 Select this if you are using KwikByte's KB920x board.
45 - <http://kwikbyte.com/KB9202_description_new.htm>
46 + <http://www.kwikbyte.com/KB9202.html>
47
48 config MACH_PICOTUX2XX
49 bool "picotux 200"
50 @@ -109,6 +119,38 @@
51 help
52 Select this if you are using Sperry-Sun's KAFA board.
53
54 +config MACH_CHUB
55 + bool "Promwad Chub board"
56 + depends on ARCH_AT91RM9200
57 + help
58 + Select this if you are using Promwad's Chub board.
59 +
60 +config MACH_HOMEMATIC
61 + bool "eQ-3 HomeMatic"
62 + depends on ARCH_AT91RM9200
63 + help
64 + Select this if you are using eQ-3's HomeMatic device.
65 + <http://www.eq-3.com>
66 +
67 +config MACH_ECBAT91
68 + bool "emQbit ECB_AT91 SBC"
69 + depends on ARCH_AT91RM9200
70 + help
71 + Select this if you are using emQbit's ECB_AT91 board.
72 + <http://wiki.emqbit.com/free-ecb-at91>
73 +
74 +config MACH_SWEDATMS
75 + bool "Sweda TMS Board"
76 + depends on ARCH_AT91RM9200
77 + help
78 + Select this if you are using Sweda TMS-100 board.
79 +
80 +config MACH_TT9200
81 + bool "Toptech TT9200"
82 + depends on ARCH_AT91RM9200
83 + help
84 + Select this if you are using Toptech's TT9200 board.
85 +
86 endif
87
88 # ----------------------------------------------------------
89 @@ -133,6 +175,34 @@
90 Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
91 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
92
93 +config MACH_CAM60
94 + bool "KwikByte KB9260 (CAM60) board"
95 + depends on ARCH_AT91SAM9260
96 + help
97 + Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
98 + <http://www.kwikbyte.com/KB9260.html>
99 +
100 +config MACH_SAM9_L9260
101 + bool "Olimex SAM9-L9260 board"
102 + depends on ARCH_AT91SAM9260
103 + help
104 + Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
105 + <http://www.olimex.com/dev/sam9-L9260.html>
106 +
107 +config MACH_USB_A9260
108 + bool "CALAO USB-A9260"
109 + depends on ARCH_AT91SAM9260
110 + help
111 + Select this if you are using a Calao Systems USB-A9260.
112 + <http://www.calao-systems.com>
113 +
114 +config MACH_QIL_A9260
115 + bool "CALAO QIL-A9260 board"
116 + depends on ARCH_AT91SAM9260
117 + help
118 + Select this if you are using a Calao Systems QIL-A9260 Board.
119 + <http://www.calao-systems.com>
120 +
121 endif
122
123 # ----------------------------------------------------------
124 @@ -163,6 +233,13 @@
125 Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
126 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
127
128 +config MACH_USB_A9263
129 + bool "CALAO USB-A9263"
130 + depends on ARCH_AT91SAM9263
131 + help
132 + Select this if you are using a Calao Systems USB-A9263.
133 + <http://www.calao-systems.com>
134 +
135 endif
136
137 # ----------------------------------------------------------
138 @@ -216,7 +293,7 @@
139
140 config MTD_AT91_DATAFLASH_CARD
141 bool "Enable DataFlash Card support"
142 - depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
143 + depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK)
144 help
145 Enable support for the DataFlash card.
146
147 @@ -237,6 +314,19 @@
148 Select this if you need to program one or more of the PCK0..PCK3
149 programmable clock outputs.
150
151 +config AT91_SLOW_CLOCK
152 + bool "Suspend-to-RAM disables main oscillator"
153 + depends on SUSPEND
154 + help
155 + Select this if you want Suspend-to-RAM to save the most power
156 + possible (without powering off the CPU) by disabling the PLLs
157 + and main oscillator so that only the 32 KiHz clock is available.
158 +
159 + When only that slow-clock is available, some peripherals lose
160 + functionality. Many can't issue wakeup events unless faster
161 + clocks are available. Some lose their operating state and
162 + need to be completely re-initialized.
163 +
164 config AT91_TIMER_HZ
165 int "Kernel HZ (jiffies per second)"
166 range 32 1024
167 --- a/arch/arm/mach-at91/Makefile
168 +++ b/arch/arm/mach-at91/Makefile
169 @@ -28,16 +28,26 @@
170 obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
171 obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
172 obj-$(CONFIG_MACH_KAFA) += board-kafa.o
173 +obj-$(CONFIG_MACH_CHUB) += board-chub.o
174 obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
175 +obj-$(CONFIG_MACH_HOMEMATIC) += board-homematic.o
176 +obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
177 +obj-$(CONFIG_MACH_SWEDATMS) += board-tms.o
178 +obj-$(CONFIG_MACH_TT9200) += board-tt9200.o
179
180 # AT91SAM9260 board-specific support
181 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
182 +obj-$(CONFIG_MACH_CAM60) += board-cam60.o
183 +obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
184 +obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o
185 +obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o
186
187 # AT91SAM9261 board-specific support
188 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
189
190 # AT91SAM9263 board-specific support
191 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
192 +obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o
193
194 # AT91SAM9RL board-specific support
195 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
196 @@ -50,9 +60,11 @@
197
198 # Drivers
199 obj-y += leds.o
200 +obj-$(CONFIG_FB_S1D13XXX) += ics1523.o
201
202 # Power Management
203 obj-$(CONFIG_PM) += pm.o
204 +obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
205
206 ifeq ($(CONFIG_PM_DEBUG),y)
207 CFLAGS_pm.o += -DDEBUG
208 --- a/arch/arm/mach-at91/at91cap9.c
209 +++ b/arch/arm/mach-at91/at91cap9.c
210 @@ -13,12 +13,15 @@
211 */
212
213 #include <linux/module.h>
214 +#include <linux/pm.h>
215
216 #include <asm/mach/arch.h>
217 #include <asm/mach/map.h>
218 +#include <asm/arch/cpu.h>
219 #include <asm/arch/at91cap9.h>
220 #include <asm/arch/at91_pmc.h>
221 #include <asm/arch/at91_rstc.h>
222 +#include <asm/arch/at91_shdwc.h>
223
224 #include "generic.h"
225 #include "clock.h"
226 @@ -288,6 +291,12 @@
227 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
228 }
229
230 +static void at91cap9_poweroff(void)
231 +{
232 + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
233 +}
234 +
235 +
236 /* --------------------------------------------------------------------
237 * AT91CAP9 processor initialization
238 * -------------------------------------------------------------------- */
239 @@ -298,6 +307,7 @@
240 iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
241
242 at91_arch_reset = at91cap9_reset;
243 + pm_power_off = at91cap9_poweroff;
244 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
245
246 /* Init clock subsystem */
247 @@ -308,6 +318,12 @@
248
249 /* Register GPIO subsystem */
250 at91_gpio_init(at91cap9_gpio, 4);
251 +
252 + /* Remember the silicon revision */
253 + if (cpu_is_at91cap9_revB())
254 + system_rev = 0xB;
255 + else if (cpu_is_at91cap9_revC())
256 + system_rev = 0xC;
257 }
258
259 /* --------------------------------------------------------------------
260 --- a/arch/arm/mach-at91/at91cap9_devices.c
261 +++ b/arch/arm/mach-at91/at91cap9_devices.c
262 @@ -13,18 +13,20 @@
263 */
264 #include <asm/mach/arch.h>
265 #include <asm/mach/map.h>
266 +#include <asm/mach/irq.h>
267
268 #include <linux/dma-mapping.h>
269 #include <linux/platform_device.h>
270 -#include <linux/mtd/physmap.h>
271 +#include <linux/i2c-gpio.h>
272
273 #include <video/atmel_lcdc.h>
274
275 #include <asm/arch/board.h>
276 +#include <asm/arch/cpu.h>
277 #include <asm/arch/gpio.h>
278 #include <asm/arch/at91cap9.h>
279 -#include <asm/arch/at91sam926x_mc.h>
280 #include <asm/arch/at91cap9_matrix.h>
281 +#include <asm/arch/at91sam9_smc.h>
282
283 #include "generic.h"
284
285 @@ -69,6 +71,9 @@
286 if (!data)
287 return;
288
289 + if (cpu_is_at91cap9_revB())
290 + set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
291 +
292 /* Enable VBus control for UHP ports */
293 for (i = 0; i < data->ports; i++) {
294 if (data->vbus_pin[i])
295 @@ -84,6 +89,110 @@
296
297
298 /* --------------------------------------------------------------------
299 + * USB HS Device (Gadget)
300 + * -------------------------------------------------------------------- */
301 +
302 +#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
303 +
304 +static struct resource usba_udc_resources[] = {
305 + [0] = {
306 + .start = AT91CAP9_UDPHS_FIFO,
307 + .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
308 + .flags = IORESOURCE_MEM,
309 + },
310 + [1] = {
311 + .start = AT91CAP9_BASE_UDPHS,
312 + .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
313 + .flags = IORESOURCE_MEM,
314 + },
315 + [2] = {
316 + .start = AT91CAP9_ID_UDPHS,
317 + .end = AT91CAP9_ID_UDPHS,
318 + .flags = IORESOURCE_IRQ,
319 + },
320 +};
321 +
322 +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
323 + [idx] = { \
324 + .name = nam, \
325 + .index = idx, \
326 + .fifo_size = maxpkt, \
327 + .nr_banks = maxbk, \
328 + .can_dma = dma, \
329 + .can_isoc = isoc, \
330 + }
331 +
332 +static struct usba_ep_data usba_udc_ep[] = {
333 + EP("ep0", 0, 64, 1, 0, 0),
334 + EP("ep1", 1, 1024, 3, 1, 1),
335 + EP("ep2", 2, 1024, 3, 1, 1),
336 + EP("ep3", 3, 1024, 2, 1, 1),
337 + EP("ep4", 4, 1024, 2, 1, 1),
338 + EP("ep5", 5, 1024, 2, 1, 0),
339 + EP("ep6", 6, 1024, 2, 1, 0),
340 + EP("ep7", 7, 1024, 2, 0, 0),
341 +};
342 +
343 +#undef EP
344 +
345 +/*
346 + * pdata doesn't have room for any endpoints, so we need to
347 + * append room for the ones we need right after it.
348 + */
349 +static struct {
350 + struct usba_platform_data pdata;
351 + struct usba_ep_data ep[8];
352 +} usba_udc_data;
353 +
354 +static struct platform_device at91_usba_udc_device = {
355 + .name = "atmel_usba_udc",
356 + .id = -1,
357 + .dev = {
358 + .platform_data = &usba_udc_data.pdata,
359 + },
360 + .resource = usba_udc_resources,
361 + .num_resources = ARRAY_SIZE(usba_udc_resources),
362 +};
363 +
364 +void __init at91_add_device_usba(struct usba_platform_data *data)
365 +{
366 + if (cpu_is_at91cap9_revB()) {
367 + set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
368 + at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
369 + AT91_MATRIX_UDPHS_BYPASS_LOCK);
370 + }
371 + else
372 + at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
373 +
374 + /*
375 + * Invalid pins are 0 on AT91, but the usba driver is shared
376 + * with AVR32, which use negative values instead. Once/if
377 + * gpio_is_valid() is ported to AT91, revisit this code.
378 + */
379 + usba_udc_data.pdata.vbus_pin = -EINVAL;
380 + usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
381 + memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
382 +
383 + if (data && data->vbus_pin > 0) {
384 + at91_set_gpio_input(data->vbus_pin, 0);
385 + at91_set_deglitch(data->vbus_pin, 1);
386 + usba_udc_data.pdata.vbus_pin = data->vbus_pin;
387 + }
388 +
389 + /* Pullup pin is handled internally by USB device peripheral */
390 +
391 + /* Clocks */
392 + at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
393 + at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
394 +
395 + platform_device_register(&at91_usba_udc_device);
396 +}
397 +#else
398 +void __init at91_add_device_usba(struct usba_platform_data *data) {}
399 +#endif
400 +
401 +
402 +/* --------------------------------------------------------------------
403 * Ethernet
404 * -------------------------------------------------------------------- */
405
406 @@ -246,7 +355,7 @@
407 }
408
409 mmc0_data = *data;
410 - at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk");
411 + at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk");
412 platform_device_register(&at91cap9_mmc0_device);
413 } else { /* MCI1 */
414 /* CLK */
415 @@ -283,10 +392,15 @@
416 #define NAND_BASE AT91_CHIPSELECT_3
417
418 static struct resource nand_resources[] = {
419 - {
420 + [0] = {
421 .start = NAND_BASE,
422 .end = NAND_BASE + SZ_256M - 1,
423 .flags = IORESOURCE_MEM,
424 + },
425 + [1] = {
426 + .start = AT91_BASE_SYS + AT91_ECC,
427 + .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
428 + .flags = IORESOURCE_MEM,
429 }
430 };
431
432 @@ -344,6 +458,7 @@
433 void __init at91_add_device_nand(struct at91_nand_data *data) {}
434 #endif
435
436 +
437 /* --------------------------------------------------------------------
438 * TWI (i2c)
439 * -------------------------------------------------------------------- */
440 @@ -532,17 +647,64 @@
441
442
443 /* --------------------------------------------------------------------
444 + * Timer/Counter block
445 + * -------------------------------------------------------------------- */
446 +
447 +#ifdef CONFIG_ATMEL_TCLIB
448 +
449 +static struct resource tcb_resources[] = {
450 + [0] = {
451 + .start = AT91CAP9_BASE_TCB0,
452 + .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
453 + .flags = IORESOURCE_MEM,
454 + },
455 + [1] = {
456 + .start = AT91CAP9_ID_TCB,
457 + .end = AT91CAP9_ID_TCB,
458 + .flags = IORESOURCE_IRQ,
459 + },
460 +};
461 +
462 +static struct platform_device at91cap9_tcb_device = {
463 + .name = "atmel_tcb",
464 + .id = 0,
465 + .resource = tcb_resources,
466 + .num_resources = ARRAY_SIZE(tcb_resources),
467 +};
468 +
469 +static void __init at91_add_device_tc(void)
470 +{
471 + /* this chip has one clock and irq for all three TC channels */
472 + at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
473 + platform_device_register(&at91cap9_tcb_device);
474 +}
475 +#else
476 +static void __init at91_add_device_tc(void) { }
477 +#endif
478 +
479 +
480 +/* --------------------------------------------------------------------
481 * RTT
482 * -------------------------------------------------------------------- */
483
484 +static struct resource rtt_resources[] = {
485 + {
486 + .start = AT91_BASE_SYS + AT91_RTT,
487 + .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
488 + .flags = IORESOURCE_MEM,
489 + }
490 +};
491 +
492 static struct platform_device at91cap9_rtt_device = {
493 .name = "at91_rtt",
494 - .id = -1,
495 - .num_resources = 0,
496 + .id = 0,
497 + .resource = rtt_resources,
498 + .num_resources = ARRAY_SIZE(rtt_resources),
499 };
500
501 static void __init at91_add_device_rtt(void)
502 {
503 + device_init_wakeup(&at91cap9_rtt_device.dev, 1);
504 platform_device_register(&at91cap9_rtt_device);
505 }
506
507 @@ -660,6 +822,9 @@
508 if (!data)
509 return;
510
511 + if (cpu_is_at91cap9_revB())
512 + set_irq_type(AT91CAP9_ID_LCDC, IRQT_HIGH);
513 +
514 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
515 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
516 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
517 @@ -990,7 +1155,7 @@
518 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
519 }
520
521 -static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
522 +static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
523 struct platform_device *atmel_default_console_device; /* the serial console device */
524
525 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
526 @@ -1031,8 +1196,6 @@
527 {
528 if (portnr < ATMEL_MAX_UART)
529 atmel_default_console_device = at91_uarts[portnr];
530 - if (!atmel_default_console_device)
531 - printk(KERN_INFO "AT91: No default serial console defined.\n");
532 }
533
534 void __init at91_add_device_serial(void)
535 @@ -1043,6 +1206,9 @@
536 if (at91_uarts[i])
537 platform_device_register(at91_uarts[i]);
538 }
539 +
540 + if (!atmel_default_console_device)
541 + printk(KERN_INFO "AT91: No default serial console defined.\n");
542 }
543 #else
544 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
545 @@ -1060,6 +1226,7 @@
546 {
547 at91_add_device_rtt();
548 at91_add_device_watchdog();
549 + at91_add_device_tc();
550 return 0;
551 }
552
553 --- a/arch/arm/mach-at91/at91rm9200_devices.c
554 +++ b/arch/arm/mach-at91/at91rm9200_devices.c
555 @@ -513,7 +513,18 @@
556 * SPI
557 * -------------------------------------------------------------------- */
558
559 -#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
560 +#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) /* legacy SPI driver */
561 +#define SPI_DEVNAME "at91_spi"
562 +
563 +#elif defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) /* SPI bitbanging driver */
564 +#define SPI_DEVNAME "at91_spi"
565 +
566 +#elif defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) /* new SPI driver */
567 +#define SPI_DEVNAME "atmel_spi"
568 +
569 +#endif
570 +
571 +#ifdef SPI_DEVNAME
572 static u64 spi_dmamask = DMA_BIT_MASK(32);
573
574 static struct resource spi_resources[] = {
575 @@ -530,7 +541,7 @@
576 };
577
578 static struct platform_device at91rm9200_spi_device = {
579 - .name = "atmel_spi",
580 + .name = SPI_DEVNAME,
581 .id = 0,
582 .dev = {
583 .dma_mask = &spi_dmamask,
584 @@ -563,6 +574,12 @@
585 else
586 at91_set_gpio_output(cs_pin, 1);
587
588 +#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
589 + /*
590 + * Force peripheral mode when using the legacy SPI driver.
591 + */
592 + at91_set_A_periph(cs_pin, 0);
593 +#endif
594
595 /* pass chip-select pin to driver */
596 devices[i].controller_data = (void *) cs_pin;
597 @@ -577,6 +594,90 @@
598
599
600 /* --------------------------------------------------------------------
601 + * Timer/Counter blocks
602 + * -------------------------------------------------------------------- */
603 +
604 +#ifdef CONFIG_ATMEL_TCLIB
605 +
606 +static struct resource tcb0_resources[] = {
607 + [0] = {
608 + .start = AT91RM9200_BASE_TCB0,
609 + .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
610 + .flags = IORESOURCE_MEM,
611 + },
612 + [1] = {
613 + .start = AT91RM9200_ID_TC0,
614 + .end = AT91RM9200_ID_TC0,
615 + .flags = IORESOURCE_IRQ,
616 + },
617 + [2] = {
618 + .start = AT91RM9200_ID_TC1,
619 + .end = AT91RM9200_ID_TC1,
620 + .flags = IORESOURCE_IRQ,
621 + },
622 + [3] = {
623 + .start = AT91RM9200_ID_TC2,
624 + .end = AT91RM9200_ID_TC2,
625 + .flags = IORESOURCE_IRQ,
626 + },
627 +};
628 +
629 +static struct platform_device at91rm9200_tcb0_device = {
630 + .name = "atmel_tcb",
631 + .id = 0,
632 + .resource = tcb0_resources,
633 + .num_resources = ARRAY_SIZE(tcb0_resources),
634 +};
635 +
636 +static struct resource tcb1_resources[] = {
637 + [0] = {
638 + .start = AT91RM9200_BASE_TCB1,
639 + .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
640 + .flags = IORESOURCE_MEM,
641 + },
642 + [1] = {
643 + .start = AT91RM9200_ID_TC3,
644 + .end = AT91RM9200_ID_TC3,
645 + .flags = IORESOURCE_IRQ,
646 + },
647 + [2] = {
648 + .start = AT91RM9200_ID_TC4,
649 + .end = AT91RM9200_ID_TC4,
650 + .flags = IORESOURCE_IRQ,
651 + },
652 + [3] = {
653 + .start = AT91RM9200_ID_TC5,
654 + .end = AT91RM9200_ID_TC5,
655 + .flags = IORESOURCE_IRQ,
656 + },
657 +};
658 +
659 +static struct platform_device at91rm9200_tcb1_device = {
660 + .name = "atmel_tcb",
661 + .id = 1,
662 + .resource = tcb1_resources,
663 + .num_resources = ARRAY_SIZE(tcb1_resources),
664 +};
665 +
666 +static void __init at91_add_device_tc(void)
667 +{
668 + /* this chip has a separate clock and irq for each TC channel */
669 + at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
670 + at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
671 + at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
672 + platform_device_register(&at91rm9200_tcb0_device);
673 +
674 + at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
675 + at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
676 + at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
677 + platform_device_register(&at91rm9200_tcb1_device);
678 +}
679 +#else
680 +static void __init at91_add_device_tc(void) { }
681 +#endif
682 +
683 +
684 +/* --------------------------------------------------------------------
685 * RTC
686 * -------------------------------------------------------------------- */
687
688 @@ -589,6 +690,7 @@
689
690 static void __init at91_add_device_rtc(void)
691 {
692 + device_init_wakeup(&at91rm9200_rtc_device.dev, 1);
693 platform_device_register(&at91rm9200_rtc_device);
694 }
695 #else
696 @@ -1019,7 +1121,7 @@
697 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
698 }
699
700 -static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
701 +static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
702 struct platform_device *atmel_default_console_device; /* the serial console device */
703
704 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
705 @@ -1110,8 +1212,6 @@
706 {
707 if (portnr < ATMEL_MAX_UART)
708 atmel_default_console_device = at91_uarts[portnr];
709 - if (!atmel_default_console_device)
710 - printk(KERN_INFO "AT91: No default serial console defined.\n");
711 }
712
713 void __init at91_add_device_serial(void)
714 @@ -1122,6 +1222,9 @@
715 if (at91_uarts[i])
716 platform_device_register(at91_uarts[i]);
717 }
718 +
719 + if (!atmel_default_console_device)
720 + printk(KERN_INFO "AT91: No default serial console defined.\n");
721 }
722 #else
723 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
724 @@ -1141,6 +1244,7 @@
725 {
726 at91_add_device_rtc();
727 at91_add_device_watchdog();
728 + at91_add_device_tc();
729 return 0;
730 }
731
732 --- a/arch/arm/mach-at91/at91rm9200_time.c
733 +++ b/arch/arm/mach-at91/at91rm9200_time.c
734 @@ -136,8 +136,6 @@
735 u32 alm;
736 int status = 0;
737
738 - BUG_ON(delta < 2);
739 -
740 /* Use "raw" primitives so we behave correctly on RT kernels. */
741 raw_local_irq_save(flags);
742
743 --- a/arch/arm/mach-at91/at91sam9260.c
744 +++ b/arch/arm/mach-at91/at91sam9260.c
745 @@ -11,6 +11,7 @@
746 */
747
748 #include <linux/module.h>
749 +#include <linux/pm.h>
750
751 #include <asm/mach/arch.h>
752 #include <asm/mach/map.h>
753 @@ -18,6 +19,7 @@
754 #include <asm/arch/at91sam9260.h>
755 #include <asm/arch/at91_pmc.h>
756 #include <asm/arch/at91_rstc.h>
757 +#include <asm/arch/at91_shdwc.h>
758
759 #include "generic.h"
760 #include "clock.h"
761 @@ -267,6 +269,11 @@
762 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
763 }
764
765 +static void at91sam9260_poweroff(void)
766 +{
767 + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
768 +}
769 +
770
771 /* --------------------------------------------------------------------
772 * AT91SAM9260 processor initialization
773 @@ -304,6 +311,7 @@
774 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
775
776 at91_arch_reset = at91sam9260_reset;
777 + pm_power_off = at91sam9260_poweroff;
778 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
779 | (1 << AT91SAM9260_ID_IRQ2);
780
781 --- a/arch/arm/mach-at91/at91sam9260_devices.c
782 +++ b/arch/arm/mach-at91/at91sam9260_devices.c
783 @@ -19,8 +19,8 @@
784 #include <asm/arch/board.h>
785 #include <asm/arch/gpio.h>
786 #include <asm/arch/at91sam9260.h>
787 -#include <asm/arch/at91sam926x_mc.h>
788 #include <asm/arch/at91sam9260_matrix.h>
789 +#include <asm/arch/at91sam9_smc.h>
790
791 #include "generic.h"
792
793 @@ -288,10 +288,15 @@
794 #define NAND_BASE AT91_CHIPSELECT_3
795
796 static struct resource nand_resources[] = {
797 - {
798 + [0] = {
799 .start = NAND_BASE,
800 .end = NAND_BASE + SZ_256M - 1,
801 .flags = IORESOURCE_MEM,
802 + },
803 + [1] = {
804 + .start = AT91_BASE_SYS + AT91_ECC,
805 + .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
806 + .flags = IORESOURCE_MEM,
807 }
808 };
809
810 @@ -540,6 +545,90 @@
811
812
813 /* --------------------------------------------------------------------
814 + * Timer/Counter blocks
815 + * -------------------------------------------------------------------- */
816 +
817 +#ifdef CONFIG_ATMEL_TCLIB
818 +
819 +static struct resource tcb0_resources[] = {
820 + [0] = {
821 + .start = AT91SAM9260_BASE_TCB0,
822 + .end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
823 + .flags = IORESOURCE_MEM,
824 + },
825 + [1] = {
826 + .start = AT91SAM9260_ID_TC0,
827 + .end = AT91SAM9260_ID_TC0,
828 + .flags = IORESOURCE_IRQ,
829 + },
830 + [2] = {
831 + .start = AT91SAM9260_ID_TC1,
832 + .end = AT91SAM9260_ID_TC1,
833 + .flags = IORESOURCE_IRQ,
834 + },
835 + [3] = {
836 + .start = AT91SAM9260_ID_TC2,
837 + .end = AT91SAM9260_ID_TC2,
838 + .flags = IORESOURCE_IRQ,
839 + },
840 +};
841 +
842 +static struct platform_device at91sam9260_tcb0_device = {
843 + .name = "atmel_tcb",
844 + .id = 0,
845 + .resource = tcb0_resources,
846 + .num_resources = ARRAY_SIZE(tcb0_resources),
847 +};
848 +
849 +static struct resource tcb1_resources[] = {
850 + [0] = {
851 + .start = AT91SAM9260_BASE_TCB1,
852 + .end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
853 + .flags = IORESOURCE_MEM,
854 + },
855 + [1] = {
856 + .start = AT91SAM9260_ID_TC3,
857 + .end = AT91SAM9260_ID_TC3,
858 + .flags = IORESOURCE_IRQ,
859 + },
860 + [2] = {
861 + .start = AT91SAM9260_ID_TC4,
862 + .end = AT91SAM9260_ID_TC4,
863 + .flags = IORESOURCE_IRQ,
864 + },
865 + [3] = {
866 + .start = AT91SAM9260_ID_TC5,
867 + .end = AT91SAM9260_ID_TC5,
868 + .flags = IORESOURCE_IRQ,
869 + },
870 +};
871 +
872 +static struct platform_device at91sam9260_tcb1_device = {
873 + .name = "atmel_tcb",
874 + .id = 1,
875 + .resource = tcb1_resources,
876 + .num_resources = ARRAY_SIZE(tcb1_resources),
877 +};
878 +
879 +static void __init at91_add_device_tc(void)
880 +{
881 + /* this chip has a separate clock and irq for each TC channel */
882 + at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
883 + at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
884 + at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
885 + platform_device_register(&at91sam9260_tcb0_device);
886 +
887 + at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
888 + at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
889 + at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
890 + platform_device_register(&at91sam9260_tcb1_device);
891 +}
892 +#else
893 +static void __init at91_add_device_tc(void) { }
894 +#endif
895 +
896 +
897 +/* --------------------------------------------------------------------
898 * RTT
899 * -------------------------------------------------------------------- */
900
901 @@ -553,13 +642,14 @@
902
903 static struct platform_device at91sam9260_rtt_device = {
904 .name = "at91_rtt",
905 - .id = -1,
906 + .id = 0,
907 .resource = rtt_resources,
908 .num_resources = ARRAY_SIZE(rtt_resources),
909 };
910
911 static void __init at91_add_device_rtt(void)
912 {
913 + device_init_wakeup(&at91sam9260_rtt_device.dev, 1);
914 platform_device_register(&at91sam9260_rtt_device);
915 }
916
917 @@ -962,7 +1052,7 @@
918 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
919 }
920
921 -static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
922 +static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
923 struct platform_device *atmel_default_console_device; /* the serial console device */
924
925 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
926 @@ -1073,8 +1163,6 @@
927 {
928 if (portnr < ATMEL_MAX_UART)
929 atmel_default_console_device = at91_uarts[portnr];
930 - if (!atmel_default_console_device)
931 - printk(KERN_INFO "AT91: No default serial console defined.\n");
932 }
933
934 void __init at91_add_device_serial(void)
935 @@ -1085,6 +1173,9 @@
936 if (at91_uarts[i])
937 platform_device_register(at91_uarts[i]);
938 }
939 +
940 + if (!atmel_default_console_device)
941 + printk(KERN_INFO "AT91: No default serial console defined.\n");
942 }
943 #else
944 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
945 @@ -1103,6 +1194,7 @@
946 {
947 at91_add_device_rtt();
948 at91_add_device_watchdog();
949 + at91_add_device_tc();
950 return 0;
951 }
952
953 --- a/arch/arm/mach-at91/at91sam9261.c
954 +++ b/arch/arm/mach-at91/at91sam9261.c
955 @@ -11,12 +11,14 @@
956 */
957
958 #include <linux/module.h>
959 +#include <linux/pm.h>
960
961 #include <asm/mach/arch.h>
962 #include <asm/mach/map.h>
963 #include <asm/arch/at91sam9261.h>
964 #include <asm/arch/at91_pmc.h>
965 #include <asm/arch/at91_rstc.h>
966 +#include <asm/arch/at91_shdwc.h>
967
968 #include "generic.h"
969 #include "clock.h"
970 @@ -245,6 +247,11 @@
971 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
972 }
973
974 +static void at91sam9261_poweroff(void)
975 +{
976 + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
977 +}
978 +
979
980 /* --------------------------------------------------------------------
981 * AT91SAM9261 processor initialization
982 @@ -256,6 +263,7 @@
983 iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
984
985 at91_arch_reset = at91sam9261_reset;
986 + pm_power_off = at91sam9261_poweroff;
987 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
988 | (1 << AT91SAM9261_ID_IRQ2);
989
990 --- a/arch/arm/mach-at91/at91sam9261_devices.c
991 +++ b/arch/arm/mach-at91/at91sam9261_devices.c
992 @@ -24,7 +24,7 @@
993 #include <asm/arch/gpio.h>
994 #include <asm/arch/at91sam9261.h>
995 #include <asm/arch/at91sam9261_matrix.h>
996 -#include <asm/arch/at91sam926x_mc.h>
997 +#include <asm/arch/at91sam9_smc.h>
998
999 #include "generic.h"
1000
1001 @@ -548,6 +548,55 @@
1002
1003
1004 /* --------------------------------------------------------------------
1005 + * Timer/Counter block
1006 + * -------------------------------------------------------------------- */
1007 +
1008 +#ifdef CONFIG_ATMEL_TCLIB
1009 +
1010 +static struct resource tcb_resources[] = {
1011 + [0] = {
1012 + .start = AT91SAM9261_BASE_TCB0,
1013 + .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
1014 + .flags = IORESOURCE_MEM,
1015 + },
1016 + [1] = {
1017 + .start = AT91SAM9261_ID_TC0,
1018 + .end = AT91SAM9261_ID_TC0,
1019 + .flags = IORESOURCE_IRQ,
1020 + },
1021 + [2] = {
1022 + .start = AT91SAM9261_ID_TC1,
1023 + .end = AT91SAM9261_ID_TC1,
1024 + .flags = IORESOURCE_IRQ,
1025 + },
1026 + [3] = {
1027 + .start = AT91SAM9261_ID_TC2,
1028 + .end = AT91SAM9261_ID_TC2,
1029 + .flags = IORESOURCE_IRQ,
1030 + },
1031 +};
1032 +
1033 +static struct platform_device at91sam9261_tcb_device = {
1034 + .name = "atmel_tcb",
1035 + .id = 0,
1036 + .resource = tcb_resources,
1037 + .num_resources = ARRAY_SIZE(tcb_resources),
1038 +};
1039 +
1040 +static void __init at91_add_device_tc(void)
1041 +{
1042 + /* this chip has a separate clock and irq for each TC channel */
1043 + at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
1044 + at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
1045 + at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
1046 + platform_device_register(&at91sam9261_tcb_device);
1047 +}
1048 +#else
1049 +static void __init at91_add_device_tc(void) { }
1050 +#endif
1051 +
1052 +
1053 +/* --------------------------------------------------------------------
1054 * RTT
1055 * -------------------------------------------------------------------- */
1056
1057 @@ -561,13 +610,14 @@
1058
1059 static struct platform_device at91sam9261_rtt_device = {
1060 .name = "at91_rtt",
1061 - .id = -1,
1062 + .id = 0,
1063 .resource = rtt_resources,
1064 .num_resources = ARRAY_SIZE(rtt_resources),
1065 };
1066
1067 static void __init at91_add_device_rtt(void)
1068 {
1069 + device_init_wakeup(&at91sam9261_rtt_device.dev, 1);
1070 platform_device_register(&at91sam9261_rtt_device);
1071 }
1072
1073 @@ -938,7 +988,7 @@
1074 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
1075 }
1076
1077 -static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1078 +static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1079 struct platform_device *atmel_default_console_device; /* the serial console device */
1080
1081 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
1082 @@ -1019,8 +1069,6 @@
1083 {
1084 if (portnr < ATMEL_MAX_UART)
1085 atmel_default_console_device = at91_uarts[portnr];
1086 - if (!atmel_default_console_device)
1087 - printk(KERN_INFO "AT91: No default serial console defined.\n");
1088 }
1089
1090 void __init at91_add_device_serial(void)
1091 @@ -1031,6 +1079,9 @@
1092 if (at91_uarts[i])
1093 platform_device_register(at91_uarts[i]);
1094 }
1095 +
1096 + if (!atmel_default_console_device)
1097 + printk(KERN_INFO "AT91: No default serial console defined.\n");
1098 }
1099 #else
1100 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1101 @@ -1050,6 +1101,7 @@
1102 {
1103 at91_add_device_rtt();
1104 at91_add_device_watchdog();
1105 + at91_add_device_tc();
1106 return 0;
1107 }
1108
1109 --- a/arch/arm/mach-at91/at91sam9263.c
1110 +++ b/arch/arm/mach-at91/at91sam9263.c
1111 @@ -11,12 +11,14 @@
1112 */
1113
1114 #include <linux/module.h>
1115 +#include <linux/pm.h>
1116
1117 #include <asm/mach/arch.h>
1118 #include <asm/mach/map.h>
1119 #include <asm/arch/at91sam9263.h>
1120 #include <asm/arch/at91_pmc.h>
1121 #include <asm/arch/at91_rstc.h>
1122 +#include <asm/arch/at91_shdwc.h>
1123
1124 #include "generic.h"
1125 #include "clock.h"
1126 @@ -271,6 +273,11 @@
1127 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
1128 }
1129
1130 +static void at91sam9263_poweroff(void)
1131 +{
1132 + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
1133 +}
1134 +
1135
1136 /* --------------------------------------------------------------------
1137 * AT91SAM9263 processor initialization
1138 @@ -282,6 +289,7 @@
1139 iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
1140
1141 at91_arch_reset = at91sam9263_reset;
1142 + pm_power_off = at91sam9263_poweroff;
1143 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
1144
1145 /* Init clock subsystem */
1146 --- a/arch/arm/mach-at91/at91sam9263_devices.c
1147 +++ b/arch/arm/mach-at91/at91sam9263_devices.c
1148 @@ -22,8 +22,8 @@
1149 #include <asm/arch/board.h>
1150 #include <asm/arch/gpio.h>
1151 #include <asm/arch/at91sam9263.h>
1152 -#include <asm/arch/at91sam926x_mc.h>
1153 #include <asm/arch/at91sam9263_matrix.h>
1154 +#include <asm/arch/at91sam9_smc.h>
1155
1156 #include "generic.h"
1157
1158 @@ -308,7 +308,7 @@
1159 }
1160
1161 mmc0_data = *data;
1162 - at91_clock_associate("mci0_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
1163 + at91_clock_associate("mci0_clk", &at91sam9263_mmc0_device.dev, "mci_clk");
1164 platform_device_register(&at91sam9263_mmc0_device);
1165 } else { /* MCI1 */
1166 /* CLK */
1167 @@ -358,10 +358,15 @@
1168 #define NAND_BASE AT91_CHIPSELECT_3
1169
1170 static struct resource nand_resources[] = {
1171 - {
1172 + [0] = {
1173 .start = NAND_BASE,
1174 .end = NAND_BASE + SZ_256M - 1,
1175 .flags = IORESOURCE_MEM,
1176 + },
1177 + [1] = {
1178 + .start = AT91_BASE_SYS + AT91_ECC0,
1179 + .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
1180 + .flags = IORESOURCE_MEM,
1181 }
1182 };
1183
1184 @@ -783,6 +788,43 @@
1185
1186
1187 /* --------------------------------------------------------------------
1188 + * Timer/Counter block
1189 + * -------------------------------------------------------------------- */
1190 +
1191 +#ifdef CONFIG_ATMEL_TCLIB
1192 +
1193 +static struct resource tcb_resources[] = {
1194 + [0] = {
1195 + .start = AT91SAM9263_BASE_TCB0,
1196 + .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
1197 + .flags = IORESOURCE_MEM,
1198 + },
1199 + [1] = {
1200 + .start = AT91SAM9263_ID_TCB,
1201 + .end = AT91SAM9263_ID_TCB,
1202 + .flags = IORESOURCE_IRQ,
1203 + },
1204 +};
1205 +
1206 +static struct platform_device at91sam9263_tcb_device = {
1207 + .name = "atmel_tcb",
1208 + .id = 0,
1209 + .resource = tcb_resources,
1210 + .num_resources = ARRAY_SIZE(tcb_resources),
1211 +};
1212 +
1213 +static void __init at91_add_device_tc(void)
1214 +{
1215 + /* this chip has one clock and irq for all three TC channels */
1216 + at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
1217 + platform_device_register(&at91sam9263_tcb_device);
1218 +}
1219 +#else
1220 +static void __init at91_add_device_tc(void) { }
1221 +#endif
1222 +
1223 +
1224 +/* --------------------------------------------------------------------
1225 * RTT
1226 * -------------------------------------------------------------------- */
1227
1228 @@ -818,7 +860,9 @@
1229
1230 static void __init at91_add_device_rtt(void)
1231 {
1232 + device_init_wakeup(&at91sam9263_rtt0_device.dev, 1);
1233 platform_device_register(&at91sam9263_rtt0_device);
1234 + device_init_wakeup(&at91sam9263_rtt1_device.dev, 1);
1235 platform_device_register(&at91sam9263_rtt1_device);
1236 }
1237
1238 @@ -933,9 +977,6 @@
1239 }
1240
1241 /*
1242 - * Return the device node so that board init code can use it as the
1243 - * parent for the device node reflecting how it's used on this board.
1244 - *
1245 * SSC controllers are accessed through library code, instead of any
1246 * kind of all-singing/all-dancing driver. For example one could be
1247 * used by a particular I2S audio codec's driver, while another one
1248 @@ -1146,7 +1187,7 @@
1249 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1250 }
1251
1252 -static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1253 +static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1254 struct platform_device *atmel_default_console_device; /* the serial console device */
1255
1256 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
1257 @@ -1227,8 +1268,6 @@
1258 {
1259 if (portnr < ATMEL_MAX_UART)
1260 atmel_default_console_device = at91_uarts[portnr];
1261 - if (!atmel_default_console_device)
1262 - printk(KERN_INFO "AT91: No default serial console defined.\n");
1263 }
1264
1265 void __init at91_add_device_serial(void)
1266 @@ -1239,9 +1278,12 @@
1267 if (at91_uarts[i])
1268 platform_device_register(at91_uarts[i]);
1269 }
1270 +
1271 + if (!atmel_default_console_device)
1272 + printk(KERN_INFO "AT91: No default serial console defined.\n");
1273 }
1274 #else
1275 -void __init at91_init_serial(struct at91_uart_config *config) {}
1276 +void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1277 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1278 void __init at91_set_serial_console(unsigned portnr) {}
1279 void __init at91_add_device_serial(void) {}
1280 @@ -1257,6 +1299,7 @@
1281 {
1282 at91_add_device_rtt();
1283 at91_add_device_watchdog();
1284 + at91_add_device_tc();
1285 return 0;
1286 }
1287
1288 --- a/arch/arm/mach-at91/at91sam926x_time.c
1289 +++ b/arch/arm/mach-at91/at91sam926x_time.c
1290 @@ -1,23 +1,20 @@
1291 /*
1292 - * linux/arch/arm/mach-at91/at91sam926x_time.c
1293 + * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
1294 *
1295 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
1296 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
1297 + * Converted to ClockSource/ClockEvents by David Brownell.
1298 *
1299 * This program is free software; you can redistribute it and/or modify
1300 * it under the terms of the GNU General Public License version 2 as
1301 * published by the Free Software Foundation.
1302 */
1303 -
1304 -#include <linux/init.h>
1305 #include <linux/interrupt.h>
1306 #include <linux/irq.h>
1307 #include <linux/kernel.h>
1308 -#include <linux/sched.h>
1309 -#include <linux/time.h>
1310 +#include <linux/clk.h>
1311 +#include <linux/clockchips.h>
1312
1313 -#include <asm/hardware.h>
1314 -#include <asm/io.h>
1315 #include <asm/mach/time.h>
1316
1317 #include <asm/arch/at91_pit.h>
1318 @@ -26,85 +23,167 @@
1319 #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
1320 #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
1321
1322 +static u32 pit_cycle; /* write-once */
1323 +static u32 pit_cnt; /* access only w/system irq blocked */
1324 +
1325 +
1326 /*
1327 - * Returns number of microseconds since last timer interrupt. Note that interrupts
1328 - * will have been disabled by do_gettimeofday()
1329 - * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
1330 + * Clocksource: just a monotonic counter of MCK/16 cycles.
1331 + * We don't care whether or not PIT irqs are enabled.
1332 */
1333 -static unsigned long at91sam926x_gettimeoffset(void)
1334 +static cycle_t read_pit_clk(void)
1335 {
1336 - unsigned long elapsed;
1337 - unsigned long t = at91_sys_read(AT91_PIT_PIIR);
1338 + unsigned long flags;
1339 + u32 elapsed;
1340 + u32 t;
1341 +
1342 + raw_local_irq_save(flags);
1343 + elapsed = pit_cnt;
1344 + t = at91_sys_read(AT91_PIT_PIIR);
1345 + raw_local_irq_restore(flags);
1346 +
1347 + elapsed += PIT_PICNT(t) * pit_cycle;
1348 + elapsed += PIT_CPIV(t);
1349 + return elapsed;
1350 +}
1351 +
1352 +static struct clocksource pit_clk = {
1353 + .name = "pit",
1354 + .rating = 175,
1355 + .read = read_pit_clk,
1356 + .shift = 20,
1357 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
1358 +};
1359 +
1360
1361 - elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
1362 +/*
1363 + * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
1364 + */
1365 +static void
1366 +pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
1367 +{
1368 + unsigned long flags;
1369
1370 - return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
1371 + switch (mode) {
1372 + case CLOCK_EVT_MODE_PERIODIC:
1373 + /* update clocksource counter, then enable the IRQ */
1374 + raw_local_irq_save(flags);
1375 + pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
1376 + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
1377 + | AT91_PIT_PITIEN);
1378 + raw_local_irq_restore(flags);
1379 + break;
1380 + case CLOCK_EVT_MODE_ONESHOT:
1381 + BUG();
1382 + /* FALLTHROUGH */
1383 + case CLOCK_EVT_MODE_SHUTDOWN:
1384 + case CLOCK_EVT_MODE_UNUSED:
1385 + /* disable irq, leaving the clocksource active */
1386 + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
1387 + break;
1388 + case CLOCK_EVT_MODE_RESUME:
1389 + break;
1390 + }
1391 }
1392
1393 +static struct clock_event_device pit_clkevt = {
1394 + .name = "pit",
1395 + .features = CLOCK_EVT_FEAT_PERIODIC,
1396 + .shift = 32,
1397 + .rating = 100,
1398 + .cpumask = CPU_MASK_CPU0,
1399 + .set_mode = pit_clkevt_mode,
1400 +};
1401 +
1402 +
1403 /*
1404 * IRQ handler for the timer.
1405 */
1406 -static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
1407 +static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
1408 {
1409 - volatile long nr_ticks;
1410
1411 - if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
1412 - /* Get number to ticks performed before interrupt and clear PIT interrupt */
1413 + /* The PIT interrupt may be disabled, and is shared */
1414 + if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
1415 + && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
1416 + unsigned nr_ticks;
1417 +
1418 + /* Get number of ticks performed before irq, and ack it */
1419 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
1420 do {
1421 - timer_tick();
1422 + pit_cnt += pit_cycle;
1423 + pit_clkevt.event_handler(&pit_clkevt);
1424 nr_ticks--;
1425 } while (nr_ticks);
1426
1427 return IRQ_HANDLED;
1428 - } else
1429 - return IRQ_NONE; /* not handled */
1430 + }
1431 +
1432 + return IRQ_NONE;
1433 }
1434
1435 -static struct irqaction at91sam926x_timer_irq = {
1436 +static struct irqaction at91sam926x_pit_irq = {
1437 .name = "at91_tick",
1438 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
1439 - .handler = at91sam926x_timer_interrupt
1440 + .handler = at91sam926x_pit_interrupt
1441 };
1442
1443 -void at91sam926x_timer_reset(void)
1444 +static void at91sam926x_pit_reset(void)
1445 {
1446 - /* Disable timer */
1447 + /* Disable timer and irqs */
1448 at91_sys_write(AT91_PIT_MR, 0);
1449
1450 - /* Clear any pending interrupts */
1451 - (void) at91_sys_read(AT91_PIT_PIVR);
1452 + /* Clear any pending interrupts, wait for PIT to stop counting */
1453 + while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
1454 + cpu_relax();
1455
1456 - /* Set Period Interval timer and enable its interrupt */
1457 - at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
1458 + /* Start PIT but don't enable IRQ */
1459 + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
1460 }
1461
1462 /*
1463 - * Set up timer interrupt.
1464 + * Set up both clocksource and clockevent support.
1465 */
1466 -void __init at91sam926x_timer_init(void)
1467 +static void __init at91sam926x_pit_init(void)
1468 {
1469 + unsigned long pit_rate;
1470 + unsigned bits;
1471 +
1472 + /*
1473 + * Use our actual MCK to figure out how many MCK/16 ticks per
1474 + * 1/HZ period (instead of a compile-time constant LATCH).
1475 + */
1476 + pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
1477 + pit_cycle = (pit_rate + HZ/2) / HZ;
1478 + WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
1479 +
1480 /* Initialize and enable the timer */
1481 - at91sam926x_timer_reset();
1482 + at91sam926x_pit_reset();
1483
1484 - /* Make IRQs happen for the system timer. */
1485 - setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
1486 + /*
1487 + * Register clocksource. The high order bits of PIV are unused,
1488 + * so this isn't a 32-bit counter unless we get clockevent irqs.
1489 + */
1490 + pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
1491 + bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
1492 + pit_clk.mask = CLOCKSOURCE_MASK(bits);
1493 + clocksource_register(&pit_clk);
1494 +
1495 + /* Set up irq handler */
1496 + setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
1497 +
1498 + /* Set up and register clockevents */
1499 + pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
1500 + clockevents_register_device(&pit_clkevt);
1501 }
1502
1503 -#ifdef CONFIG_PM
1504 -static void at91sam926x_timer_suspend(void)
1505 +static void at91sam926x_pit_suspend(void)
1506 {
1507 /* Disable timer */
1508 at91_sys_write(AT91_PIT_MR, 0);
1509 }
1510 -#else
1511 -#define at91sam926x_timer_suspend NULL
1512 -#endif
1513
1514 struct sys_timer at91sam926x_timer = {
1515 - .init = at91sam926x_timer_init,
1516 - .offset = at91sam926x_gettimeoffset,
1517 - .suspend = at91sam926x_timer_suspend,
1518 - .resume = at91sam926x_timer_reset,
1519 + .init = at91sam926x_pit_init,
1520 + .suspend = at91sam926x_pit_suspend,
1521 + .resume = at91sam926x_pit_reset,
1522 };
1523 -
1524 --- a/arch/arm/mach-at91/at91sam9rl.c
1525 +++ b/arch/arm/mach-at91/at91sam9rl.c
1526 @@ -10,6 +10,7 @@
1527 */
1528
1529 #include <linux/module.h>
1530 +#include <linux/pm.h>
1531
1532 #include <asm/mach/arch.h>
1533 #include <asm/mach/map.h>
1534 @@ -17,6 +18,7 @@
1535 #include <asm/arch/at91sam9rl.h>
1536 #include <asm/arch/at91_pmc.h>
1537 #include <asm/arch/at91_rstc.h>
1538 +#include <asm/arch/at91_shdwc.h>
1539
1540 #include "generic.h"
1541 #include "clock.h"
1542 @@ -244,6 +246,11 @@
1543 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
1544 }
1545
1546 +static void at91sam9rl_poweroff(void)
1547 +{
1548 + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
1549 +}
1550 +
1551
1552 /* --------------------------------------------------------------------
1553 * AT91SAM9RL processor initialization
1554 @@ -274,6 +281,7 @@
1555 iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
1556
1557 at91_arch_reset = at91sam9rl_reset;
1558 + pm_power_off = at91sam9rl_poweroff;
1559 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
1560
1561 /* Init clock subsystem */
1562 --- a/arch/arm/mach-at91/at91sam9rl_devices.c
1563 +++ b/arch/arm/mach-at91/at91sam9rl_devices.c
1564 @@ -20,12 +20,107 @@
1565 #include <asm/arch/gpio.h>
1566 #include <asm/arch/at91sam9rl.h>
1567 #include <asm/arch/at91sam9rl_matrix.h>
1568 -#include <asm/arch/at91sam926x_mc.h>
1569 +#include <asm/arch/at91sam9_smc.h>
1570
1571 #include "generic.h"
1572
1573
1574 /* --------------------------------------------------------------------
1575 + * USB HS Device (Gadget)
1576 + * -------------------------------------------------------------------- */
1577 +
1578 +#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
1579 +
1580 +static struct resource usba_udc_resources[] = {
1581 + [0] = {
1582 + .start = AT91SAM9RL_UDPHS_FIFO,
1583 + .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
1584 + .flags = IORESOURCE_MEM,
1585 + },
1586 + [1] = {
1587 + .start = AT91SAM9RL_BASE_UDPHS,
1588 + .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
1589 + .flags = IORESOURCE_MEM,
1590 + },
1591 + [2] = {
1592 + .start = AT91SAM9RL_ID_UDPHS,
1593 + .end = AT91SAM9RL_ID_UDPHS,
1594 + .flags = IORESOURCE_IRQ,
1595 + },
1596 +};
1597 +
1598 +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1599 + [idx] = { \
1600 + .name = nam, \
1601 + .index = idx, \
1602 + .fifo_size = maxpkt, \
1603 + .nr_banks = maxbk, \
1604 + .can_dma = dma, \
1605 + .can_isoc = isoc, \
1606 + }
1607 +
1608 +static struct usba_ep_data usba_udc_ep[] __initdata = {
1609 + EP("ep0", 0, 64, 1, 0, 0),
1610 + EP("ep1", 1, 1024, 2, 1, 1),
1611 + EP("ep2", 2, 1024, 2, 1, 1),
1612 + EP("ep3", 3, 1024, 3, 1, 0),
1613 + EP("ep4", 4, 1024, 3, 1, 0),
1614 + EP("ep5", 5, 1024, 3, 1, 1),
1615 + EP("ep6", 6, 1024, 3, 1, 1),
1616 +};
1617 +
1618 +#undef EP
1619 +
1620 +/*
1621 + * pdata doesn't have room for any endpoints, so we need to
1622 + * append room for the ones we need right after it.
1623 + */
1624 +static struct {
1625 + struct usba_platform_data pdata;
1626 + struct usba_ep_data ep[7];
1627 +} usba_udc_data;
1628 +
1629 +static struct platform_device at91_usba_udc_device = {
1630 + .name = "atmel_usba_udc",
1631 + .id = -1,
1632 + .dev = {
1633 + .platform_data = &usba_udc_data.pdata,
1634 + },
1635 + .resource = usba_udc_resources,
1636 + .num_resources = ARRAY_SIZE(usba_udc_resources),
1637 +};
1638 +
1639 +void __init at91_add_device_usba(struct usba_platform_data *data)
1640 +{
1641 + /*
1642 + * Invalid pins are 0 on AT91, but the usba driver is shared
1643 + * with AVR32, which use negative values instead. Once/if
1644 + * gpio_is_valid() is ported to AT91, revisit this code.
1645 + */
1646 + usba_udc_data.pdata.vbus_pin = -EINVAL;
1647 + usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
1648 + memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
1649 +
1650 + if (data && data->vbus_pin > 0) {
1651 + at91_set_gpio_input(data->vbus_pin, 0);
1652 + at91_set_deglitch(data->vbus_pin, 1);
1653 + usba_udc_data.pdata.vbus_pin = data->vbus_pin;
1654 + }
1655 +
1656 + /* Pullup pin is handled internally by USB device peripheral */
1657 +
1658 + /* Clocks */
1659 + at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
1660 + at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
1661 +
1662 + platform_device_register(&at91_usba_udc_device);
1663 +}
1664 +#else
1665 +void __init at91_add_device_usba(struct usba_platform_data *data) {}
1666 +#endif
1667 +
1668 +
1669 +/* --------------------------------------------------------------------
1670 * MMC / SD
1671 * -------------------------------------------------------------------- */
1672
1673 @@ -105,10 +200,15 @@
1674 #define NAND_BASE AT91_CHIPSELECT_3
1675
1676 static struct resource nand_resources[] = {
1677 - {
1678 + [0] = {
1679 .start = NAND_BASE,
1680 .end = NAND_BASE + SZ_256M - 1,
1681 .flags = IORESOURCE_MEM,
1682 + },
1683 + [1] = {
1684 + .start = AT91_BASE_SYS + AT91_ECC,
1685 + .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
1686 + .flags = IORESOURCE_MEM,
1687 }
1688 };
1689
1690 @@ -385,6 +485,100 @@
1691
1692
1693 /* --------------------------------------------------------------------
1694 + * Timer/Counter block
1695 + * -------------------------------------------------------------------- */
1696 +
1697 +#ifdef CONFIG_ATMEL_TCLIB
1698 +
1699 +static struct resource tcb_resources[] = {
1700 + [0] = {
1701 + .start = AT91SAM9RL_BASE_TCB0,
1702 + .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
1703 + .flags = IORESOURCE_MEM,
1704 + },
1705 + [1] = {
1706 + .start = AT91SAM9RL_ID_TC0,
1707 + .end = AT91SAM9RL_ID_TC0,
1708 + .flags = IORESOURCE_IRQ,
1709 + },
1710 + [2] = {
1711 + .start = AT91SAM9RL_ID_TC1,
1712 + .end = AT91SAM9RL_ID_TC1,
1713 + .flags = IORESOURCE_IRQ,
1714 + },
1715 + [3] = {
1716 + .start = AT91SAM9RL_ID_TC2,
1717 + .end = AT91SAM9RL_ID_TC2,
1718 + .flags = IORESOURCE_IRQ,
1719 + },
1720 +};
1721 +
1722 +static struct platform_device at91sam9rl_tcb_device = {
1723 + .name = "atmel_tcb",
1724 + .id = 0,
1725 + .resource = tcb_resources,
1726 + .num_resources = ARRAY_SIZE(tcb_resources),
1727 +};
1728 +
1729 +static void __init at91_add_device_tc(void)
1730 +{
1731 + /* this chip has a separate clock and irq for each TC channel */
1732 + at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
1733 + at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
1734 + at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
1735 + platform_device_register(&at91sam9rl_tcb_device);
1736 +}
1737 +#else
1738 +static void __init at91_add_device_tc(void) { }
1739 +#endif
1740 +
1741 +
1742 +/* --------------------------------------------------------------------
1743 + * Touchscreen
1744 + * -------------------------------------------------------------------- */
1745 +
1746 +#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1747 +static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1748 +
1749 +static struct resource tsadcc_resources[] = {
1750 + [0] = {
1751 + .start = AT91SAM9RL_BASE_TSC,
1752 + .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
1753 + .flags = IORESOURCE_MEM,
1754 + },
1755 + [1] = {
1756 + .start = AT91SAM9RL_ID_TSC,
1757 + .end = AT91SAM9RL_ID_TSC,
1758 + .flags = IORESOURCE_IRQ,
1759 + }
1760 +};
1761 +
1762 +static struct platform_device at91_tsadcc_device = {
1763 + .name = "atmel_tsadcc",
1764 + .id = -1,
1765 + .dev = {
1766 + .dma_mask = &tsadcc_dmamask,
1767 + .coherent_dma_mask = DMA_BIT_MASK(32),
1768 + },
1769 + .resource = tsadcc_resources,
1770 + .num_resources = ARRAY_SIZE(tsadcc_resources),
1771 +};
1772 +
1773 +void __init at91_add_device_tsadcc(void)
1774 +{
1775 + at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
1776 + at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
1777 + at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
1778 + at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
1779 +
1780 + platform_device_register(&at91_tsadcc_device);
1781 +}
1782 +#else
1783 +void __init at91_add_device_tsadcc(void) {}
1784 +#endif
1785 +
1786 +
1787 +/* --------------------------------------------------------------------
1788 * RTC
1789 * -------------------------------------------------------------------- */
1790
1791 @@ -397,6 +591,7 @@
1792
1793 static void __init at91_add_device_rtc(void)
1794 {
1795 + device_init_wakeup(&at91sam9rl_rtc_device.dev, 1);
1796 platform_device_register(&at91sam9rl_rtc_device);
1797 }
1798 #else
1799 @@ -418,13 +613,14 @@
1800
1801 static struct platform_device at91sam9rl_rtt_device = {
1802 .name = "at91_rtt",
1803 - .id = -1,
1804 + .id = 0,
1805 .resource = rtt_resources,
1806 .num_resources = ARRAY_SIZE(rtt_resources),
1807 };
1808
1809 static void __init at91_add_device_rtt(void)
1810 {
1811 + device_init_wakeup(&at91sam9rl_rtt_device.dev, 1);
1812 platform_device_register(&at91sam9rl_rtt_device);
1813 }
1814
1815 @@ -539,9 +735,6 @@
1816 }
1817
1818 /*
1819 - * Return the device node so that board init code can use it as the
1820 - * parent for the device node reflecting how it's used on this board.
1821 - *
1822 * SSC controllers are accessed through library code, instead of any
1823 * kind of all-singing/all-dancing driver. For example one could be
1824 * used by a particular I2S audio codec's driver, while another one
1825 @@ -802,7 +995,7 @@
1826 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1827 }
1828
1829 -static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1830 +static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1831 struct platform_device *atmel_default_console_device; /* the serial console device */
1832
1833 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
1834 @@ -893,8 +1086,6 @@
1835 {
1836 if (portnr < ATMEL_MAX_UART)
1837 atmel_default_console_device = at91_uarts[portnr];
1838 - if (!atmel_default_console_device)
1839 - printk(KERN_INFO "AT91: No default serial console defined.\n");
1840 }
1841
1842 void __init at91_add_device_serial(void)
1843 @@ -905,6 +1096,9 @@
1844 if (at91_uarts[i])
1845 platform_device_register(at91_uarts[i]);
1846 }
1847 +
1848 + if (!atmel_default_console_device)
1849 + printk(KERN_INFO "AT91: No default serial console defined.\n");
1850 }
1851 #else
1852 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1853 @@ -925,6 +1119,7 @@
1854 at91_add_device_rtc();
1855 at91_add_device_rtt();
1856 at91_add_device_watchdog();
1857 + at91_add_device_tc();
1858 return 0;
1859 }
1860
1861 --- /dev/null
1862 +++ b/arch/arm/mach-at91/board-cam60.c
1863 @@ -0,0 +1,180 @@
1864 +/*
1865 + * KwikByte CAM60 (KB9260)
1866 + *
1867 + * based on board-sam9260ek.c
1868 + * Copyright (C) 2005 SAN People
1869 + * Copyright (C) 2006 Atmel
1870 + *
1871 + * This program is free software; you can redistribute it and/or modify
1872 + * it under the terms of the GNU General Public License as published by
1873 + * the Free Software Foundation; either version 2 of the License, or
1874 + * (at your option) any later version.
1875 + *
1876 + * This program is distributed in the hope that it will be useful,
1877 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1878 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1879 + * GNU General Public License for more details.
1880 + *
1881 + * You should have received a copy of the GNU General Public License
1882 + * along with this program; if not, write to the Free Software
1883 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1884 + */
1885 +
1886 +#include <linux/types.h>
1887 +#include <linux/init.h>
1888 +#include <linux/mm.h>
1889 +#include <linux/module.h>
1890 +#include <linux/platform_device.h>
1891 +#include <linux/spi/spi.h>
1892 +#include <linux/spi/flash.h>
1893 +
1894 +#include <asm/hardware.h>
1895 +#include <asm/setup.h>
1896 +#include <asm/mach-types.h>
1897 +#include <asm/irq.h>
1898 +
1899 +#include <asm/mach/arch.h>
1900 +#include <asm/mach/map.h>
1901 +#include <asm/mach/irq.h>
1902 +
1903 +#include <asm/arch/board.h>
1904 +#include <asm/arch/gpio.h>
1905 +
1906 +#include "generic.h"
1907 +
1908 +
1909 +static void __init cam60_map_io(void)
1910 +{
1911 + /* Initialize processor: 10 MHz crystal */
1912 + at91sam9260_initialize(10000000);
1913 +
1914 + /* DGBU on ttyS0. (Rx & Tx only) */
1915 + at91_register_uart(0, 0, 0);
1916 +
1917 + /* set serial console to ttyS0 (ie, DBGU) */
1918 + at91_set_serial_console(0);
1919 +}
1920 +
1921 +static void __init cam60_init_irq(void)
1922 +{
1923 + at91sam9260_init_interrupts(NULL);
1924 +}
1925 +
1926 +
1927 +/*
1928 + * USB Host
1929 + */
1930 +static struct at91_usbh_data __initdata cam60_usbh_data = {
1931 + .ports = 1,
1932 +};
1933 +
1934 +
1935 +/*
1936 + * SPI devices.
1937 + */
1938 +#if defined(CONFIG_MTD_DATAFLASH)
1939 +static struct mtd_partition __initdata cam60_spi_partitions[] = {
1940 + {
1941 + .name = "BOOT1",
1942 + .offset = 0,
1943 + .size = 4 * 1056,
1944 + },
1945 + {
1946 + .name = "BOOT2",
1947 + .offset = MTDPART_OFS_NXTBLK,
1948 + .size = 256 * 1056,
1949 + },
1950 + {
1951 + .name = "kernel",
1952 + .offset = MTDPART_OFS_NXTBLK,
1953 + .size = 2222 * 1056,
1954 + },
1955 + {
1956 + .name = "file system",
1957 + .offset = MTDPART_OFS_NXTBLK,
1958 + .size = MTDPART_SIZ_FULL,
1959 + },
1960 +};
1961 +
1962 +static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
1963 + .name = "spi_flash",
1964 + .parts = cam60_spi_partitions,
1965 + .nr_parts = ARRAY_SIZE(cam60_spi_partitions)
1966 +};
1967 +#endif
1968 +
1969 +static struct spi_board_info cam60_spi_devices[] = {
1970 +#if defined(CONFIG_MTD_DATAFLASH)
1971 + { /* DataFlash chip */
1972 + .modalias = "mtd_dataflash",
1973 + .chip_select = 0,
1974 + .max_speed_hz = 15 * 1000 * 1000,
1975 + .bus_num = 0,
1976 + .platform_data = &cam60_spi_flash_platform_data
1977 + },
1978 +#endif
1979 +};
1980 +
1981 +
1982 +/*
1983 + * MACB Ethernet device
1984 + */
1985 +static struct __initdata at91_eth_data cam60_macb_data = {
1986 + .phy_irq_pin = AT91_PIN_PB5,
1987 + .is_rmii = 0,
1988 +};
1989 +
1990 +
1991 +/*
1992 + * NAND Flash
1993 + */
1994 +static struct mtd_partition __initdata cam60_nand_partition[] = {
1995 + {
1996 + .name = "nand_fs",
1997 + .offset = 0,
1998 + .size = MTDPART_SIZ_FULL,
1999 + },
2000 +};
2001 +
2002 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
2003 +{
2004 + *num_partitions = ARRAY_SIZE(cam60_nand_partition);
2005 + return cam60_nand_partition;
2006 +}
2007 +
2008 +static struct at91_nand_data __initdata cam60_nand_data = {
2009 + .ale = 21,
2010 + .cle = 22,
2011 + // .det_pin = ... not there
2012 + .rdy_pin = AT91_PIN_PA9,
2013 + .enable_pin = AT91_PIN_PA7,
2014 + .partition_info = nand_partitions,
2015 +};
2016 +
2017 +
2018 +static void __init cam60_board_init(void)
2019 +{
2020 + /* Serial */
2021 + at91_add_device_serial();
2022 + /* SPI */
2023 + at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
2024 + /* Ethernet */
2025 + at91_add_device_eth(&cam60_macb_data);
2026 + /* USB Host */
2027 + /* enable USB power supply circuit */
2028 + at91_set_gpio_output(AT91_PIN_PB18, 1);
2029 + at91_add_device_usbh(&cam60_usbh_data);
2030 + /* NAND */
2031 + at91_add_device_nand(&cam60_nand_data);
2032 +}
2033 +
2034 +MACHINE_START(CAM60, "KwikByte CAM60")
2035 + /* Maintainer: KwikByte */
2036 + .phys_io = AT91_BASE_SYS,
2037 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2038 + .boot_params = AT91_SDRAM_BASE + 0x100,
2039 + .timer = &at91sam926x_timer,
2040 + .map_io = cam60_map_io,
2041 + .init_irq = cam60_init_irq,
2042 + .init_machine = cam60_board_init,
2043 +MACHINE_END
2044 --- a/arch/arm/mach-at91/board-cap9adk.c
2045 +++ b/arch/arm/mach-at91/board-cap9adk.c
2046 @@ -36,16 +36,14 @@
2047 #include <asm/hardware.h>
2048 #include <asm/setup.h>
2049 #include <asm/mach-types.h>
2050 -#include <asm/irq.h>
2051
2052 #include <asm/mach/arch.h>
2053 #include <asm/mach/map.h>
2054 -#include <asm/mach/irq.h>
2055
2056 #include <asm/arch/board.h>
2057 #include <asm/arch/gpio.h>
2058 #include <asm/arch/at91cap9_matrix.h>
2059 -#include <asm/arch/at91sam926x_mc.h>
2060 +#include <asm/arch/at91sam9_smc.h>
2061
2062 #include "generic.h"
2063
2064 @@ -78,6 +76,12 @@
2065 .ports = 2,
2066 };
2067
2068 +/*
2069 + * USB HS Device port
2070 + */
2071 +static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
2072 + .vbus_pin = AT91_PIN_PB31,
2073 +};
2074
2075 /*
2076 * ADS7846 Touchscreen
2077 @@ -130,7 +134,7 @@
2078 {
2079 .modalias = "ads7846",
2080 .chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
2081 - .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
2082 + .max_speed_hz = 125000 * 16, /* max sample rate * clocks per sample */
2083 .bus_num = 0,
2084 .platform_data = &ads_info,
2085 .irq = AT91_PIN_PC4,
2086 @@ -324,8 +328,9 @@
2087 /* Serial */
2088 at91_add_device_serial();
2089 /* USB Host */
2090 - set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
2091 at91_add_device_usbh(&cap9adk_usbh_data);
2092 + /* USB HS */
2093 + at91_add_device_usba(&cap9adk_usba_udc_data);
2094 /* SPI */
2095 at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
2096 /* Touchscreen */
2097 @@ -341,7 +346,6 @@
2098 /* I2C */
2099 at91_add_device_i2c(NULL, 0);
2100 /* LCD Controller */
2101 - set_irq_type(AT91CAP9_ID_LCDC, IRQT_HIGH);
2102 at91_add_device_lcdc(&cap9adk_lcdc_data);
2103 /* AC97 */
2104 at91_add_device_ac97(&cap9adk_ac97_data);
2105 --- a/arch/arm/mach-at91/board-carmeva.c
2106 +++ b/arch/arm/mach-at91/board-carmeva.c
2107 @@ -40,24 +40,21 @@
2108 #include "generic.h"
2109
2110
2111 -/*
2112 - * Serial port configuration.
2113 - * 0 .. 3 = USART0 .. USART3
2114 - * 4 = DBGU
2115 - */
2116 -static struct at91_uart_config __initdata carmeva_uart_config = {
2117 - .console_tty = 0, /* ttyS0 */
2118 - .nr_tty = 2,
2119 - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
2120 -};
2121 -
2122 static void __init carmeva_map_io(void)
2123 {
2124 /* Initialize processor: 20.000 MHz crystal */
2125 at91rm9200_initialize(20000000, AT91RM9200_BGA);
2126
2127 - /* Setup the serial ports and console */
2128 - at91_init_serial(&carmeva_uart_config);
2129 + /* DBGU on ttyS0. (Rx & Tx only) */
2130 + at91_register_uart(0, 0, 0);
2131 +
2132 + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
2133 + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
2134 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
2135 + | ATMEL_UART_RI);
2136 +
2137 + /* set serial console to ttyS0 (ie, DBGU) */
2138 + at91_set_serial_console(0);
2139 }
2140
2141 static void __init carmeva_init_irq(void)
2142 @@ -117,6 +114,30 @@
2143 },
2144 };
2145
2146 +static struct gpio_led carmeva_leds[] = {
2147 + { /* "user led 1", LED9 */
2148 + .name = "led9",
2149 + .gpio = AT91_PIN_PA21,
2150 + .active_low = 1,
2151 + .default_trigger = "heartbeat",
2152 + },
2153 + { /* "user led 2", LED10 */
2154 + .name = "led10",
2155 + .gpio = AT91_PIN_PA25,
2156 + .active_low = 1,
2157 + },
2158 + { /* "user led 3", LED11 */
2159 + .name = "led11",
2160 + .gpio = AT91_PIN_PA26,
2161 + .active_low = 1,
2162 + },
2163 + { /* "user led 4", LED12 */
2164 + .name = "led12",
2165 + .gpio = AT91_PIN_PA18,
2166 + .active_low = 1,
2167 + }
2168 +};
2169 +
2170 static void __init carmeva_board_init(void)
2171 {
2172 /* Serial */
2173 @@ -135,6 +156,8 @@
2174 // at91_add_device_cf(&carmeva_cf_data);
2175 /* MMC */
2176 at91_add_device_mmc(0, &carmeva_mmc_data);
2177 + /* LEDs */
2178 + at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
2179 }
2180
2181 MACHINE_START(CARMEVA, "Carmeva")
2182 --- /dev/null
2183 +++ b/arch/arm/mach-at91/board-chub.c
2184 @@ -0,0 +1,132 @@
2185 +/*
2186 + * linux/arch/arm/mach-at91/board-chub.c
2187 + *
2188 + * Copyright (C) 2005 SAN People, adapted for Promwad Chub board
2189 + * by Kuten Ivan
2190 + *
2191 + * This program is free software; you can redistribute it and/or modify
2192 + * it under the terms of the GNU General Public License as published by
2193 + * the Free Software Foundation; either version 2 of the License, or
2194 + * (at your option) any later version.
2195 + *
2196 + * This program is distributed in the hope that it will be useful,
2197 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2198 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2199 + * GNU General Public License for more details.
2200 + *
2201 + * You should have received a copy of the GNU General Public License
2202 + * along with this program; if not, write to the Free Software
2203 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2204 + */
2205 +
2206 +#include <linux/types.h>
2207 +#include <linux/init.h>
2208 +#include <linux/mm.h>
2209 +#include <linux/module.h>
2210 +#include <linux/platform_device.h>
2211 +
2212 +#include <asm/hardware.h>
2213 +#include <asm/setup.h>
2214 +#include <asm/mach-types.h>
2215 +#include <asm/irq.h>
2216 +
2217 +#include <asm/mach/arch.h>
2218 +#include <asm/mach/map.h>
2219 +#include <asm/mach/irq.h>
2220 +
2221 +#include <asm/arch/board.h>
2222 +#include <asm/arch/gpio.h>
2223 +
2224 +#include "generic.h"
2225 +
2226 +/*
2227 + * Serial port configuration.
2228 + * 0 .. 3 = USART0 .. USART3
2229 + * 4 = DBGU
2230 + */
2231 +static struct at91_uart_config __initdata chub_uart_config = {
2232 + .console_tty = 0, /* ttyS0 */
2233 + .nr_tty = 5,
2234 + .tty_map = { 4, 0, 1, 2, 3 } /* ttyS0, ..., ttyS4 */
2235 +};
2236 +
2237 +static void __init chub_init_irq(void)
2238 +{
2239 + at91rm9200_init_interrupts(NULL);
2240 +}
2241 +
2242 +static void __init chub_map_io(void)
2243 +{
2244 + /* Initialize clocks: 18.432 MHz crystal */
2245 + at91rm9200_initialize(18432000, AT91RM9200_PQFP);
2246 +
2247 + /* Setup the serial ports and console */
2248 + at91_init_serial(&chub_uart_config);
2249 +}
2250 +
2251 +static struct at91_eth_data __initdata chub_eth_data = {
2252 + .phy_irq_pin = AT91_PIN_PB29,
2253 + .is_rmii = 0,
2254 +};
2255 +
2256 +static struct mtd_partition __initdata chub_nand_partition[] = {
2257 + {
2258 + .name = "NAND Partition 1",
2259 + .offset = 0,
2260 + .size = MTDPART_SIZ_FULL,
2261 + },
2262 +};
2263 +
2264 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
2265 +{
2266 + *num_partitions = ARRAY_SIZE(chub_nand_partition);
2267 + return chub_nand_partition;
2268 +}
2269 +
2270 +static struct at91_nand_data __initdata chub_nand_data = {
2271 + .ale = 22,
2272 + .cle = 21,
2273 + .enable_pin = AT91_PIN_PA27,
2274 + .partition_info = nand_partitions,
2275 +};
2276 +
2277 +static struct spi_board_info chub_spi_devices[] = {
2278 + { /* DataFlash chip */
2279 + .modalias = "mtd_dataflash",
2280 + .chip_select = 0,
2281 + .max_speed_hz = 15 * 1000 * 1000,
2282 + },
2283 +};
2284 +
2285 +static void __init chub_board_init(void)
2286 +{
2287 + /* Serial */
2288 + at91_add_device_serial();
2289 + /* I2C */
2290 + at91_add_device_i2c(NULL, 0);
2291 + /* Ethernet */
2292 + at91_add_device_eth(&chub_eth_data);
2293 + /* SPI */
2294 + at91_add_device_spi(chub_spi_devices, ARRAY_SIZE(chub_spi_devices));
2295 + /* NAND Flash */
2296 + at91_add_device_nand(&chub_nand_data);
2297 + /* Disable write protect for NAND */
2298 + at91_set_gpio_output(AT91_PIN_PB7, 1);
2299 + /* Power enable for 3x RS-232 and 1x RS-485 */
2300 + at91_set_gpio_output(AT91_PIN_PB9, 1);
2301 + /* Disable write protect for FRAM */
2302 + at91_set_gpio_output(AT91_PIN_PA21, 1);
2303 + /* Disable write protect for Dataflash */
2304 + at91_set_gpio_output(AT91_PIN_PA19, 1);
2305 +}
2306 +
2307 +MACHINE_START(CHUB, "Promwad Chub")
2308 + /* Maintainer: Ivan Kuten AT Promwad DOT com */
2309 + .phys_io = AT91_BASE_SYS,
2310 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2311 + .boot_params = AT91_SDRAM_BASE + 0x100,
2312 + .timer = &at91rm9200_timer,
2313 + .map_io = chub_map_io,
2314 + .init_irq = chub_init_irq,
2315 + .init_machine = chub_board_init,
2316 +MACHINE_END
2317 --- a/arch/arm/mach-at91/board-csb337.c
2318 +++ b/arch/arm/mach-at91/board-csb337.c
2319 @@ -61,6 +61,7 @@
2320
2321 /* Setup the LEDs */
2322 at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
2323 + at91_set_gpio_output(AT91_PIN_PB2, 1); /* third (unused) LED */
2324
2325 /* Setup the serial ports and console */
2326 at91_init_serial(&csb337_uart_config);
2327 @@ -202,11 +203,11 @@
2328
2329 static void __init csb300_add_device_buttons(void)
2330 {
2331 - at91_set_gpio_input(AT91_PIN_PB29, 0); /* sw0 */
2332 + at91_set_gpio_input(AT91_PIN_PB29, 1); /* sw0 */
2333 at91_set_deglitch(AT91_PIN_PB29, 1);
2334 - at91_set_gpio_input(AT91_PIN_PB28, 0); /* sw1 */
2335 + at91_set_gpio_input(AT91_PIN_PB28, 1); /* sw1 */
2336 at91_set_deglitch(AT91_PIN_PB28, 1);
2337 - at91_set_gpio_input(AT91_PIN_PA21, 0); /* sw2 */
2338 + at91_set_gpio_input(AT91_PIN_PA21, 1); /* sw2 */
2339 at91_set_deglitch(AT91_PIN_PA21, 1);
2340
2341 platform_device_register(&csb300_button_device);
2342 @@ -233,7 +234,7 @@
2343 .gpio = AT91_PIN_PB0,
2344 .active_low = 1,
2345 .default_trigger = "ide-disk",
2346 - },
2347 + }
2348 };
2349
2350
2351 --- a/arch/arm/mach-at91/board-csb637.c
2352 +++ b/arch/arm/mach-at91/board-csb637.c
2353 @@ -40,27 +40,16 @@
2354 #include "generic.h"
2355
2356
2357 -/*
2358 - * Serial port configuration.
2359 - * 0 .. 3 = USART0 .. USART3
2360 - * 4 = DBGU
2361 - */
2362 -static struct at91_uart_config __initdata csb637_uart_config = {
2363 - .console_tty = 0, /* ttyS0 */
2364 - .nr_tty = 2,
2365 - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
2366 -};
2367 -
2368 static void __init csb637_map_io(void)
2369 {
2370 /* Initialize processor: 3.6864 MHz crystal */
2371 at91rm9200_initialize(3686400, AT91RM9200_BGA);
2372
2373 - /* Setup the LEDs */
2374 - at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
2375 + /* DBGU on ttyS0. (Rx & Tx only) */
2376 + at91_register_uart(0, 0, 0);
2377
2378 - /* Setup the serial ports and console */
2379 - at91_init_serial(&csb637_uart_config);
2380 + /* make console=ttyS0 (ie, DBGU) the default */
2381 + at91_set_serial_console(0);
2382 }
2383
2384 static void __init csb637_init_irq(void)
2385 @@ -118,8 +107,19 @@
2386 .num_resources = ARRAY_SIZE(csb_flash_resources),
2387 };
2388
2389 +static struct gpio_led csb_leds[] = {
2390 + { /* "d1", red */
2391 + .name = "d1",
2392 + .gpio = AT91_PIN_PB2,
2393 + .active_low = 1,
2394 + .default_trigger = "heartbeat",
2395 + }
2396 +};
2397 +
2398 static void __init csb637_board_init(void)
2399 {
2400 + /* LED(s) */
2401 + at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
2402 /* Serial */
2403 at91_add_device_serial();
2404 /* Ethernet */
2405 --- a/arch/arm/mach-at91/board-dk.c
2406 +++ b/arch/arm/mach-at91/board-dk.c
2407 @@ -25,6 +25,7 @@
2408 #include <linux/init.h>
2409 #include <linux/mm.h>
2410 #include <linux/module.h>
2411 +#include <linux/dma-mapping.h>
2412 #include <linux/platform_device.h>
2413 #include <linux/spi/spi.h>
2414 #include <linux/mtd/physmap.h>
2415 @@ -45,17 +46,6 @@
2416 #include "generic.h"
2417
2418
2419 -/*
2420 - * Serial port configuration.
2421 - * 0 .. 3 = USART0 .. USART3
2422 - * 4 = DBGU
2423 - */
2424 -static struct at91_uart_config __initdata dk_uart_config = {
2425 - .console_tty = 0, /* ttyS0 */
2426 - .nr_tty = 2,
2427 - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
2428 -};
2429 -
2430 static void __init dk_map_io(void)
2431 {
2432 /* Initialize processor: 18.432 MHz crystal */
2433 @@ -64,8 +54,16 @@
2434 /* Setup the LEDs */
2435 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
2436
2437 - /* Setup the serial ports and console */
2438 - at91_init_serial(&dk_uart_config);
2439 + /* DBGU on ttyS0. (Rx & Tx only) */
2440 + at91_register_uart(0, 0, 0);
2441 +
2442 + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
2443 + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
2444 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
2445 + | ATMEL_UART_RI);
2446 +
2447 + /* set serial console to ttyS0 (ie, DBGU) */
2448 + at91_set_serial_console(0);
2449 }
2450
2451 static void __init dk_init_irq(void)
2452 @@ -73,6 +71,185 @@
2453 at91rm9200_init_interrupts(NULL);
2454 }
2455
2456 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
2457 +#include <video/s1d13xxxfb.h>
2458 +#include <asm/arch/ics1523.h>
2459 +
2460 +/* EPSON S1D13806 FB */
2461 +#define AT91_FB_REG_BASE 0x30000000L
2462 +#define AT91_FB_REG_SIZE 0x200
2463 +#define AT91_FB_VMEM_BASE 0x30200000L
2464 +#define AT91_FB_VMEM_SIZE 0x140000L
2465 +
2466 +static void dk_init_video(void)
2467 +{
2468 + /* NWAIT Signal */
2469 + at91_set_A_periph(AT91_PIN_PC6, 0);
2470 +
2471 + /* Initialization of the Static Memory Controller for Chip Select 2 */
2472 + at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
2473 + | AT91_SMC_WSEN | AT91_SMC_NWS_(4) /* wait states */
2474 + | AT91_SMC_TDF_(1) /* float time */
2475 + );
2476 +
2477 + at91_ics1523_init();
2478 +}
2479 +
2480 +/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz)
2481 + Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
2482 +static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = {
2483 + {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */
2484 + {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */
2485 + {S1DREG_GPIO_CNF0, 0x00},
2486 + {S1DREG_GPIO_CNF1, 0x00},
2487 + {S1DREG_GPIO_CTL0, 0x08},
2488 + {S1DREG_GPIO_CTL1, 0x00},
2489 + {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/
2490 + {S1DREG_LCD_CLK_CNF, 0x00},
2491 + {S1DREG_CRT_CLK_CNF, 0x00},
2492 + {S1DREG_MPLUG_CLK_CNF, 0x00},
2493 + {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */
2494 + {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */
2495 + {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */
2496 + {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */
2497 + {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */
2498 + {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
2499 + {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */
2500 + {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */
2501 + {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */
2502 + {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */
2503 + {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */
2504 + {S1DREG_LCD_DISP_VHEIGHT0, 0xDF},
2505 + {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2506 + {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */
2507 + {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */
2508 + {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */
2509 + {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */
2510 + {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */
2511 + {S1DREG_LCD_DISP_START0, 0x00},
2512 + {S1DREG_LCD_DISP_START1, 0xC8},
2513 + {S1DREG_LCD_DISP_START2, 0x00},
2514 + {S1DREG_LCD_MEM_OFF0, 0x80},
2515 + {S1DREG_LCD_MEM_OFF1, 0x02},
2516 + {S1DREG_LCD_PIX_PAN, 0x00},
2517 + {S1DREG_LCD_DISP_FIFO_HTC, 0x3B},
2518 + {S1DREG_LCD_DISP_FIFO_LTC, 0x3C},
2519 + {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */
2520 + {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */
2521 + {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */
2522 + {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */
2523 + {S1DREG_CRT_DISP_VHEIGHT0, 0xDF},
2524 + {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2525 + {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */
2526 + {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */
2527 + {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */
2528 + {S1DREG_TV_OUT_CTL, 0x10},
2529 + {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */
2530 + {S1DREG_CRT_DISP_START0, 0x00},
2531 + {S1DREG_CRT_DISP_START1, 0x00},
2532 + {S1DREG_CRT_DISP_START2, 0x00},
2533 + {S1DREG_CRT_MEM_OFF0, 0x80},
2534 + {S1DREG_CRT_MEM_OFF1, 0x02},
2535 + {S1DREG_CRT_PIX_PAN, 0x00},
2536 + {S1DREG_CRT_DISP_FIFO_HTC, 0x3B},
2537 + {S1DREG_CRT_DISP_FIFO_LTC, 0x3C},
2538 + {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */
2539 + {S1DREG_LCD_CUR_START, 0x01},
2540 + {S1DREG_LCD_CUR_XPOS0, 0x00},
2541 + {S1DREG_LCD_CUR_XPOS1, 0x00},
2542 + {S1DREG_LCD_CUR_YPOS0, 0x00},
2543 + {S1DREG_LCD_CUR_YPOS1, 0x00},
2544 + {S1DREG_LCD_CUR_BCTL0, 0x00},
2545 + {S1DREG_LCD_CUR_GCTL0, 0x00},
2546 + {S1DREG_LCD_CUR_RCTL0, 0x00},
2547 + {S1DREG_LCD_CUR_BCTL1, 0x1F},
2548 + {S1DREG_LCD_CUR_GCTL1, 0x3F},
2549 + {S1DREG_LCD_CUR_RCTL1, 0x1F},
2550 + {S1DREG_LCD_CUR_FIFO_HTC, 0x00},
2551 + {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */
2552 + {S1DREG_CRT_CUR_START, 0x01},
2553 + {S1DREG_CRT_CUR_XPOS0, 0x00},
2554 + {S1DREG_CRT_CUR_XPOS1, 0x00},
2555 + {S1DREG_CRT_CUR_YPOS0, 0x00},
2556 + {S1DREG_CRT_CUR_YPOS1, 0x00},
2557 + {S1DREG_CRT_CUR_BCTL0, 0x00},
2558 + {S1DREG_CRT_CUR_GCTL0, 0x00},
2559 + {S1DREG_CRT_CUR_RCTL0, 0x00},
2560 + {S1DREG_CRT_CUR_BCTL1, 0x1F},
2561 + {S1DREG_CRT_CUR_GCTL1, 0x3F},
2562 + {S1DREG_CRT_CUR_RCTL1, 0x1F},
2563 + {S1DREG_CRT_CUR_FIFO_HTC, 0x00},
2564 + {S1DREG_BBLT_CTL0, 0x00},
2565 + {S1DREG_BBLT_CTL0, 0x00},
2566 + {S1DREG_BBLT_CC_EXP, 0x00},
2567 + {S1DREG_BBLT_OP, 0x00},
2568 + {S1DREG_BBLT_SRC_START0, 0x00},
2569 + {S1DREG_BBLT_SRC_START1, 0x00},
2570 + {S1DREG_BBLT_SRC_START2, 0x00},
2571 + {S1DREG_BBLT_DST_START0, 0x00},
2572 + {S1DREG_BBLT_DST_START1, 0x00},
2573 + {S1DREG_BBLT_DST_START2, 0x00},
2574 + {S1DREG_BBLT_MEM_OFF0, 0x00},
2575 + {S1DREG_BBLT_MEM_OFF1, 0x00},
2576 + {S1DREG_BBLT_WIDTH0, 0x00},
2577 + {S1DREG_BBLT_WIDTH1, 0x00},
2578 + {S1DREG_BBLT_HEIGHT0, 0x00},
2579 + {S1DREG_BBLT_HEIGHT1, 0x00},
2580 + {S1DREG_BBLT_BGC0, 0x00},
2581 + {S1DREG_BBLT_BGC1, 0x00},
2582 + {S1DREG_BBLT_FGC0, 0x00},
2583 + {S1DREG_BBLT_FGC1, 0x00},
2584 + {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */
2585 + {S1DREG_LKUP_ADDR, 0x00},
2586 + {S1DREG_PS_CNF, 0x00}, /* Power Save disable */
2587 + {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */
2588 + {S1DREG_CPU2MEM_WDOGT, 0x00},
2589 + {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */
2590 +};
2591 +
2592 +static struct s1d13xxxfb_pdata dk_s1dfb_pdata = {
2593 + .initregs = dk_s1dfb_initregs,
2594 + .initregssize = ARRAY_SIZE(dk_s1dfb_initregs),
2595 + .platform_init_video = dk_init_video,
2596 +};
2597 +
2598 +static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
2599 +
2600 +static struct resource dk_s1dfb_resource[] = {
2601 + [0] = { /* video mem */
2602 + .name = "s1d13806 memory",
2603 + .start = AT91_FB_VMEM_BASE,
2604 + .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
2605 + .flags = IORESOURCE_MEM,
2606 + },
2607 + [1] = { /* video registers */
2608 + .name = "s1d13806 registers",
2609 + .start = AT91_FB_REG_BASE,
2610 + .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
2611 + .flags = IORESOURCE_MEM,
2612 + },
2613 +};
2614 +
2615 +static struct platform_device dk_s1dfb_device = {
2616 + .name = "s1d13806fb",
2617 + .id = -1,
2618 + .dev = {
2619 + .dma_mask = &s1dfb_dmamask,
2620 + .coherent_dma_mask = DMA_BIT_MASK(32),
2621 + .platform_data = &dk_s1dfb_pdata,
2622 + },
2623 + .resource = dk_s1dfb_resource,
2624 + .num_resources = ARRAY_SIZE(dk_s1dfb_resource),
2625 +};
2626 +
2627 +static void __init dk_add_device_video(void)
2628 +{
2629 + platform_device_register(&dk_s1dfb_device);
2630 +}
2631 +#else
2632 +static void __init dk_add_device_video(void) {}
2633 +#endif
2634 +
2635 static struct at91_eth_data __initdata dk_eth_data = {
2636 .phy_irq_pin = AT91_PIN_PC4,
2637 .is_rmii = 1,
2638 @@ -164,7 +341,7 @@
2639 #define DK_FLASH_SIZE 0x200000
2640
2641 static struct physmap_flash_data dk_flash_data = {
2642 - .width = 2,
2643 + .width = 2,
2644 };
2645
2646 static struct resource dk_flash_resource = {
2647 @@ -223,8 +400,12 @@
2648 platform_device_register(&dk_flash);
2649 /* LEDs */
2650 at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
2651 + /* SSC (to LM4549 audio codec) */
2652 + at91_add_device_ssc(AT91RM9200_ID_SSC1, ATMEL_SSC_TD | ATMEL_SSC_RX);
2653 + /* SSC (to SI3021 line interface) */
2654 + at91_add_device_ssc(AT91RM9200_ID_SSC2, ATMEL_SSC_TD | ATMEL_SSC_TK | ATMEL_SSC_RD | ATMEL_SSC_RF);
2655 /* VGA */
2656 -// dk_add_device_video();
2657 + dk_add_device_video();
2658 }
2659
2660 MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
2661 --- a/arch/arm/mach-at91/board-eb9200.c
2662 +++ b/arch/arm/mach-at91/board-eb9200.c
2663 @@ -40,24 +40,24 @@
2664 #include "generic.h"
2665
2666
2667 -/*
2668 - * Serial port configuration.
2669 - * 0 .. 3 = USART0 .. USART3
2670 - * 4 = DBGU
2671 - */
2672 -static struct at91_uart_config __initdata eb9200_uart_config = {
2673 - .console_tty = 0, /* ttyS0 */
2674 - .nr_tty = 2,
2675 - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
2676 -};
2677 -
2678 static void __init eb9200_map_io(void)
2679 {
2680 /* Initialize processor: 18.432 MHz crystal */
2681 at91rm9200_initialize(18432000, AT91RM9200_BGA);
2682
2683 - /* Setup the serial ports and console */
2684 - at91_init_serial(&eb9200_uart_config);
2685 + /* DBGU on ttyS0. (Rx & Tx only) */
2686 + at91_register_uart(0, 0, 0);
2687 +
2688 + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
2689 + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
2690 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
2691 + | ATMEL_UART_RI);
2692 +
2693 + /* USART2 on ttyS2. (Rx, Tx) - IRDA */
2694 + at91_register_uart(AT91RM9200_ID_US2, 2, 0);
2695 +
2696 + /* set serial console to ttyS0 (ie, DBGU) */
2697 + at91_set_serial_console(0);
2698 }
2699
2700 static void __init eb9200_init_irq(void)
2701 --- /dev/null
2702 +++ b/arch/arm/mach-at91/board-ecbat91.c
2703 @@ -0,0 +1,178 @@
2704 +/*
2705 + * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
2706 + * Copyright (C) 2007 emQbit.com.
2707 + *
2708 + * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
2709 + *
2710 + * This program is free software; you can redistribute it and/or modify
2711 + * it under the terms of the GNU General Public License as published by
2712 + * the Free Software Foundation; either version 2 of the License, or
2713 + * (at your option) any later version.
2714 + *
2715 + * This program is distributed in the hope that it will be useful,
2716 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2717 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2718 + * GNU General Public License for more details.
2719 + *
2720 + * You should have received a copy of the GNU General Public License
2721 + * along with this program; if not, write to the Free Software
2722 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2723 + */
2724 +
2725 +#include <linux/types.h>
2726 +#include <linux/init.h>
2727 +#include <linux/mm.h>
2728 +#include <linux/module.h>
2729 +#include <linux/platform_device.h>
2730 +#include <linux/spi/spi.h>
2731 +#include <linux/spi/flash.h>
2732 +
2733 +#include <asm/hardware.h>
2734 +#include <asm/setup.h>
2735 +#include <asm/mach-types.h>
2736 +#include <asm/irq.h>
2737 +
2738 +#include <asm/mach/arch.h>
2739 +#include <asm/mach/map.h>
2740 +#include <asm/mach/irq.h>
2741 +
2742 +#include <asm/arch/board.h>
2743 +#include <asm/arch/gpio.h>
2744 +
2745 +#include "generic.h"
2746 +
2747 +
2748 +static void __init ecb_at91map_io(void)
2749 +{
2750 + /* Initialize processor: 18.432 MHz crystal */
2751 + at91rm9200_initialize(18432000, AT91RM9200_PQFP);
2752 +
2753 + /* Setup the LEDs */
2754 + at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
2755 +
2756 + /* DBGU on ttyS0. (Rx & Tx only) */
2757 + at91_register_uart(0, 0, 0);
2758 +
2759 + /* USART0 on ttyS1. (Rx & Tx only) */
2760 + at91_register_uart(AT91RM9200_ID_US0, 1, 0);
2761 +
2762 + /* set serial console to ttyS0 (ie, DBGU) */
2763 + at91_set_serial_console(0);
2764 +}
2765 +
2766 +static void __init ecb_at91init_irq(void)
2767 +{
2768 + at91rm9200_init_interrupts(NULL);
2769 +}
2770 +
2771 +static struct at91_eth_data __initdata ecb_at91eth_data = {
2772 + .phy_irq_pin = AT91_PIN_PC4,
2773 + .is_rmii = 0,
2774 +};
2775 +
2776 +static struct at91_usbh_data __initdata ecb_at91usbh_data = {
2777 + .ports = 1,
2778 +};
2779 +
2780 +static struct at91_mmc_data __initdata ecb_at91mmc_data = {
2781 + .slot_b = 0,
2782 + .wire4 = 1,
2783 +};
2784 +
2785 +
2786 +#if defined(CONFIG_MTD_DATAFLASH)
2787 +static struct mtd_partition __initdata my_flash0_partitions[] =
2788 +{
2789 + { /* 0x8400 */
2790 + .name = "Darrell-loader",
2791 + .offset = 0,
2792 + .size = 12* 1056,
2793 + },
2794 + {
2795 + .name = "U-boot",
2796 + .offset = MTDPART_OFS_NXTBLK,
2797 + .size = 110 * 1056,
2798 + },
2799 + { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
2800 + .name = "Uoot-env",
2801 + .offset = MTDPART_OFS_NXTBLK,
2802 + .size = 8 * 1056,
2803 + },
2804 + { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
2805 + .name = "Kernel",
2806 + .offset = MTDPART_OFS_NXTBLK,
2807 + .size = 1534 * 1056,
2808 + },
2809 + { /* 190200 - jffs2 root filesystem */
2810 + .name = "Filesystem",
2811 + .offset = MTDPART_OFS_NXTBLK,
2812 + .size = MTDPART_SIZ_FULL, /* 26 sectors */
2813 + }
2814 +};
2815 +
2816 +static struct flash_platform_data __initdata my_flash0_platform = {
2817 + .name = "Removable flash card",
2818 + .parts = my_flash0_partitions,
2819 + .nr_parts = ARRAY_SIZE(my_flash0_partitions)
2820 +};
2821 +
2822 +#endif
2823 +
2824 +static struct spi_board_info __initdata ecb_at91spi_devices[] = {
2825 + { /* DataFlash chip */
2826 + .modalias = "mtd_dataflash",
2827 + .chip_select = 0,
2828 + .max_speed_hz = 10 * 1000 * 1000,
2829 + .bus_num = 0,
2830 +#if defined(CONFIG_MTD_DATAFLASH)
2831 + .platform_data = &my_flash0_platform,
2832 +#endif
2833 + },
2834 + { /* User accessable spi - cs1 (250KHz) */
2835 + .modalias = "spi-cs1",
2836 + .chip_select = 1,
2837 + .max_speed_hz = 250 * 1000,
2838 + },
2839 + { /* User accessable spi - cs2 (1MHz) */
2840 + .modalias = "spi-cs2",
2841 + .chip_select = 2,
2842 + .max_speed_hz = 1 * 1000 * 1000,
2843 + },
2844 + { /* User accessable spi - cs3 (10MHz) */
2845 + .modalias = "spi-cs3",
2846 + .chip_select = 3,
2847 + .max_speed_hz = 10 * 1000 * 1000,
2848 + },
2849 +};
2850 +
2851 +static void __init ecb_at91board_init(void)
2852 +{
2853 + /* Serial */
2854 + at91_add_device_serial();
2855 +
2856 + /* Ethernet */
2857 + at91_add_device_eth(&ecb_at91eth_data);
2858 +
2859 + /* USB Host */
2860 + at91_add_device_usbh(&ecb_at91usbh_data);
2861 +
2862 + /* I2C */
2863 + at91_add_device_i2c(NULL, 0);
2864 +
2865 + /* MMC */
2866 + at91_add_device_mmc(0, &ecb_at91mmc_data);
2867 +
2868 + /* SPI */
2869 + at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
2870 +}
2871 +
2872 +MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
2873 + /* Maintainer: emQbit.com */
2874 + .phys_io = AT91_BASE_SYS,
2875 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2876 + .boot_params = AT91_SDRAM_BASE + 0x100,
2877 + .timer = &at91rm9200_timer,
2878 + .map_io = ecb_at91map_io,
2879 + .init_irq = ecb_at91init_irq,
2880 + .init_machine = ecb_at91board_init,
2881 +MACHINE_END
2882 --- a/arch/arm/mach-at91/board-ek.c
2883 +++ b/arch/arm/mach-at91/board-ek.c
2884 @@ -25,6 +25,7 @@
2885 #include <linux/init.h>
2886 #include <linux/mm.h>
2887 #include <linux/module.h>
2888 +#include <linux/dma-mapping.h>
2889 #include <linux/platform_device.h>
2890 #include <linux/spi/spi.h>
2891 #include <linux/mtd/physmap.h>
2892 @@ -45,17 +46,6 @@
2893 #include "generic.h"
2894
2895
2896 -/*
2897 - * Serial port configuration.
2898 - * 0 .. 3 = USART0 .. USART3
2899 - * 4 = DBGU
2900 - */
2901 -static struct at91_uart_config __initdata ek_uart_config = {
2902 - .console_tty = 0, /* ttyS0 */
2903 - .nr_tty = 2,
2904 - .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
2905 -};
2906 -
2907 static void __init ek_map_io(void)
2908 {
2909 /* Initialize processor: 18.432 MHz crystal */
2910 @@ -64,8 +54,16 @@
2911 /* Setup the LEDs */
2912 at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
2913
2914 - /* Setup the serial ports and console */
2915 - at91_init_serial(&ek_uart_config);
2916 + /* DBGU on ttyS0. (Rx & Tx only) */
2917 + at91_register_uart(0, 0, 0);
2918 +
2919 + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
2920 + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
2921 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
2922 + | ATMEL_UART_RI);
2923 +
2924 + /* set serial console to ttyS0 (ie, DBGU) */
2925 + at91_set_serial_console(0);
2926 }
2927
2928 static void __init ek_init_irq(void)
2929 @@ -73,6 +71,187 @@
2930 at91rm9200_init_interrupts(NULL);
2931 }
2932
2933 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
2934 +#include <video/s1d13xxxfb.h>
2935 +#include <asm/arch/ics1523.h>
2936 +
2937 +/* EPSON S1D13806 FB */
2938 +#define AT91_FB_REG_BASE 0x40000000L
2939 +#define AT91_FB_REG_SIZE 0x200
2940 +#define AT91_FB_VMEM_BASE 0x40200000L
2941 +#define AT91_FB_VMEM_SIZE 0x140000L
2942 +
2943 +static void ek_init_video(void)
2944 +{
2945 + /* NWAIT Signal */
2946 + at91_set_A_periph(AT91_PIN_PC6, 0);
2947 +
2948 + /* Initialization of the Static Memory Controller for Chip Select 3 */
2949 + at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16 /* 16 bit */
2950 + | AT91_SMC_WSEN | AT91_SMC_NWS_(5) /* wait states */
2951 + | AT91_SMC_TDF_(1) /* float time */
2952 + );
2953 +
2954 + at91_ics1523_init();
2955 +}
2956 +
2957 +/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz)
2958 + Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
2959 +static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = {
2960 + {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */
2961 + {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */
2962 + {S1DREG_GPIO_CNF0, 0xFF}, // 0x00
2963 + {S1DREG_GPIO_CNF1, 0x1F}, // 0x08
2964 + {S1DREG_GPIO_CTL0, 0x00},
2965 + {S1DREG_GPIO_CTL1, 0x00},
2966 + {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/
2967 + {S1DREG_LCD_CLK_CNF, 0x00},
2968 + {S1DREG_CRT_CLK_CNF, 0x00},
2969 + {S1DREG_MPLUG_CLK_CNF, 0x00},
2970 + {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */
2971 + {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */
2972 + {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */
2973 + {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */
2974 + {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */
2975 + {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
2976 + {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */
2977 + {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */
2978 + {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */
2979 + {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */
2980 + {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */
2981 + {S1DREG_LCD_DISP_VHEIGHT0, 0xDF},
2982 + {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2983 + {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */
2984 + {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */
2985 + {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */
2986 + {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */
2987 + {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */
2988 + {S1DREG_LCD_DISP_START0, 0x00},
2989 + {S1DREG_LCD_DISP_START1, 0xC8},
2990 + {S1DREG_LCD_DISP_START2, 0x00},
2991 + {S1DREG_LCD_MEM_OFF0, 0x80},
2992 + {S1DREG_LCD_MEM_OFF1, 0x02},
2993 + {S1DREG_LCD_PIX_PAN, 0x00},
2994 + {S1DREG_LCD_DISP_FIFO_HTC, 0x3B},
2995 + {S1DREG_LCD_DISP_FIFO_LTC, 0x3C},
2996 + {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */
2997 + {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */
2998 + {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */
2999 + {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */
3000 + {S1DREG_CRT_DISP_VHEIGHT0, 0xDF},
3001 + {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */
3002 + {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */
3003 + {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */
3004 + {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */
3005 + {S1DREG_TV_OUT_CTL, 0x10},
3006 + {0x005E, 0x9F},
3007 + {0x005F, 0x00},
3008 + {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */
3009 + {S1DREG_CRT_DISP_START0, 0x00},
3010 + {S1DREG_CRT_DISP_START1, 0x00},
3011 + {S1DREG_CRT_DISP_START2, 0x00},
3012 + {S1DREG_CRT_MEM_OFF0, 0x80},
3013 + {S1DREG_CRT_MEM_OFF1, 0x02},
3014 + {S1DREG_CRT_PIX_PAN, 0x00},
3015 + {S1DREG_CRT_DISP_FIFO_HTC, 0x3B},
3016 + {S1DREG_CRT_DISP_FIFO_LTC, 0x3C},
3017 + {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */
3018 + {S1DREG_LCD_CUR_START, 0x01},
3019 + {S1DREG_LCD_CUR_XPOS0, 0x00},
3020 + {S1DREG_LCD_CUR_XPOS1, 0x00},
3021 + {S1DREG_LCD_CUR_YPOS0, 0x00},
3022 + {S1DREG_LCD_CUR_YPOS1, 0x00},
3023 + {S1DREG_LCD_CUR_BCTL0, 0x00},
3024 + {S1DREG_LCD_CUR_GCTL0, 0x00},
3025 + {S1DREG_LCD_CUR_RCTL0, 0x00},
3026 + {S1DREG_LCD_CUR_BCTL1, 0x1F},
3027 + {S1DREG_LCD_CUR_GCTL1, 0x3F},
3028 + {S1DREG_LCD_CUR_RCTL1, 0x1F},
3029 + {S1DREG_LCD_CUR_FIFO_HTC, 0x00},
3030 + {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */
3031 + {S1DREG_CRT_CUR_START, 0x01},
3032 + {S1DREG_CRT_CUR_XPOS0, 0x00},
3033 + {S1DREG_CRT_CUR_XPOS1, 0x00},
3034 + {S1DREG_CRT_CUR_YPOS0, 0x00},
3035 + {S1DREG_CRT_CUR_YPOS1, 0x00},
3036 + {S1DREG_CRT_CUR_BCTL0, 0x00},
3037 + {S1DREG_CRT_CUR_GCTL0, 0x00},
3038 + {S1DREG_CRT_CUR_RCTL0, 0x00},
3039 + {S1DREG_CRT_CUR_BCTL1, 0x1F},
3040 + {S1DREG_CRT_CUR_GCTL1, 0x3F},
3041 + {S1DREG_CRT_CUR_RCTL1, 0x1F},
3042 + {S1DREG_CRT_CUR_FIFO_HTC, 0x00},
3043 + {S1DREG_BBLT_CTL0, 0x00},
3044 + {S1DREG_BBLT_CTL0, 0x00},
3045 + {S1DREG_BBLT_CC_EXP, 0x00},
3046 + {S1DREG_BBLT_OP, 0x00},
3047 + {S1DREG_BBLT_SRC_START0, 0x00},
3048 + {S1DREG_BBLT_SRC_START1, 0x00},
3049 + {S1DREG_BBLT_SRC_START2, 0x00},
3050 + {S1DREG_BBLT_DST_START0, 0x00},
3051 + {S1DREG_BBLT_DST_START1, 0x00},
3052 + {S1DREG_BBLT_DST_START2, 0x00},
3053 + {S1DREG_BBLT_MEM_OFF0, 0x00},
3054 + {S1DREG_BBLT_MEM_OFF1, 0x00},
3055 + {S1DREG_BBLT_WIDTH0, 0x00},
3056 + {S1DREG_BBLT_WIDTH1, 0x00},
3057 + {S1DREG_BBLT_HEIGHT0, 0x00},
3058 + {S1DREG_BBLT_HEIGHT1, 0x00},
3059 + {S1DREG_BBLT_BGC0, 0x00},
3060 + {S1DREG_BBLT_BGC1, 0x00},
3061 + {S1DREG_BBLT_FGC0, 0x00},
3062 + {S1DREG_BBLT_FGC1, 0x00},
3063 + {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */
3064 + {S1DREG_LKUP_ADDR, 0x00},
3065 + {S1DREG_PS_CNF, 0x10}, /* Power Save disable */
3066 + {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */
3067 + {S1DREG_CPU2MEM_WDOGT, 0x00},
3068 + {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */
3069 +};
3070 +
3071 +static struct s1d13xxxfb_pdata ek_s1dfb_pdata = {
3072 + .initregs = ek_s1dfb_initregs,
3073 + .initregssize = ARRAY_SIZE(ek_s1dfb_initregs),
3074 + .platform_init_video = ek_init_video,
3075 +};
3076 +
3077 +static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
3078 +
3079 +static struct resource ek_s1dfb_resource[] = {
3080 + [0] = { /* video mem */
3081 + .name = "s1d13806 memory",
3082 + .start = AT91_FB_VMEM_BASE,
3083 + .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
3084 + .flags = IORESOURCE_MEM,
3085 + },
3086 + [1] = { /* video registers */
3087 + .name = "s1d13806 registers",
3088 + .start = AT91_FB_REG_BASE,
3089 + .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
3090 + .flags = IORESOURCE_MEM,
3091 + },
3092 +};
3093 +
3094 +static struct platform_device ek_s1dfb_device = {
3095 + .name = "s1d13806fb",
3096 + .id = -1,
3097 + .dev = {
3098 + .dma_mask = &s1dfb_dmamask,
3099 + .coherent_dma_mask = DMA_BIT_MASK(32),
3100 + .platform_data = &ek_s1dfb_pdata,
3101 + },
3102 + .resource = ek_s1dfb_resource,
3103 + .num_resources = ARRAY_SIZE(ek_s1dfb_resource),
3104 +};
3105 +
3106 +static void __init ek_add_device_video(void)
3107 +{
3108 + platform_device_register(&ek_s1dfb_device);
3109 +}
3110 +#else
3111 +static void __init ek_add_device_video(void) {}
3112 +#endif
3113 +
3114 static struct at91_eth_data __initdata ek_eth_data = {
3115 .phy_irq_pin = AT91_PIN_PC4,
3116 .is_rmii = 1,
3117 @@ -122,7 +301,7 @@
3118 #define EK_FLASH_SIZE 0x200000
3119
3120 static struct physmap_flash_data ek_flash_data = {
3121 - .width = 2,
3122 + .width = 2,
3123 };
3124
3125 static struct resource ek_flash_resource = {
3126 @@ -189,7 +368,7 @@
3127 /* LEDs */
3128 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
3129 /* VGA */
3130 -// ek_add_device_video();
3131 + ek_add_device_video();
3132 }
3133
3134 MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
3135 --- /dev/null
3136 +++ b/arch/arm/mach-at91/board-homematic.c
3137 @@ -0,0 +1,163 @@
3138 +/*
3139 + * linux/arch/arm/mach-at91/board-homematic.c
3140 + *
3141 + * Copyright (C) 2007 eQ-3 Entwicklung GmbH
3142 + *
3143 + * based on work
3144 + * Copyright (C) 2005 SAN People
3145 + *
3146 + * This program is free software; you can redistribute it and/or modify
3147 + * it under the terms of the GNU General Public License as published by
3148 + * the Free Software Foundation; either version 2 of the License, or
3149 + * (at your option) any later version.
3150 + *
3151 + * This program is distributed in the hope that it will be useful,
3152 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3153 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3154 + * GNU General Public License for more details.
3155 + *
3156 + * You should have received a copy of the GNU General Public License
3157 + * along with this program; if not, write to the Free Software
3158 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3159 + */
3160 +
3161 +#include <linux/types.h>
3162 +#include <linux/init.h>
3163 +#include <linux/mm.h>
3164 +#include <linux/module.h>
3165 +#include <linux/platform_device.h>
3166 +#include <linux/spi/spi.h>
3167 +#include <linux/mtd/physmap.h>
3168 +
3169 +#include <asm/hardware.h>
3170 +#include <asm/setup.h>
3171 +#include <asm/mach-types.h>
3172 +#include <asm/irq.h>
3173 +
3174 +#include <asm/mach/arch.h>
3175 +#include <asm/mach/map.h>
3176 +#include <asm/mach/irq.h>
3177 +
3178 +#include <asm/arch/board.h>
3179 +#include <asm/arch/gpio.h>
3180 +#include <asm/arch/at91rm9200_mc.h>
3181 +
3182 +#include "generic.h"
3183 +
3184 +
3185 +/*
3186 + * Serial port configuration.
3187 + * 0 .. 3 = USART0 .. USART3
3188 + * 4 = DBGU
3189 + */
3190 +static struct at91_uart_config __initdata homematic_uart_config = {
3191 + .console_tty = 0, /* ttyS0 */
3192 + .nr_tty = 2,
3193 + .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
3194 +};
3195 +
3196 +static void __init homematic_map_io(void)
3197 +{
3198 + /* Initialize processor: 18.432 MHz crystal */
3199 + at91rm9200_initialize(18432000, AT91RM9200_BGA);
3200 +
3201 + /* Setup the serial ports and console */
3202 + at91_init_serial(&homematic_uart_config);
3203 +}
3204 +
3205 +static void __init homematic_init_irq(void)
3206 +{
3207 + at91rm9200_init_interrupts(NULL);
3208 +}
3209 +
3210 +static struct at91_eth_data __initdata homematic_eth_data = {
3211 + .phy_irq_pin = AT91_PIN_PC4,
3212 + .is_rmii = 0,
3213 +};
3214 +
3215 +static struct at91_usbh_data __initdata homematic_usbh_data = {
3216 + .ports = 2,
3217 +};
3218 +
3219 +static struct at91_udc_data __initdata homematic_udc_data = {
3220 + .vbus_pin = AT91_PIN_PD4,
3221 + .pullup_pin = AT91_PIN_PD5,
3222 +};
3223 +
3224 +static struct at91_mmc_data __initdata homematic_mmc_data = {
3225 + .slot_b = 0,
3226 + .wire4 = 1,
3227 +};
3228 +
3229 +static struct spi_board_info homematic_spi_devices[] = {
3230 + { /* DataFlash chip */
3231 + .modalias = "mtd_dataflash",
3232 + .chip_select = 0,
3233 + .max_speed_hz = 15 * 1000 * 1000,
3234 + },
3235 +};
3236 +
3237 +static struct mtd_partition __initdata homematic_nand_partition[] = {
3238 + {
3239 + .name = "root",
3240 + .offset = 0,
3241 + .size = 0x02000000,
3242 + }, {
3243 + .name = "storage",
3244 + .offset = 0x02000000,
3245 + .size = MTDPART_SIZ_FULL,
3246 + },
3247 +};
3248 +
3249 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
3250 +{
3251 + *num_partitions = ARRAY_SIZE(homematic_nand_partition);
3252 + return homematic_nand_partition;
3253 +}
3254 +
3255 +static struct at91_nand_data __initdata homematic_nand_data = {
3256 + .ale = 22,
3257 + .cle = 21,
3258 +// .det_pin = AT91_PIN_PB1,
3259 + .rdy_pin = AT91_PIN_PC2,
3260 + .enable_pin = AT91_PIN_PC0,
3261 + .partition_info = nand_partitions,
3262 +};
3263 +
3264 +static void __init homematic_board_init(void)
3265 +{
3266 + /* Serial */
3267 + at91_add_device_serial();
3268 + /* Ethernet */
3269 + at91_add_device_eth(&homematic_eth_data);
3270 + /* USB Host */
3271 + at91_add_device_usbh(&homematic_usbh_data);
3272 + /* USB Device */
3273 + at91_add_device_udc(&homematic_udc_data);
3274 + at91_set_multi_drive(homematic_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */
3275 + /* I2C */
3276 + at91_add_device_i2c(NULL, 0);
3277 + /* SPI */
3278 + at91_add_device_spi(homematic_spi_devices, ARRAY_SIZE(homematic_spi_devices));
3279 +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
3280 + /* DataFlash card */
3281 + at91_set_gpio_output(AT91_PIN_PB7, 0);
3282 +#else
3283 + /* MMC */
3284 + at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
3285 + at91_add_device_mmc(0, &homematic_mmc_data);
3286 +#endif
3287 + /* NAND */
3288 + at91_add_device_nand(&homematic_nand_data);
3289 +}
3290 +
3291 +MACHINE_START(HOMEMATIC, "HomeMatic")
3292 + /* Maintainer: eQ-3 */
3293 + .phys_io = AT91_BASE_SYS,
3294 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
3295 + .boot_params = AT91_SDRAM_BASE + 0x100,
3296 + .timer = &at91rm9200_timer,
3297 + .map_io = homematic_map_io,
3298 + .init_irq = homematic_init_irq,
3299 + .init_machine = homematic_board_init,
3300 +MACHINE_END
3301 --- a/arch/arm/mach-at91/board-kb9202.c
3302 +++ b/arch/arm/mach-at91/board-kb9202.c
3303 @@ -37,19 +37,10 @@
3304 #include <asm/arch/board.h>
3305 #include <asm/arch/gpio.h>
3306
3307 -#include "generic.h"
3308 +#include <asm/arch/at91rm9200_mc.h>
3309
3310 +#include "generic.h"
3311
3312 -/*
3313 - * Serial port configuration.
3314 - * 0 .. 3 = USART0 .. USART3
3315 - * 4 = DBGU
3316 - */
3317 -static struct at91_uart_config __initdata kb9202_uart_config = {
3318 - .console_tty = 0, /* ttyS0 */
3319 - .nr_tty = 3,
3320 - .tty_map = { 4, 0, 1, -1, -1 } /* ttyS0, ..., ttyS4 */
3321 -};
3322
3323 static void __init kb9202_map_io(void)
3324 {
3325 @@ -59,8 +50,20 @@
3326 /* Set up the LEDs */
3327 at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
3328
3329 - /* Setup the serial ports and console */
3330 - at91_init_serial(&kb9202_uart_config);
3331 + /* DBGU on ttyS0. (Rx & Tx only) */
3332 + at91_register_uart(0, 0, 0);
3333 +
3334 + /* USART0 on ttyS1 (Rx & Tx only) */
3335 + at91_register_uart(AT91RM9200_ID_US0, 1, 0);
3336 +
3337 + /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
3338 + at91_register_uart(AT91RM9200_ID_US1, 2, 0);
3339 +
3340 + /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
3341 + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
3342 +
3343 + /* set serial console to ttyS0 (ie, DBGU) */
3344 + at91_set_serial_console(0);
3345 }
3346
3347 static void __init kb9202_init_irq(void)
3348 @@ -111,6 +114,48 @@
3349 .partition_info = nand_partitions,
3350 };
3351
3352 +
3353 +#if defined(CONFIG_FB_S1D15605)
3354 +#warning "The Reset pin must be passed via platform_data, not this way"
3355 +static struct resource kb9202_lcd_resources[] = {
3356 + [0] = {
3357 + .start = AT91_CHIPSELECT_2,
3358 + .end = AT91_CHIPSELECT_2 + 0x200FF,
3359 + .flags = IORESOURCE_MEM
3360 + },
3361 + [1] = { /* reset pin */
3362 + .start = AT91_PIN_PC22,
3363 + .end = AT91_PIN_PC22,
3364 + .flags = IORESOURCE_MEM
3365 + },
3366 +};
3367 +
3368 +static struct platform_device kb9202_lcd_device = {
3369 + .name = "s1d15605fb",
3370 + .id = 0,
3371 + .num_resources = ARRAY_SIZE(kb9202_lcd_resources),
3372 + .resource = kb9202_lcd_resources,
3373 +};
3374 +
3375 +static void __init kb9202_add_device_lcd(void)
3376 +{
3377 + /* In case the boot loader did not set the chip select mode and timing */
3378 + at91_sys_write(AT91_SMC_CSR(2),
3379 + AT91_SMC_WSEN | AT91_SMC_NWS_(18) | AT91_SMC_TDF_(1) | AT91_SMC_DBW_8 |
3380 + AT91_SMC_RWSETUP_(1) | AT91_SMC_RWHOLD_(1));
3381 +
3382 + /* Backlight pin = output, off */
3383 + at91_set_gpio_output(AT91_PIN_PC23, 0);
3384 +
3385 + /* Reset pin = output, in reset */
3386 + at91_set_gpio_output(AT91_PIN_PC22, 0);
3387 +
3388 + platform_device_register(&kb9202_lcd_device);
3389 +}
3390 +#else
3391 +static void __init kb9202_add_device_lcd(void) {}
3392 +#endif
3393 +
3394 static void __init kb9202_board_init(void)
3395 {
3396 /* Serial */
3397 @@ -129,6 +174,8 @@
3398 at91_add_device_spi(NULL, 0);
3399 /* NAND */
3400 at91_add_device_nand(&kb9202_nand_data);
3401 + /* LCD */
3402 + kb9202_add_device_lcd();
3403 }
3404
3405 MACHINE_START(KB9200, "KB920x")
3406 --- /dev/null
3407 +++ b/arch/arm/mach-at91/board-qil-a9260.c
3408 @@ -0,0 +1,255 @@
3409 +/*
3410 + * linux/arch/arm/mach-at91/board-qil-a9260.c
3411 + *
3412 + * Copyright (C) 2005 SAN People
3413 + * Copyright (C) 2006 Atmel
3414 + * Copyright (C) 2007 Calao-systems
3415 + *
3416 + * This program is free software; you can redistribute it and/or modify
3417 + * it under the terms of the GNU General Public License as published by
3418 + * the Free Software Foundation; either version 2 of the License, or
3419 + * (at your option) any later version.
3420 + *
3421 + * This program is distributed in the hope that it will be useful,
3422 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3423 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3424 + * GNU General Public License for more details.
3425 + *
3426 + * You should have received a copy of the GNU General Public License
3427 + * along with this program; if not, write to the Free Software
3428 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3429 + */
3430 +
3431 +#include <linux/types.h>
3432 +#include <linux/init.h>
3433 +#include <linux/mm.h>
3434 +#include <linux/module.h>
3435 +#include <linux/platform_device.h>
3436 +#include <linux/spi/spi.h>
3437 +#include <linux/gpio_keys.h>
3438 +#include <linux/input.h>
3439 +#include <linux/clk.h>
3440 +
3441 +#include <asm/hardware.h>
3442 +#include <asm/setup.h>
3443 +#include <asm/mach-types.h>
3444 +#include <asm/irq.h>
3445 +
3446 +#include <asm/mach/arch.h>
3447 +#include <asm/mach/map.h>
3448 +#include <asm/mach/irq.h>
3449 +
3450 +#include <asm/arch/board.h>
3451 +#include <asm/arch/gpio.h>
3452 +#include <asm/arch/at91_shdwc.h>
3453 +
3454 +#include "generic.h"
3455 +
3456 +
3457 +static void __init ek_map_io(void)
3458 +{
3459 + /* Initialize processor: 12.000 MHz crystal */
3460 + at91sam9260_initialize(12000000);
3461 +
3462 + /* DGBU on ttyS0. (Rx & Tx only) */
3463 + at91_register_uart(0, 0, 0);
3464 +
3465 + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
3466 + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
3467 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
3468 + | ATMEL_UART_RI);
3469 +
3470 + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
3471 + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
3472 +
3473 + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
3474 + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
3475 +
3476 + /* set serial console to ttyS1 (ie, USART0) */
3477 + at91_set_serial_console(1);
3478 +
3479 +}
3480 +
3481 +static void __init ek_init_irq(void)
3482 +{
3483 + at91sam9260_init_interrupts(NULL);
3484 +}
3485 +
3486 +
3487 +/*
3488 + * USB Host port
3489 + */
3490 +static struct at91_usbh_data __initdata ek_usbh_data = {
3491 + .ports = 2,
3492 +};
3493 +
3494 +/*
3495 + * USB Device port
3496 + */
3497 +static struct at91_udc_data __initdata ek_udc_data = {
3498 + .vbus_pin = AT91_PIN_PC5,
3499 + .pullup_pin = 0, /* pull-up driven by UDC */
3500 +};
3501 +
3502 +/*
3503 + * SPI devices.
3504 + */
3505 +static struct spi_board_info ek_spi_devices[] = {
3506 +#if defined(CONFIG_RTC_DRV_M41T94)
3507 + { /* M41T94 RTC */
3508 + .modalias = "m41t94",
3509 + .chip_select = 0,
3510 + .max_speed_hz = 1 * 1000 * 1000,
3511 + .bus_num = 0,
3512 + }
3513 +#endif
3514 +};
3515 +
3516 +/*
3517 + * MACB Ethernet device
3518 + */
3519 +static struct at91_eth_data __initdata ek_macb_data = {
3520 + .phy_irq_pin = AT91_PIN_PA31,
3521 + .is_rmii = 1,
3522 +};
3523 +
3524 +/*
3525 + * NAND flash
3526 + */
3527 +static struct mtd_partition __initdata ek_nand_partition[] = {
3528 + {
3529 + .name = "Uboot & Kernel",
3530 + .offset = 0x00000000,
3531 + .size = 16 * 1024 * 1024,
3532 + },
3533 + {
3534 + .name = "Root FS",
3535 + .offset = 0x01000000,
3536 + .size = 120 * 1024 * 1024,
3537 + },
3538 + {
3539 + .name = "FS",
3540 + .offset = 0x08800000,
3541 + .size = 120 * 1024 * 1024,
3542 + },
3543 +};
3544 +
3545 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
3546 +{
3547 + *num_partitions = ARRAY_SIZE(ek_nand_partition);
3548 + return ek_nand_partition;
3549 +}
3550 +
3551 +static struct at91_nand_data __initdata ek_nand_data = {
3552 + .ale = 21,
3553 + .cle = 22,
3554 +// .det_pin = ... not connected
3555 + .rdy_pin = AT91_PIN_PC13,
3556 + .enable_pin = AT91_PIN_PC14,
3557 + .partition_info = nand_partitions,
3558 +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
3559 + .bus_width_16 = 1,
3560 +#else
3561 + .bus_width_16 = 0,
3562 +#endif
3563 +};
3564 +
3565 +/*
3566 + * MCI (SD/MMC)
3567 + */
3568 +static struct at91_mmc_data __initdata ek_mmc_data = {
3569 + .slot_b = 0,
3570 + .wire4 = 1,
3571 +// .det_pin = ... not connected
3572 +// .wp_pin = ... not connected
3573 +// .vcc_pin = ... not connected
3574 +};
3575 +
3576 +/*
3577 + * GPIO Buttons
3578 + */
3579 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
3580 +static struct gpio_keys_button ek_buttons[] = {
3581 + { /* USER PUSH BUTTON */
3582 + .code = KEY_ENTER,
3583 + .gpio = AT91_PIN_PB10,
3584 + .active_low = 1,
3585 + .desc = "user_pb",
3586 + .wakeup = 1,
3587 + }
3588 +};
3589 +
3590 +static struct gpio_keys_platform_data ek_button_data = {
3591 + .buttons = ek_buttons,
3592 + .nbuttons = ARRAY_SIZE(ek_buttons),
3593 +};
3594 +
3595 +static struct platform_device ek_button_device = {
3596 + .name = "gpio-keys",
3597 + .id = -1,
3598 + .num_resources = 0,
3599 + .dev = {
3600 + .platform_data = &ek_button_data,
3601 + }
3602 +};
3603 +
3604 +static void __init ek_add_device_buttons(void)
3605 +{
3606 + at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
3607 + at91_set_deglitch(AT91_PIN_PB10, 1);
3608 +
3609 + platform_device_register(&ek_button_device);
3610 +}
3611 +#else
3612 +static void __init ek_add_device_buttons(void) {}
3613 +#endif
3614 +
3615 +/*
3616 + * LEDs
3617 + */
3618 +static struct gpio_led ek_leds[] = {
3619 + { /* user_led (green) */
3620 + .name = "user_led",
3621 + .gpio = AT91_PIN_PB21,
3622 + .active_low = 0,
3623 + .default_trigger = "heartbeat",
3624 + }
3625 +};
3626 +
3627 +static void __init ek_board_init(void)
3628 +{
3629 + /* Serial */
3630 + at91_add_device_serial();
3631 + /* USB Host */
3632 + at91_add_device_usbh(&ek_usbh_data);
3633 + /* USB Device */
3634 + at91_add_device_udc(&ek_udc_data);
3635 + /* SPI */
3636 + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3637 + /* NAND */
3638 + at91_add_device_nand(&ek_nand_data);
3639 + /* I2C */
3640 + at91_add_device_i2c(NULL, 0);
3641 + /* Ethernet */
3642 + at91_add_device_eth(&ek_macb_data);
3643 + /* MMC */
3644 + at91_add_device_mmc(0, &ek_mmc_data);
3645 + /* Push Buttons */
3646 + ek_add_device_buttons();
3647 + /* LEDs */
3648 + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
3649 + /* shutdown controller, wakeup button (5 msec low) */
3650 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
3651 + | AT91_SHDW_RTTWKEN);
3652 +}
3653 +
3654 +MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
3655 + /* Maintainer: calao-systems */
3656 + .phys_io = AT91_BASE_SYS,
3657 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
3658 + .boot_params = AT91_SDRAM_BASE + 0x100,
3659 + .timer = &at91sam926x_timer,
3660 + .map_io = ek_map_io,
3661 + .init_irq = ek_init_irq,
3662 + .init_machine = ek_board_init,
3663 +MACHINE_END
3664 --- /dev/null
3665 +++ b/arch/arm/mach-at91/board-sam9-l9260.c
3666 @@ -0,0 +1,199 @@
3667 +/*
3668 + * linux/arch/arm/mach-at91/board-sam9-l9260.c
3669 + *
3670 + * Copyright (C) 2005 SAN People
3671 + * Copyright (C) 2006 Atmel
3672 + * Copyright (C) 2007 Olimex Ltd
3673 + *
3674 + * This program is free software; you can redistribute it and/or modify
3675 + * it under the terms of the GNU General Public License as published by
3676 + * the Free Software Foundation; either version 2 of the License, or
3677 + * (at your option) any later version.
3678 + *
3679 + * This program is distributed in the hope that it will be useful,
3680 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3681 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3682 + * GNU General Public License for more details.
3683 + *
3684 + * You should have received a copy of the GNU General Public License
3685 + * along with this program; if not, write to the Free Software
3686 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3687 + */
3688 +
3689 +#include <linux/types.h>
3690 +#include <linux/init.h>
3691 +#include <linux/mm.h>
3692 +#include <linux/module.h>
3693 +#include <linux/platform_device.h>
3694 +#include <linux/spi/spi.h>
3695 +
3696 +#include <asm/hardware.h>
3697 +#include <asm/setup.h>
3698 +#include <asm/mach-types.h>
3699 +#include <asm/irq.h>
3700 +
3701 +#include <asm/mach/arch.h>
3702 +#include <asm/mach/map.h>
3703 +#include <asm/mach/irq.h>
3704 +
3705 +#include <asm/arch/board.h>
3706 +#include <asm/arch/gpio.h>
3707 +
3708 +#include "generic.h"
3709 +
3710 +
3711 +static void __init ek_map_io(void)
3712 +{
3713 + /* Initialize processor: 18.432 MHz crystal */
3714 + at91sam9260_initialize(18432000);
3715 +
3716 + /* Setup the LEDs */
3717 + at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
3718 +
3719 + /* DBGU on ttyS0. (Rx & Tx only) */
3720 + at91_register_uart(0, 0, 0);
3721 +
3722 + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
3723 + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
3724 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
3725 + | ATMEL_UART_RI);
3726 +
3727 + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
3728 + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
3729 +
3730 + /* set serial console to ttyS0 (ie, DBGU) */
3731 + at91_set_serial_console(0);
3732 +}
3733 +
3734 +static void __init ek_init_irq(void)
3735 +{
3736 + at91sam9260_init_interrupts(NULL);
3737 +}
3738 +
3739 +
3740 +/*
3741 + * USB Host port
3742 + */
3743 +static struct at91_usbh_data __initdata ek_usbh_data = {
3744 + .ports = 2,
3745 +};
3746 +
3747 +/*
3748 + * USB Device port
3749 + */
3750 +static struct at91_udc_data __initdata ek_udc_data = {
3751 + .vbus_pin = AT91_PIN_PC5,
3752 + .pullup_pin = 0, /* pull-up driven by UDC */
3753 +};
3754 +
3755 +
3756 +/*
3757 + * SPI devices.
3758 + */
3759 +static struct spi_board_info ek_spi_devices[] = {
3760 +#if !defined(CONFIG_MMC_AT91)
3761 + { /* DataFlash chip */
3762 + .modalias = "mtd_dataflash",
3763 + .chip_select = 1,
3764 + .max_speed_hz = 15 * 1000 * 1000,
3765 + .bus_num = 0,
3766 + },
3767 +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
3768 + { /* DataFlash card */
3769 + .modalias = "mtd_dataflash",
3770 + .chip_select = 0,
3771 + .max_speed_hz = 15 * 1000 * 1000,
3772 + .bus_num = 0,
3773 + },
3774 +#endif
3775 +#endif
3776 +};
3777 +
3778 +
3779 +/*
3780 + * MACB Ethernet device
3781 + */
3782 +static struct at91_eth_data __initdata ek_macb_data = {
3783 + .phy_irq_pin = AT91_PIN_PA7,
3784 + .is_rmii = 0,
3785 +};
3786 +
3787 +
3788 +/*
3789 + * NAND flash
3790 + */
3791 +static struct mtd_partition __initdata ek_nand_partition[] = {
3792 + {
3793 + .name = "Bootloader Area",
3794 + .offset = 0,
3795 + .size = 10 * 1024 * 1024,
3796 + },
3797 + {
3798 + .name = "User Area",
3799 + .offset = 10 * 1024 * 1024,
3800 + .size = MTDPART_SIZ_FULL,
3801 + },
3802 +};
3803 +
3804 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
3805 +{
3806 + *num_partitions = ARRAY_SIZE(ek_nand_partition);
3807 + return ek_nand_partition;
3808 +}
3809 +
3810 +static struct at91_nand_data __initdata ek_nand_data = {
3811 + .ale = 21,
3812 + .cle = 22,
3813 +// .det_pin = ... not connected
3814 + .rdy_pin = AT91_PIN_PC13,
3815 + .enable_pin = AT91_PIN_PC14,
3816 + .partition_info = nand_partitions,
3817 +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
3818 + .bus_width_16 = 1,
3819 +#else
3820 + .bus_width_16 = 0,
3821 +#endif
3822 +};
3823 +
3824 +
3825 +/*
3826 + * MCI (SD/MMC)
3827 + */
3828 +static struct at91_mmc_data __initdata ek_mmc_data = {
3829 + .slot_b = 1,
3830 + .wire4 = 1,
3831 + .det_pin = AT91_PIN_PC8,
3832 + .wp_pin = AT91_PIN_PC4,
3833 +// .vcc_pin = ... not connected
3834 +};
3835 +
3836 +static void __init ek_board_init(void)
3837 +{
3838 + /* Serial */
3839 + at91_add_device_serial();
3840 + /* USB Host */
3841 + at91_add_device_usbh(&ek_usbh_data);
3842 + /* USB Device */
3843 + at91_add_device_udc(&ek_udc_data);
3844 + /* SPI */
3845 + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3846 + /* NAND */
3847 + at91_add_device_nand(&ek_nand_data);
3848 + /* Ethernet */
3849 + at91_add_device_eth(&ek_macb_data);
3850 + /* MMC */
3851 + at91_add_device_mmc(0, &ek_mmc_data);
3852 + /* I2C */
3853 + at91_add_device_i2c(NULL, 0);
3854 +}
3855 +
3856 +MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
3857 + /* Maintainer: Olimex */
3858 + .phys_io = AT91_BASE_SYS,
3859 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
3860 + .boot_params = AT91_SDRAM_BASE + 0x100,
3861 + .timer = &at91sam926x_timer,
3862 + .map_io = ek_map_io,
3863 + .init_irq = ek_init_irq,
3864 + .init_machine = ek_board_init,
3865 +MACHINE_END
3866 --- a/arch/arm/mach-at91/board-sam9260ek.c
3867 +++ b/arch/arm/mach-at91/board-sam9260ek.c
3868 @@ -25,6 +25,10 @@
3869 #include <linux/module.h>
3870 #include <linux/platform_device.h>
3871 #include <linux/spi/spi.h>
3872 +#include <linux/spi/at73c213.h>
3873 +#include <linux/clk.h>
3874 +#include <linux/gpio_keys.h>
3875 +#include <linux/input.h>
3876
3877 #include <asm/hardware.h>
3878 #include <asm/setup.h>
3879 @@ -37,29 +41,29 @@
3880
3881 #include <asm/arch/board.h>
3882 #include <asm/arch/gpio.h>
3883 -#include <asm/arch/at91sam926x_mc.h>
3884 +#include <asm/arch/at91_shdwc.h>
3885
3886 #include "generic.h"
3887
3888
3889 -/*
3890 - * Serial port configuration.
3891 - * 0 .. 5 = USART0 .. USART5
3892 - * 6 = DBGU
3893 - */
3894 -static struct at91_uart_config __initdata ek_uart_config = {
3895 - .console_tty = 0, /* ttyS0 */
3896 - .nr_tty = 3,
3897 - .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
3898 -};
3899 -
3900 static void __init ek_map_io(void)
3901 {
3902 /* Initialize processor: 18.432 MHz crystal */
3903 at91sam9260_initialize(18432000);
3904
3905 - /* Setup the serial ports and console */
3906 - at91_init_serial(&ek_uart_config);
3907 + /* DGBU on ttyS0. (Rx & Tx only) */
3908 + at91_register_uart(0, 0, 0);
3909 +
3910 + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
3911 + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
3912 + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
3913 + | ATMEL_UART_RI);
3914 +
3915 + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
3916 + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
3917 +
3918 + /* set serial console to ttyS0 (ie, DBGU) */
3919 + at91_set_serial_console(0);
3920 }
3921
3922 static void __init ek_init_irq(void)
3923 @@ -85,6 +89,35 @@
3924
3925
3926 /*
3927 + * Audio
3928 + */
3929 +static struct at73c213_board_info at73c213_data = {
3930 + .ssc_id = 0,
3931 + .shortname = "AT91SAM9260-EK external DAC",
3932 +};
3933 +
3934 +#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
3935 +static void __init at73c213_set_clk(struct at73c213_board_info *info)
3936 +{
3937 + struct clk *pck0;
3938 + struct clk *plla;
3939 +
3940 + pck0 = clk_get(NULL, "pck0");
3941 + plla = clk_get(NULL, "plla");
3942 +
3943 + /* AT73C213 MCK Clock */
3944 + at91_set_B_periph(AT91_PIN_PC1, 0); /* PCK0 */
3945 +
3946 + clk_set_parent(pck0, plla);
3947 + clk_put(plla);
3948 +
3949 + info->dac_clk = pck0;
3950 +}
3951 +#else
3952 +static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
3953 +#endif
3954 +
3955 +/*
3956 * SPI devices.
3957 */
3958 static struct spi_board_info ek_spi_devices[] = {
3959 @@ -110,6 +143,8 @@
3960 .chip_select = 0,
3961 .max_speed_hz = 10 * 1000 * 1000,
3962 .bus_num = 1,
3963 + .mode = SPI_MODE_1,
3964 + .platform_data = &at73c213_data,
3965 },
3966 #endif
3967 };
3968 @@ -172,6 +207,74 @@
3969 // .vcc_pin = ... not connected
3970 };
3971
3972 +
3973 +/*
3974 + * LEDs
3975 + */
3976 +static struct gpio_led ek_leds[] = {
3977 + { /* "bottom" led, green, userled1 to be defined */
3978 + .name = "ds5",
3979 + .gpio = AT91_PIN_PA6,
3980 + .active_low = 1,
3981 + .default_trigger = "none",
3982 + },
3983 + { /* "power" led, yellow */
3984 + .name = "ds1",
3985 + .gpio = AT91_PIN_PA9,
3986 + .default_trigger = "heartbeat",
3987 + }
3988 +};
3989 +
3990 +
3991 +/*
3992 + * GPIO Buttons
3993 + */
3994 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
3995 +static struct gpio_keys_button ek_buttons[] = {
3996 + {
3997 + .gpio = AT91_PIN_PA30,
3998 + .code = BTN_3,
3999 + .desc = "Button 3",
4000 + .active_low = 1,
4001 + .wakeup = 1,
4002 + },
4003 + {
4004 + .gpio = AT91_PIN_PA31,
4005 + .code = BTN_4,
4006 + .desc = "Button 4",
4007 + .active_low = 1,
4008 + .wakeup = 1,
4009 + }
4010 +};
4011 +
4012 +static struct gpio_keys_platform_data ek_button_data = {
4013 + .buttons = ek_buttons,
4014 + .nbuttons = ARRAY_SIZE(ek_buttons),
4015 +};
4016 +
4017 +static struct platform_device ek_button_device = {
4018 + .name = "gpio-keys",
4019 + .id = -1,
4020 + .num_resources = 0,
4021 + .dev = {
4022 + .platform_data = &ek_button_data,
4023 + }
4024 +};
4025 +
4026 +static void __init ek_add_device_buttons(void)
4027 +{
4028 + at91_set_gpio_input(AT91_PIN_PA30, 1); /* btn3 */
4029 + at91_set_deglitch(AT91_PIN_PA30, 1);
4030 + at91_set_gpio_input(AT91_PIN_PA31, 1); /* btn4 */
4031 + at91_set_deglitch(AT91_PIN_PA31, 1);
4032 +
4033 + platform_device_register(&ek_button_device);
4034 +}
4035 +#else
4036 +static void __init ek_add_device_buttons(void) {}
4037 +#endif
4038 +
4039 +
4040 static void __init ek_board_init(void)
4041 {
4042 /* Serial */
4043 @@ -190,6 +293,16 @@
4044 at91_add_device_mmc(0, &ek_mmc_data);
4045 /* I2C */
4046 at91_add_device_i2c(NULL, 0);
4047 + /* SSC (to AT73C213) */
4048 + at73c213_set_clk(&at73c213_data);
4049 + at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
4050 + /* LEDs */
4051 + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
4052 + /* Push Buttons */
4053 + ek_add_device_buttons();
4054 + /* shutdown controller, wakeup button (5 msec low) */
4055 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
4056 + | AT91_SHDW_RTTWKEN);
4057 }
4058
4059 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
4060 --- a/arch/arm/mach-at91/board-sam9261ek.c
4061 +++ b/arch/arm/mach-at91/board-sam9261ek.c
4062 @@ -26,6 +26,8 @@
4063 #include <linux/platform_device.h>
4064 #include <linux/spi/spi.h>
4065 #include <linux/spi/ads7846.h>
4066 +#include <linux/spi/at73c213.h>
4067 +#include <linux/clk.h>
4068 #include <linux/dm9000.h>
4069 #include <linux/fb.h>
4070 #include <linux/gpio_keys.h>
4071 @@ -44,22 +46,12 @@
4072
4073 #include <asm/arch/board.h>
4074 #include <asm/arch/gpio.h>
4075 -#include <asm/arch/at91sam926x_mc.h>
4076 +#include <asm/arch/at91sam9_smc.h>
4077 +#include <asm/arch/at91_shdwc.h>
4078
4079 #include "generic.h"
4080
4081
4082 -/*
4083 - * Serial port configuration.
4084 - * 0 .. 2 = USART0 .. USART2
4085 - * 3 = DBGU
4086 - */
4087 -static struct at91_uart_config __initdata ek_uart_config = {
4088 - .console_tty = 0, /* ttyS0 */
4089 - .nr_tty = 1,
4090 - .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */
4091 -};
4092 -
4093 static void __init ek_map_io(void)
4094 {
4095 /* Initialize processor: 18.432 MHz crystal */
4096 @@ -68,8 +60,11 @@
4097 /* Setup the LEDs */
4098 at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
4099
4100 - /* Setup the serial ports and console */
4101 - at91_init_serial(&ek_uart_config);
4102 + /* DGBU on ttyS0. (Rx & Tx only) */
4103 + at91_register_uart(0, 0, 0);
4104 +
4105 + /* set serial console to ttyS0 (ie, DBGU) */
4106 + at91_set_serial_console(0);
4107 }
4108
4109 static void __init ek_init_irq(void)
4110 @@ -239,6 +234,35 @@
4111 #endif
4112
4113 /*
4114 + * Audio
4115 + */
4116 +static struct at73c213_board_info at73c213_data = {
4117 + .ssc_id = 1,
4118 + .shortname = "AT91SAM9261-EK external DAC",
4119 +};
4120 +
4121 +#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
4122 +static void __init at73c213_set_clk(struct at73c213_board_info *info)
4123 +{
4124 + struct clk *pck2;
4125 + struct clk *plla;
4126 +
4127 + pck2 = clk_get(NULL, "pck2");
4128 + plla = clk_get(NULL, "plla");
4129 +
4130 + /* AT73C213 MCK Clock */
4131 + at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */
4132 +
4133 + clk_set_parent(pck2, plla);
4134 + clk_put(plla);
4135 +
4136 + info->dac_clk = pck2;
4137 +}
4138 +#else
4139 +static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
4140 +#endif
4141 +
4142 +/*
4143 * SPI devices
4144 */
4145 static struct spi_board_info ek_spi_devices[] = {
4146 @@ -252,10 +276,11 @@
4147 {
4148 .modalias = "ads7846",
4149 .chip_select = 2,
4150 - .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
4151 + .max_speed_hz = 125000 * 16, /* max sample rate * clocks per sample */
4152 .bus_num = 0,
4153 .platform_data = &ads_info,
4154 .irq = AT91SAM9261_ID_IRQ0,
4155 + .controller_data = (void *) AT91_PIN_PA28, /* CS pin */
4156 },
4157 #endif
4158 #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
4159 @@ -271,6 +296,9 @@
4160 .chip_select = 3,
4161 .max_speed_hz = 10 * 1000 * 1000,
4162 .bus_num = 0,
4163 + .mode = SPI_MODE_1,
4164 + .platform_data = &at73c213_data,
4165 + .controller_data = (void*) AT91_PIN_PA29, /* default for CS3 is PA6, but it must be PA29 */
4166 },
4167 #endif
4168 };
4169 @@ -408,24 +436,28 @@
4170 .code = BTN_0,
4171 .desc = "Button 0",
4172 .active_low = 1,
4173 + .wakeup = 1,
4174 },
4175 {
4176 .gpio = AT91_PIN_PA26,
4177 .code = BTN_1,
4178 .desc = "Button 1",
4179 .active_low = 1,
4180 + .wakeup = 1,
4181 },
4182 {
4183 .gpio = AT91_PIN_PA25,
4184 .code = BTN_2,
4185 .desc = "Button 2",
4186 .active_low = 1,
4187 + .wakeup = 1,
4188 },
4189 {
4190 .gpio = AT91_PIN_PA24,
4191 .code = BTN_3,
4192 .desc = "Button 3",
4193 .active_low = 1,
4194 + .wakeup = 1,
4195 }
4196 };
4197
4198 @@ -445,13 +477,13 @@
4199
4200 static void __init ek_add_device_buttons(void)
4201 {
4202 - at91_set_gpio_input(AT91_PIN_PA27, 0); /* btn0 */
4203 + at91_set_gpio_input(AT91_PIN_PA27, 1); /* btn0 */
4204 at91_set_deglitch(AT91_PIN_PA27, 1);
4205 - at91_set_gpio_input(AT91_PIN_PA26, 0); /* btn1 */
4206 + at91_set_gpio_input(AT91_PIN_PA26, 1); /* btn1 */
4207 at91_set_deglitch(AT91_PIN_PA26, 1);
4208 - at91_set_gpio_input(AT91_PIN_PA25, 0); /* btn2 */
4209 + at91_set_gpio_input(AT91_PIN_PA25, 1); /* btn2 */
4210 at91_set_deglitch(AT91_PIN_PA25, 1);
4211 - at91_set_gpio_input(AT91_PIN_PA24, 0); /* btn3 */
4212 + at91_set_gpio_input(AT91_PIN_PA24, 1); /* btn3 */
4213 at91_set_deglitch(AT91_PIN_PA24, 1);
4214
4215 platform_device_register(&ek_button_device);
4216 @@ -460,6 +492,29 @@
4217 static void __init ek_add_device_buttons(void) {}
4218 #endif
4219
4220 +/*
4221 + * LEDs
4222 + */
4223 +static struct gpio_led ek_leds[] = {
4224 + { /* "bottom" led, green, userled1 to be defined */
4225 + .name = "ds7",
4226 + .gpio = AT91_PIN_PA14,
4227 + .active_low = 1,
4228 + .default_trigger = "none",
4229 + },
4230 + { /* "top" led, green, userled2 to be defined */
4231 + .name = "ds8",
4232 + .gpio = AT91_PIN_PA13,
4233 + .active_low = 1,
4234 + .default_trigger = "none",
4235 + },
4236 + { /* "power" led, yellow */
4237 + .name = "ds1",
4238 + .gpio = AT91_PIN_PA23,
4239 + .default_trigger = "heartbeat",
4240 + }
4241 +};
4242 +
4243 static void __init ek_board_init(void)
4244 {
4245 /* Serial */
4246 @@ -481,6 +536,9 @@
4247 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
4248 /* Touchscreen */
4249 ek_add_device_ts();
4250 + /* SSC (to AT73C213) */
4251 + at73c213_set_clk(&at73c213_data);
4252 + at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
4253 #else
4254 /* MMC */
4255 at91_add_device_mmc(0, &ek_mmc_data);
4256 @@ -489,6 +547,11 @@
4257 at91_add_device_lcdc(&ek_lcdc_data);
4258 /* Push Buttons */
4259 ek_add_device_buttons();
4260 + /* LEDs */
4261 + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
4262 + /* shutdown controller, wakeup button (5 msec low) */
4263 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
4264 + | AT91_SHDW_RTTWKEN);
4265 }
4266
4267 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
4268 --- a/arch/arm/mach-at91/board-sam9263ek.c
4269 +++ b/arch/arm/mach-at91/board-sam9263ek.c
4270 @@ -43,29 +43,24 @@
4271
4272 #include <asm/arch/board.h>
4273 #include <asm/arch/gpio.h>
4274 -#include <asm/arch/at91sam926x_mc.h>
4275 +#include <asm/arch/at91_shdwc.h>
4276
4277 #include "generic.h"
4278
4279
4280 -/*
4281 - * Serial port configuration.
4282 - * 0 .. 2 = USART0 .. USART2
4283 - * 3 = DBGU
4284 - */
4285 -static struct at91_uart_config __initdata ek_uart_config = {
4286 - .console_tty = 0, /* ttyS0 */
4287 - .nr_tty = 2,
4288 - .tty_map = { 3, 0, -1, -1, } /* ttyS0, ..., ttyS3 */
4289 -};
4290 -
4291 static void __init ek_map_io(void)
4292 {
4293 /* Initialize processor: 16.367 MHz crystal */
4294 at91sam9263_initialize(16367660);
4295
4296 - /* Setup the serial ports and console */
4297 - at91_init_serial(&ek_uart_config);
4298 + /* DGBU on ttyS0. (Rx & Tx only) */
4299 + at91_register_uart(0, 0, 0);
4300 +
4301 + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
4302 + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
4303 +
4304 + /* set serial console to ttyS0 (ie, DBGU) */
4305 + at91_set_serial_console(0);
4306 }
4307
4308 static void __init ek_init_irq(void)
4309 @@ -141,7 +136,7 @@
4310 {
4311 .modalias = "ads7846",
4312 .chip_select = 3,
4313 - .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
4314 + .max_speed_hz = 125000 * 16, /* max sample rate * clocks per sample */
4315 .bus_num = 0,
4316 .platform_data = &ads_info,
4317 .irq = AT91SAM9263_ID_IRQ1,
4318 @@ -301,9 +296,9 @@
4319
4320 static void __init ek_add_device_buttons(void)
4321 {
4322 - at91_set_GPIO_periph(AT91_PIN_PC5, 0); /* left button */
4323 + at91_set_GPIO_periph(AT91_PIN_PC5, 1); /* left button */
4324 at91_set_deglitch(AT91_PIN_PC5, 1);
4325 - at91_set_GPIO_periph(AT91_PIN_PC4, 0); /* right button */
4326 + at91_set_GPIO_periph(AT91_PIN_PC4, 1); /* right button */
4327 at91_set_deglitch(AT91_PIN_PC4, 1);
4328
4329 platform_device_register(&ek_button_device);
4330 @@ -341,7 +336,7 @@
4331 .name = "ds3",
4332 .gpio = AT91_PIN_PB7,
4333 .default_trigger = "heartbeat",
4334 - },
4335 + }
4336 };
4337
4338
4339 @@ -374,6 +369,9 @@
4340 at91_add_device_ac97(&ek_ac97_data);
4341 /* LEDs */
4342 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
4343 + /* shutdown controller, wakeup button (5 msec low) */
4344 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
4345 + | AT91_SHDW_RTTWKEN);
4346 }
4347
4348 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
4349 --- a/arch/arm/mach-at91/board-sam9rlek.c
4350 +++ b/arch/arm/mach-at91/board-sam9rlek.c
4351 @@ -29,29 +29,24 @@
4352
4353 #include <asm/arch/board.h>
4354 #include <asm/arch/gpio.h>
4355 -#include <asm/arch/at91sam926x_mc.h>
4356 +#include <asm/arch/at91_shdwc.h>
4357
4358 #include "generic.h"
4359
4360
4361 -/*
4362 - * Serial port configuration.
4363 - * 0 .. 3 = USART0 .. USART3
4364 - * 4 = DBGU
4365 - */
4366 -static struct at91_uart_config __initdata ek_uart_config = {
4367 - .console_tty = 0, /* ttyS0 */
4368 - .nr_tty = 2,
4369 - .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
4370 -};
4371 -
4372 static void __init ek_map_io(void)
4373 {
4374 /* Initialize processor: 12.000 MHz crystal */
4375 at91sam9rl_initialize(12000000);
4376
4377 - /* Setup the serial ports and console */
4378 - at91_init_serial(&ek_uart_config);
4379 + /* DGBU on ttyS0. (Rx & Tx only) */
4380 + at91_register_uart(0, 0, 0);
4381 +
4382 + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
4383 + at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
4384 +
4385 + /* set serial console to ttyS0 (ie, DBGU) */
4386 + at91_set_serial_console(0);
4387 }
4388
4389 static void __init ek_init_irq(void)
4390 @@ -61,6 +56,14 @@
4391
4392
4393 /*
4394 + * USB HS Device port
4395 + */
4396 +static struct usba_platform_data __initdata ek_usba_udc_data = {
4397 + .vbus_pin = AT91_PIN_PA8,
4398 +};
4399 +
4400 +
4401 +/*
4402 * MCI (SD/MMC)
4403 */
4404 static struct at91_mmc_data __initdata ek_mmc_data = {
4405 @@ -180,6 +183,8 @@
4406 {
4407 /* Serial */
4408 at91_add_device_serial();
4409 + /* USB HS */
4410 + at91_add_device_usba(&ek_usba_udc_data);
4411 /* I2C */
4412 at91_add_device_i2c(NULL, 0);
4413 /* NAND */
4414 @@ -190,6 +195,9 @@
4415 at91_add_device_mmc(0, &ek_mmc_data);
4416 /* LCD Controller */
4417 at91_add_device_lcdc(&ek_lcdc_data);
4418 + /* shutdown controller, wakeup button (5 msec low) */
4419 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
4420 + | AT91_SHDW_RTTWKEN);
4421 }
4422
4423 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
4424 --- /dev/null
4425 +++ b/arch/arm/mach-at91/board-tms.c
4426 @@ -0,0 +1,198 @@
4427 +/*
4428 +* linux/arch/arm/mach-at91/board-tms.c
4429 +*
4430 +* Copyright (C) 2005 SAN People
4431 +*
4432 +* Adapted from board-dk to sweda TMS-100 by Luiz de Barros <lboneto@gmail.com>
4433 +*
4434 +* This program is free software; you can redistribute it and/or modify
4435 +* it under the terms of the GNU General Public License as published by
4436 +* the Free Software Foundation; either version 2 of the License, or
4437 +* (at your option) any later version.
4438 +*
4439 +* This program is distributed in the hope that it will be useful,
4440 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
4441 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4442 +* GNU General Public License for more details.
4443 +*
4444 +* You should have received a copy of the GNU General Public License
4445 +* along with this program; if not, write to the Free Software
4446 +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4447 +*/
4448 +
4449 +#include <linux/types.h>
4450 +#include <linux/init.h>
4451 +#include <linux/mm.h>
4452 +#include <linux/module.h>
4453 +#include <linux/platform_device.h>
4454 +#include <linux/spi/spi.h>
4455 +#include <linux/mtd/physmap.h>
4456 +
4457 +#include <asm/hardware.h>
4458 +#include <asm/setup.h>
4459 +#include <asm/mach-types.h>
4460 +#include <asm/irq.h>
4461 +
4462 +#include <asm/mach/arch.h>
4463 +#include <asm/mach/map.h>
4464 +#include <asm/mach/irq.h>
4465 +
4466 +#include <asm/arch/board.h>
4467 +#include <asm/arch/gpio.h>
4468 +#include <asm/arch/at91rm9200_mc.h>
4469 +
4470 +#include "generic.h"
4471 +#include <linux/serial_8250.h>
4472 +
4473 +
4474 +#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP| UPF_SHARE_IRQ)
4475 +#define SERIAL_CLK (1843200)
4476 +
4477 +
4478 +/*---------------------------------------------------------------------
4479 + * External UART
4480 + */
4481 +
4482 +#define PORT(_base, _irq) \
4483 + { \
4484 + .mapbase = _base, \
4485 + .irq = _irq, \
4486 + .uartclk = SERIAL_CLK, \
4487 + .iotype = UPIO_MEM, \
4488 + .regshift = 0, \
4489 + .flags = SERIAL_FLAGS, \
4490 + }
4491 +
4492 +static struct plat_serial8250_port tms_data[] = {
4493 + PORT(0x70000000, AT91_PIN_PC3),
4494 + PORT(0x80000000, AT91_PIN_PC5),
4495 + { },
4496 +};
4497 +
4498 +static struct platform_device tms_device = {
4499 + .name = "serial8250",
4500 + .id = PLAT8250_DEV_PLATFORM,
4501 + .dev =
4502 + {
4503 + .platform_data = &tms_data,
4504 + },
4505 +};
4506 +
4507 +static void setup_external_uart(void)
4508 +{
4509 + at91_sys_write(AT91_SMC_CSR(2),
4510 + AT91_SMC_ACSS_STD
4511 + | AT91_SMC_DBW_8
4512 + | AT91_SMC_BAT
4513 + | AT91_SMC_WSEN
4514 + | AT91_SMC_NWS_(32) /* wait states */
4515 + | AT91_SMC_RWSETUP_(6) /* setup time */
4516 + | AT91_SMC_RWHOLD_(4) /* hold time */
4517 +
4518 + );
4519 + at91_sys_write(AT91_SMC_CSR(6),
4520 + AT91_SMC_ACSS_STD
4521 + | AT91_SMC_DBW_8
4522 + | AT91_SMC_BAT
4523 + | AT91_SMC_WSEN
4524 + | AT91_SMC_NWS_(32) /* wait states */
4525 + | AT91_SMC_RWSETUP_(6) /* setup time */
4526 + | AT91_SMC_RWHOLD_(4) /* hold time */
4527 +
4528 + );
4529 + at91_sys_write(AT91_SMC_CSR(7),
4530 + AT91_SMC_ACSS_STD
4531 + | AT91_SMC_DBW_8
4532 + | AT91_SMC_BAT
4533 + | AT91_SMC_WSEN
4534 + | AT91_SMC_NWS_(32) /* wait states */
4535 + | AT91_SMC_RWSETUP_(6) /* setup time */
4536 + | AT91_SMC_RWHOLD_(4) /* hold time */
4537 + );
4538 +
4539 + platform_device_register(&tms_device);
4540 +}
4541 +
4542 +
4543 +/*
4544 + * Serial port configuration.
4545 + * 0 .. 3 = USART0 .. USART3
4546 + * 4 = DBGU
4547 + */
4548 +static struct at91_uart_config __initdata tms_uart_config = {
4549 + .console_tty = 0, /* ttyS0 */
4550 + .nr_tty = 5,
4551 + .tty_map = { 4, 0, 1, 2, 3 } /* ttyS0, ..., ttyS4 */
4552 +};
4553 +
4554 +static void __init tms_map_io(void)
4555 +{
4556 + /* Initialize processor: 18.432 MHz crystal */
4557 + at91rm9200_initialize(18432000, AT91RM9200_BGA);
4558 +
4559 + /* Setup the LEDs */
4560 + at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
4561 +
4562 + /* Setup the serial ports and console */
4563 + at91_init_serial(&tms_uart_config);
4564 +}
4565 +
4566 +static void __init tms_init_irq(void)
4567 +{
4568 + at91rm9200_init_interrupts(NULL);
4569 +}
4570 +
4571 +
4572 +static struct at91_eth_data __initdata tms_eth_data = {
4573 + .phy_irq_pin = AT91_PIN_PC4,
4574 + .is_rmii = 1,
4575 +};
4576 +
4577 +static struct at91_usbh_data __initdata tms_usbh_data = {
4578 + .ports = 2,
4579 +};
4580 +
4581 +static struct spi_board_info tms_spi_devices[] = {
4582 + { /* DataFlash chip */
4583 + .modalias = "mtd_dataflash",
4584 + .chip_select = 0,
4585 + .max_speed_hz = 15 * 1000 * 1000,
4586 + },
4587 + { /* DataFlash chip */
4588 + .modalias = "mtd_dataflash",
4589 + .chip_select = 1,
4590 + .max_speed_hz = 15 * 1000 * 1000,
4591 + }
4592 +};
4593 +
4594 +static struct i2c_board_info __initdata tms_i2c_devices[] = {
4595 + {
4596 + I2C_BOARD_INFO("isl1208", 0x6f),
4597 + }
4598 +};
4599 +
4600 +static void __init tms_board_init(void)
4601 +{
4602 + /* Serial */
4603 + at91_add_device_serial();
4604 + /* Ethernet */
4605 + at91_add_device_eth(&tms_eth_data);
4606 + at91_add_device_usbh(&tms_usbh_data);
4607 + /* I2C */
4608 + at91_add_device_i2c(tms_i2c_devices, ARRAY_SIZE(tms_i2c_devices));
4609 + /* SPI */
4610 + at91_add_device_spi(tms_spi_devices, ARRAY_SIZE(tms_spi_devices));
4611 + /* Two port external UART */
4612 + setup_external_uart();
4613 +}
4614 +
4615 +MACHINE_START(SWEDATMS, "Sweda TMS-100 Board")
4616 + /* Maintainer: Luiz de Barros */
4617 + .phys_io = AT91_BASE_SYS,
4618 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
4619 + .boot_params = AT91_SDRAM_BASE + 0x100,
4620 + .timer = &at91rm9200_timer,
4621 + .map_io = tms_map_io,
4622 + .init_irq = tms_init_irq,
4623 + .init_machine = tms_board_init,
4624 +MACHINE_END
4625 --- /dev/null
4626 +++ b/arch/arm/mach-at91/board-tt9200.c
4627 @@ -0,0 +1,192 @@
4628 +/*
4629 + * linux/arch/arm/mach-at91rm9200/board-tt9200.c
4630 + * Copyright (C) 2007 Toptechnology
4631 + *
4632 + * Based on board-ecbat91.c
4633 + *
4634 + * This program is free software; you can redistribute it and/or modify
4635 + * it under the terms of the GNU General Public License as published by
4636 + * the Free Software Foundation; either version 2 of the License, or
4637 + * (at your option) any later version.
4638 + *
4639 + * This program is distributed in the hope that it will be useful,
4640 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4641 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4642 + * GNU General Public License for more details.
4643 + *
4644 + * You should have received a copy of the GNU General Public License
4645 + * along with this program; if not, write to the Free Software
4646 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4647 + */
4648 +
4649 +#include <linux/types.h>
4650 +#include <linux/init.h>
4651 +#include <linux/mm.h>
4652 +#include <linux/module.h>
4653 +#include <linux/platform_device.h>
4654 +#include <linux/spi/spi.h>
4655 +#include <linux/spi/flash.h>
4656 +
4657 +#include <asm/hardware.h>
4658 +#include <asm/setup.h>
4659 +#include <asm/mach-types.h>
4660 +#include <asm/irq.h>
4661 +
4662 +#include <asm/mach/arch.h>
4663 +#include <asm/mach/map.h>
4664 +#include <asm/mach/irq.h>
4665 +
4666 +#include <asm/arch/board.h>
4667 +#include <asm/arch/gpio.h>
4668 +
4669 +#include "generic.h"
4670 +
4671 +
4672 +static void __init tt9200_map_io(void)
4673 +{
4674 + /* Initialize processor: 18.432 MHz crystal */
4675 + at91rm9200_initialize(18432000, AT91RM9200_PQFP);
4676 +
4677 + /* Setup the LEDs */
4678 + at91_init_leds(AT91_PIN_PB27, AT91_PIN_PB27);
4679 +
4680 + /* DBGU on ttyS0. (Rx & Tx only) */
4681 + at91_register_uart(0, 0, 0);
4682 +
4683 + /* USART0 on ttyS1. (Rx & Tx only) */
4684 + at91_register_uart(AT91RM9200_ID_US0, 1, 0);
4685 +
4686 + /* USART1 on ttyS2. (Rx & Tx only) */
4687 + at91_register_uart(AT91RM9200_ID_US1, 2, 0);
4688 +
4689 + /* USART2 on ttyS3. (Rx & Tx only) */
4690 + at91_register_uart(AT91RM9200_ID_US2, 3, 0);
4691 +
4692 + /* USART3 on ttyS4. (Rx, Tx, CTS, RTS) */
4693 + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | ATMEL_UART_RTS);
4694 +
4695 + /* Console on ttyS0 (ie, DBGU) */
4696 + at91_set_serial_console(0);
4697 +}
4698 +
4699 +static void __init tt9200_init_irq(void)
4700 +{
4701 + at91rm9200_init_interrupts(NULL);
4702 +}
4703 +
4704 +static struct at91_eth_data __initdata tt9200_eth_data = {
4705 + .phy_irq_pin = AT91_PIN_PB29,
4706 + .is_rmii = 0,
4707 +};
4708 +
4709 +static struct at91_usbh_data __initdata tt9200_usbh_data = {
4710 + .ports = 1,
4711 +};
4712 +
4713 +static struct i2c_board_info __initdata tt9200_i2c_devices[] = {
4714 + {
4715 + I2C_BOARD_INFO("rtc-m41t80", 0x68),
4716 + .type = "m41t80",
4717 + }
4718 +};
4719 +
4720 +static struct at91_mmc_data __initdata tt9200_mmc_data = {
4721 + .slot_b = 0,
4722 + .wire4 = 1,
4723 +};
4724 +
4725 +
4726 +#if defined(CONFIG_MTD_DATAFLASH)
4727 +static struct mtd_partition __initdata tt9200_flash_partitions[] =
4728 +{
4729 + {
4730 + .name = "Darrell",
4731 + .offset = 0,
4732 + .size = 12 * 1056,
4733 + },
4734 + {
4735 + .name = "U-boot",
4736 + .offset = MTDPART_OFS_NXTBLK,
4737 + .size = 110 * 1056,
4738 + },
4739 + {
4740 + .name = "U-boot env",
4741 + .offset = MTDPART_OFS_NXTBLK,
4742 + .size = 8 * 1056,
4743 + },
4744 + {
4745 + .name = "Kernel",
4746 + .offset = MTDPART_OFS_NXTBLK,
4747 + .size = 1534 * 1056,
4748 + },
4749 + {
4750 + .name = "Filesystem",
4751 + .offset = MTDPART_OFS_NXTBLK,
4752 + .size = MTDPART_SIZ_FULL,
4753 + }
4754 +};
4755 +
4756 +static struct flash_platform_data __initdata tt9200_flash_platform = {
4757 + .name = "SPI Dataflash",
4758 + .parts = tt9200_flash_partitions,
4759 + .nr_parts = ARRAY_SIZE(tt9200_flash_partitions)
4760 +};
4761 +
4762 +#endif
4763 +
4764 +static struct spi_board_info __initdata tt9200_spi_devices[] = {
4765 + { /* DataFlash chip */
4766 + .modalias = "mtd_dataflash",
4767 + .chip_select = 0,
4768 + /* Errata #13 */
4769 + .max_speed_hz = 5 * 1000 * 1000,
4770 + .bus_num = 0,
4771 +#if defined(CONFIG_MTD_DATAFLASH)
4772 + .platform_data = &tt9200_flash_platform,
4773 +#endif
4774 + },
4775 +};
4776 +
4777 +static struct gpio_led tt9200_leds[] = {
4778 + {
4779 + .name = "led0",
4780 + .gpio = AT91_PIN_PB27,
4781 + .active_low = 1,
4782 + .default_trigger = "heartbeat",
4783 + }
4784 +};
4785 +
4786 +static void __init tt9200_board_init(void)
4787 +{
4788 + /* Serial */
4789 + at91_add_device_serial();
4790 +
4791 + /* Ethernet */
4792 + at91_add_device_eth(&tt9200_eth_data);
4793 +
4794 + /* USB Host */
4795 + at91_add_device_usbh(&tt9200_usbh_data);
4796 +
4797 + /* I2C */
4798 + at91_add_device_i2c(tt9200_i2c_devices, ARRAY_SIZE(tt9200_i2c_devices));
4799 +
4800 + /* MMC */
4801 + at91_add_device_mmc(0, &tt9200_mmc_data);
4802 +
4803 + /* LEDS */
4804 + at91_gpio_leds(tt9200_leds, ARRAY_SIZE(tt9200_leds));
4805 +
4806 + /* SPI */
4807 + at91_add_device_spi(tt9200_spi_devices, ARRAY_SIZE(tt9200_spi_devices));
4808 +}
4809 +
4810 +MACHINE_START(TT9200, "Toptech TT9200")
4811 + /* Maintainer: toptech.com.ar */
4812 + .phys_io = AT91_BASE_SYS,
4813 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
4814 + .boot_params = AT91_SDRAM_BASE + 0x100,
4815 + .timer = &at91rm9200_timer,
4816 + .map_io = tt9200_map_io,
4817 + .init_irq = tt9200_init_irq,
4818 + .init_machine = tt9200_board_init,
4819 +MACHINE_END
4820 --- /dev/null
4821 +++ b/arch/arm/mach-at91/board-usb-a9260.c
4822 @@ -0,0 +1,215 @@
4823 +/*
4824 + * linux/arch/arm/mach-at91/board-usb-a9260.c
4825 + *
4826 + * Copyright (C) 2005 SAN People
4827 + * Copyright (C) 2006 Atmel
4828 + * Copyright (C) 2007 Calao-systems
4829 + *
4830 + * This program is free software; you can redistribute it and/or modify
4831 + * it under the terms of the GNU General Public License as published by
4832 + * the Free Software Foundation; either version 2 of the License, or
4833 + * (at your option) any later version.
4834 + *
4835 + * This program is distributed in the hope that it will be useful,
4836 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4837 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4838 + * GNU General Public License for more details.
4839 + *
4840 + * You should have received a copy of the GNU General Public License
4841 + * along with this program; if not, write to the Free Software
4842 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4843 + */
4844 +
4845 +#include <linux/types.h>
4846 +#include <linux/init.h>
4847 +#include <linux/mm.h>
4848 +#include <linux/module.h>
4849 +#include <linux/platform_device.h>
4850 +#include <linux/spi/spi.h>
4851 +#include <linux/gpio_keys.h>
4852 +#include <linux/input.h>
4853 +#include <linux/clk.h>
4854 +
4855 +#include <asm/hardware.h>
4856 +#include <asm/setup.h>
4857 +#include <asm/mach-types.h>
4858 +#include <asm/irq.h>
4859 +
4860 +#include <asm/mach/arch.h>
4861 +#include <asm/mach/map.h>
4862 +#include <asm/mach/irq.h>
4863 +
4864 +#include <asm/arch/board.h>
4865 +#include <asm/arch/gpio.h>
4866 +#include <asm/arch/at91_shdwc.h>
4867 +
4868 +#include "generic.h"
4869 +
4870 +
4871 +static void __init ek_map_io(void)
4872 +{
4873 + /* Initialize processor: 12.000 MHz crystal */
4874 + at91sam9260_initialize(12000000);
4875 +
4876 + /* DGBU on ttyS0. (Rx & Tx only) */
4877 + at91_register_uart(0, 0, 0);
4878 +
4879 + /* set serial console to ttyS0 (ie, DBGU) */
4880 + at91_set_serial_console(0);
4881 +}
4882 +
4883 +static void __init ek_init_irq(void)
4884 +{
4885 + at91sam9260_init_interrupts(NULL);
4886 +}
4887 +
4888 +
4889 +/*
4890 + * USB Host port
4891 + */
4892 +static struct at91_usbh_data __initdata ek_usbh_data = {
4893 + .ports = 2,
4894 +};
4895 +
4896 +/*
4897 + * USB Device port
4898 + */
4899 +static struct at91_udc_data __initdata ek_udc_data = {
4900 + .vbus_pin = AT91_PIN_PC5,
4901 + .pullup_pin = 0, /* pull-up driven by UDC */
4902 +};
4903 +
4904 +/*
4905 + * MACB Ethernet device
4906 + */
4907 +static struct at91_eth_data __initdata ek_macb_data = {
4908 + .phy_irq_pin = AT91_PIN_PA31,
4909 + .is_rmii = 1,
4910 +};
4911 +
4912 +/*
4913 + * NAND flash
4914 + */
4915 +static struct mtd_partition __initdata ek_nand_partition[] = {
4916 + {
4917 + .name = "Uboot & Kernel",
4918 + .offset = 0x00000000,
4919 + .size = 16 * 1024 * 1024,
4920 + },
4921 + {
4922 + .name = "Root FS",
4923 + .offset = 0x01000000,
4924 + .size = 120 * 1024 * 1024,
4925 + },
4926 + {
4927 + .name = "FS",
4928 + .offset = 0x08800000,
4929 + .size = 120 * 1024 * 1024,
4930 + }
4931 +};
4932 +
4933 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
4934 +{
4935 + *num_partitions = ARRAY_SIZE(ek_nand_partition);
4936 + return ek_nand_partition;
4937 +}
4938 +
4939 +static struct at91_nand_data __initdata ek_nand_data = {
4940 + .ale = 21,
4941 + .cle = 22,
4942 +// .det_pin = ... not connected
4943 + .rdy_pin = AT91_PIN_PC13,
4944 + .enable_pin = AT91_PIN_PC14,
4945 + .partition_info = nand_partitions,
4946 +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
4947 + .bus_width_16 = 1,
4948 +#else
4949 + .bus_width_16 = 0,
4950 +#endif
4951 +};
4952 +
4953 +/*
4954 + * GPIO Buttons
4955 + */
4956 +
4957 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
4958 +static struct gpio_keys_button ek_buttons[] = {
4959 + { /* USER PUSH BUTTON */
4960 + .code = KEY_ENTER,
4961 + .gpio = AT91_PIN_PB10,
4962 + .active_low = 1,
4963 + .desc = "user_pb",
4964 + .wakeup = 1,
4965 + }
4966 +};
4967 +
4968 +static struct gpio_keys_platform_data ek_button_data = {
4969 + .buttons = ek_buttons,
4970 + .nbuttons = ARRAY_SIZE(ek_buttons),
4971 +};
4972 +
4973 +static struct platform_device ek_button_device = {
4974 + .name = "gpio-keys",
4975 + .id = -1,
4976 + .num_resources = 0,
4977 + .dev = {
4978 + .platform_data = &ek_button_data,
4979 + }
4980 +};
4981 +
4982 +static void __init ek_add_device_buttons(void)
4983 +{
4984 + at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
4985 + at91_set_deglitch(AT91_PIN_PB10, 1);
4986 +
4987 + platform_device_register(&ek_button_device);
4988 +}
4989 +#else
4990 +static void __init ek_add_device_buttons(void) {}
4991 +#endif
4992 +
4993 +/*
4994 + * LEDs
4995 + */
4996 +static struct gpio_led ek_leds[] = {
4997 + { /* user_led (green) */
4998 + .name = "user_led",
4999 + .gpio = AT91_PIN_PB21,
5000 + .active_low = 0,
5001 + .default_trigger = "heartbeat",
5002 + }
5003 +};
5004 +
5005 +static void __init ek_board_init(void)
5006 +{
5007 + /* Serial */
5008 + at91_add_device_serial();
5009 + /* USB Host */
5010 + at91_add_device_usbh(&ek_usbh_data);
5011 + /* USB Device */
5012 + at91_add_device_udc(&ek_udc_data);
5013 + /* NAND */
5014 + at91_add_device_nand(&ek_nand_data);
5015 + /* I2C */
5016 + at91_add_device_i2c(NULL, 0);
5017 + /* Ethernet */
5018 + at91_add_device_eth(&ek_macb_data);
5019 + /* Push Buttons */
5020 + ek_add_device_buttons();
5021 + /* LEDs */
5022 + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
5023 + /* shutdown controller, wakeup button (5 msec low) */
5024 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
5025 + | AT91_SHDW_RTTWKEN);
5026 +}
5027 +
5028 +MACHINE_START(USB_A9260, "CALAO USB_A9260")
5029 + /* Maintainer: calao-systems */
5030 + .phys_io = AT91_BASE_SYS,
5031 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
5032 + .boot_params = AT91_SDRAM_BASE + 0x100,
5033 + .timer = &at91sam926x_timer,
5034 + .map_io = ek_map_io,
5035 + .init_irq = ek_init_irq,
5036 + .init_machine = ek_board_init,
5037 +MACHINE_END
5038 --- /dev/null
5039 +++ b/arch/arm/mach-at91/board-usb-a9263.c
5040 @@ -0,0 +1,230 @@
5041 +/*
5042 + * linux/arch/arm/mach-at91/board-usb-a9263.c
5043 + *
5044 + * Copyright (C) 2005 SAN People
5045 + * Copyright (C) 2007 Atmel Corporation.
5046 + * Copyright (C) 2007 Calao-systems
5047 + *
5048 + * This program is free software; you can redistribute it and/or modify
5049 + * it under the terms of the GNU General Public License as published by
5050 + * the Free Software Foundation; either version 2 of the License, or
5051 + * (at your option) any later version.
5052 + *
5053 + * This program is distributed in the hope that it will be useful,
5054 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5055 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5056 + * GNU General Public License for more details.
5057 + *
5058 + * You should have received a copy of the GNU General Public License
5059 + * along with this program; if not, write to the Free Software
5060 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5061 + */
5062 +
5063 +#include <linux/types.h>
5064 +#include <linux/init.h>
5065 +#include <linux/mm.h>
5066 +#include <linux/module.h>
5067 +#include <linux/platform_device.h>
5068 +#include <linux/spi/spi.h>
5069 +#include <linux/gpio_keys.h>
5070 +#include <linux/input.h>
5071 +
5072 +#include <asm/hardware.h>
5073 +#include <asm/setup.h>
5074 +#include <asm/mach-types.h>
5075 +#include <asm/irq.h>
5076 +
5077 +#include <asm/mach/arch.h>
5078 +#include <asm/mach/map.h>
5079 +#include <asm/mach/irq.h>
5080 +
5081 +#include <asm/arch/board.h>
5082 +#include <asm/arch/gpio.h>
5083 +#include <asm/arch/at91_shdwc.h>
5084 +
5085 +#include "generic.h"
5086 +
5087 +
5088 +static void __init ek_map_io(void)
5089 +{
5090 + /* Initialize processor: 12.00 MHz crystal */
5091 + at91sam9263_initialize(12000000);
5092 +
5093 + /* DGBU on ttyS0. (Rx & Tx only) */
5094 + at91_register_uart(0, 0, 0);
5095 +
5096 + /* set serial console to ttyS0 (ie, DBGU) */
5097 + at91_set_serial_console(0);
5098 +}
5099 +
5100 +static void __init ek_init_irq(void)
5101 +{
5102 + at91sam9263_init_interrupts(NULL);
5103 +}
5104 +
5105 +
5106 +/*
5107 + * USB Host port
5108 + */
5109 +static struct at91_usbh_data __initdata ek_usbh_data = {
5110 + .ports = 2,
5111 +};
5112 +
5113 +/*
5114 + * USB Device port
5115 + */
5116 +static struct at91_udc_data __initdata ek_udc_data = {
5117 + .vbus_pin = AT91_PIN_PB11,
5118 + .pullup_pin = 0, /* pull-up driven by UDC */
5119 +};
5120 +
5121 +/*
5122 + * SPI devices.
5123 + */
5124 +static struct spi_board_info ek_spi_devices[] = {
5125 +#if !defined(CONFIG_MMC_AT91)
5126 + { /* DataFlash chip */
5127 + .modalias = "mtd_dataflash",
5128 + .chip_select = 0,
5129 + .max_speed_hz = 15 * 1000 * 1000,
5130 + .bus_num = 0,
5131 + }
5132 +#endif
5133 +};
5134 +
5135 +/*
5136 + * MACB Ethernet device
5137 + */
5138 +static struct at91_eth_data __initdata ek_macb_data = {
5139 + .phy_irq_pin = AT91_PIN_PE31,
5140 + .is_rmii = 1,
5141 +};
5142 +
5143 +/*
5144 + * NAND flash
5145 + */
5146 +static struct mtd_partition __initdata ek_nand_partition[] = {
5147 + {
5148 + .name = "Linux Kernel",
5149 + .offset = 0x00000000,
5150 + .size = 16 * 1024 * 1024,
5151 + },
5152 + {
5153 + .name = "Root FS",
5154 + .offset = 0x01000000,
5155 + .size = 120 * 1024 * 1024,
5156 + },
5157 + {
5158 + .name = "FS",
5159 + .offset = 0x08800000,
5160 + .size = 120 * 1024 * 1024,
5161 + }
5162 +};
5163 +
5164 +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
5165 +{
5166 + *num_partitions = ARRAY_SIZE(ek_nand_partition);
5167 + return ek_nand_partition;
5168 +}
5169 +
5170 +static struct at91_nand_data __initdata ek_nand_data = {
5171 + .ale = 21,
5172 + .cle = 22,
5173 +// .det_pin = ... not connected
5174 + .rdy_pin = AT91_PIN_PA22,
5175 + .enable_pin = AT91_PIN_PD15,
5176 + .partition_info = nand_partitions,
5177 +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
5178 + .bus_width_16 = 1,
5179 +#else
5180 + .bus_width_16 = 0,
5181 +#endif
5182 +};
5183 +
5184 +/*
5185 + * GPIO Buttons
5186 + */
5187 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
5188 +static struct gpio_keys_button ek_buttons[] = {
5189 + { /* USER PUSH BUTTON */
5190 + .code = KEY_ENTER,
5191 + .gpio = AT91_PIN_PB10,
5192 + .active_low = 1,
5193 + .desc = "user_pb",
5194 + .wakeup = 1,
5195 + }
5196 +};
5197 +
5198 +static struct gpio_keys_platform_data ek_button_data = {
5199 + .buttons = ek_buttons,
5200 + .nbuttons = ARRAY_SIZE(ek_buttons),
5201 +};
5202 +
5203 +static struct platform_device ek_button_device = {
5204 + .name = "gpio-keys",
5205 + .id = -1,
5206 + .num_resources = 0,
5207 + .dev = {
5208 + .platform_data = &ek_button_data,
5209 + }
5210 +};
5211 +
5212 +static void __init ek_add_device_buttons(void)
5213 +{
5214 + at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
5215 + at91_set_deglitch(AT91_PIN_PB10, 1);
5216 +
5217 + platform_device_register(&ek_button_device);
5218 +}
5219 +#else
5220 +static void __init ek_add_device_buttons(void) {}
5221 +#endif
5222 +
5223 +/*
5224 + * LEDs
5225 + */
5226 +static struct gpio_led ek_leds[] = {
5227 + { /* user_led (green) */
5228 + .name = "user_led",
5229 + .gpio = AT91_PIN_PB21,
5230 + .active_low = 1,
5231 + .default_trigger = "heartbeat",
5232 + }
5233 +};
5234 +
5235 +
5236 +static void __init ek_board_init(void)
5237 +{
5238 + /* Serial */
5239 + at91_add_device_serial();
5240 + /* USB Host */
5241 + at91_add_device_usbh(&ek_usbh_data);
5242 + /* USB Device */
5243 + at91_add_device_udc(&ek_udc_data);
5244 + /* SPI */
5245 + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
5246 + /* Ethernet */
5247 + at91_add_device_eth(&ek_macb_data);
5248 + /* NAND */
5249 + at91_add_device_nand(&ek_nand_data);
5250 + /* I2C */
5251 + at91_add_device_i2c(NULL, 0);
5252 + /* Push Buttons */
5253 + ek_add_device_buttons();
5254 + /* LEDs */
5255 + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
5256 + /* shutdown controller, wakeup button (5 msec low) */
5257 + at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
5258 + | AT91_SHDW_RTTWKEN);
5259 +}
5260 +
5261 +MACHINE_START(USB_A9263, "CALAO USB_A9263")
5262 + /* Maintainer: calao-systems */
5263 + .phys_io = AT91_BASE_SYS,
5264 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
5265 + .boot_params = AT91_SDRAM_BASE + 0x100,
5266 + .timer = &at91sam926x_timer,
5267 + .map_io = ek_map_io,
5268 + .init_irq = ek_init_irq,
5269 + .init_machine = ek_board_init,
5270 +MACHINE_END
5271 --- a/arch/arm/mach-at91/clock.c
5272 +++ b/arch/arm/mach-at91/clock.c
5273 @@ -32,6 +32,7 @@
5274 #include <asm/arch/cpu.h>
5275
5276 #include "clock.h"
5277 +#include "generic.h"
5278
5279
5280 /*
5281 @@ -113,12 +114,34 @@
5282 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
5283 }
5284
5285 +static void pmc_uckr_mode(struct clk *clk, int is_on)
5286 +{
5287 + unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
5288 +
5289 + if (is_on) {
5290 + is_on = AT91_PMC_LOCKU;
5291 + at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
5292 + } else
5293 + at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
5294 +
5295 + do {
5296 + cpu_relax();
5297 + } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
5298 +}
5299 +
5300 /* USB function clocks (PLLB must be 48 MHz) */
5301 static struct clk udpck = {
5302 .name = "udpck",
5303 .parent = &pllb,
5304 .mode = pmc_sys_mode,
5305 };
5306 +static struct clk utmi_clk = {
5307 + .name = "utmi_clk",
5308 + .parent = &main_clk,
5309 + .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
5310 + .mode = pmc_uckr_mode,
5311 + .type = CLK_TYPE_PLL,
5312 +};
5313 static struct clk uhpck = {
5314 .name = "uhpck",
5315 .parent = &pllb,
5316 @@ -254,6 +277,23 @@
5317
5318 /*------------------------------------------------------------------------*/
5319
5320 +#ifdef CONFIG_PM
5321 +
5322 +int clk_must_disable(struct clk *clk)
5323 +{
5324 + if (!at91_suspend_entering_slow_clock())
5325 + return 0;
5326 +
5327 + while (clk->parent)
5328 + clk = clk->parent;
5329 + return clk != &clk32k;
5330 +}
5331 +EXPORT_SYMBOL(clk_must_disable);
5332 +
5333 +#endif
5334 +
5335 +/*------------------------------------------------------------------------*/
5336 +
5337 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
5338
5339 /*
5340 @@ -362,7 +402,7 @@
5341
5342 static int at91_clk_show(struct seq_file *s, void *unused)
5343 {
5344 - u32 scsr, pcsr, sr;
5345 + u32 scsr, pcsr, uckr = 0, sr;
5346 struct clk *clk;
5347
5348 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
5349 @@ -370,7 +410,10 @@
5350 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
5351 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
5352 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
5353 - seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
5354 + if (!cpu_is_at91sam9rl())
5355 + seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
5356 + if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
5357 + seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
5358 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
5359 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
5360
5361 @@ -383,6 +426,8 @@
5362 state = (scsr & clk->pmc_mask) ? "on" : "off";
5363 else if (clk->mode == pmc_periph_mode)
5364 state = (pcsr & clk->pmc_mask) ? "on" : "off";
5365 + else if (clk->mode == pmc_uckr_mode)
5366 + state = (uckr & clk->pmc_mask) ? "on" : "off";
5367 else if (clk->pmc_mask)
5368 state = (sr & clk->pmc_mask) ? "on" : "off";
5369 else if (clk == &clk32k || clk == &main_clk)
5370 @@ -583,6 +628,17 @@
5371 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
5372
5373 /*
5374 + * USB HS clock init
5375 + */
5376 + if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
5377 + /*
5378 + * multiplier is hard-wired to 40
5379 + * (obtain the USB High Speed 480 MHz when input is 12 MHz)
5380 + */
5381 + utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
5382 + }
5383 +
5384 + /*
5385 * MCK and CPU derive from one of those primary clocks.
5386 * For now, assume this parentage won't change.
5387 */
5388 @@ -599,6 +655,9 @@
5389 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
5390 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
5391
5392 + if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
5393 + list_add_tail(&utmi_clk.node, &clocks);
5394 +
5395 /* MCK and CPU clock are "always on" */
5396 clk_enable(&mck);
5397
5398 --- a/arch/arm/mach-at91/generic.h
5399 +++ b/arch/arm/mach-at91/generic.h
5400 @@ -41,6 +41,7 @@
5401 /* Power Management */
5402 extern void at91_irq_suspend(void);
5403 extern void at91_irq_resume(void);
5404 +extern int at91_suspend_entering_slow_clock(void);
5405
5406 /* GPIO */
5407 #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
5408 --- a/arch/arm/mach-at91/gpio.c
5409 +++ b/arch/arm/mach-at91/gpio.c
5410 @@ -490,7 +490,8 @@
5411
5412 /*--------------------------------------------------------------------------*/
5413
5414 -/* This lock class tells lockdep that GPIO irqs are in a different
5415 +/*
5416 + * This lock class tells lockdep that GPIO irqs are in a different
5417 * category than their parents, so it won't report false recursion.
5418 */
5419 static struct lock_class_key gpio_lock_class;
5420 @@ -557,6 +558,7 @@
5421 data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS;
5422
5423 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
5424 + /* AT91CAP9_ID_PIOABCD groups PIOA, PIOB, PIOC, PIOD */
5425 if (last && last->id == data->id)
5426 last->next = data;
5427 }
5428 --- /dev/null
5429 +++ b/arch/arm/mach-at91/ics1523.c
5430 @@ -0,0 +1,208 @@
5431 +/*
5432 + * arch/arm/mach-at91rm9200/ics1523.c
5433 + *
5434 + * Copyright (C) 2003 ATMEL Rousset
5435 + *
5436 + * This program is free software; you can redistribute it and/or modify
5437 + * it under the terms of the GNU General Public License as published by
5438 + * the Free Software Foundation; either version 2 of the License, or
5439 + * (at your option) any later version.
5440 + *
5441 + * This program is distributed in the hope that it will be useful,
5442 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5443 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5444 + * GNU General Public License for more details.
5445 + *
5446 + * You should have received a copy of the GNU General Public License
5447 + * along with this program; if not, write to the Free Software
5448 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5449 + */
5450 +
5451 +#include <asm/hardware.h>
5452 +#include <asm/io.h>
5453 +
5454 +#include <linux/clk.h>
5455 +#include <linux/delay.h>
5456 +#include <linux/err.h>
5457 +#include <linux/init.h>
5458 +#include <linux/kernel.h>
5459 +
5460 +#include <asm/arch/ics1523.h>
5461 +#include <asm/arch/at91_twi.h>
5462 +#include <asm/arch/gpio.h>
5463 +
5464 +/* TWI Errors */
5465 +#define AT91_TWI_ERROR (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE)
5466 +
5467 +
5468 +static void __iomem *twi_base;
5469 +
5470 +#define at91_twi_read(reg) __raw_readl(twi_base + (reg))
5471 +#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg))
5472 +
5473 +
5474 +/* -----------------------------------------------------------------------------
5475 + * Initialization of TWI CLOCK
5476 + * ----------------------------------------------------------------------------- */
5477 +
5478 +static void at91_ics1523_SetTwiClock(unsigned int mck_khz)
5479 +{
5480 + int sclock;
5481 +
5482 + /* Here, CKDIV = 1 and CHDIV = CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
5483 + sclock = (10*mck_khz / ICS_TRANSFER_RATE);
5484 + if (sclock % 10 >= 5)
5485 + sclock = (sclock /10) - 5;
5486 + else
5487 + sclock = (sclock /10)- 6;
5488 + sclock = (sclock + (4 - sclock %4)) >> 2; /* div 4 */
5489 +
5490 + at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8));
5491 +}
5492 +
5493 +/* -----------------------------------------------------------------------------
5494 + * Read a byte with TWI Interface from the Clock Generator ICS1523
5495 + * ----------------------------------------------------------------------------- */
5496 +
5497 +static int at91_ics1523_ReadByte(unsigned char reg_address, unsigned char *data_in)
5498 +{
5499 + int Status, nb_trial;
5500 +
5501 + at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR));
5502 + at91_twi_write(AT91_TWI_IADR, reg_address);
5503 + at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
5504 +
5505 + /* Program temporizing period (300us) */
5506 + udelay(300);
5507 +
5508 + /* Wait TXcomplete ... */
5509 + nb_trial = 0;
5510 + Status = at91_twi_read(AT91_TWI_SR);
5511 + while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
5512 + nb_trial++;
5513 + Status = at91_twi_read(AT91_TWI_SR);
5514 + }
5515 +
5516 + if (Status & AT91_TWI_TXCOMP) {
5517 + *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR);
5518 + return ICS1523_ACCESS_OK;
5519 + }
5520 + else
5521 + return ICS1523_ACCESS_ERROR;
5522 +}
5523 +
5524 +/* -----------------------------------------------------------------------------
5525 + * Write a byte with TWI Interface to the Clock Generator ICS1523
5526 + * ----------------------------------------------------------------------------- */
5527 +
5528 +static int at91_ics1523_WriteByte(unsigned char reg_address, unsigned char data_out)
5529 +{
5530 + int Status, nb_trial;
5531 +
5532 + at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR));
5533 + at91_twi_write(AT91_TWI_IADR, reg_address);
5534 + at91_twi_write(AT91_TWI_THR, data_out);
5535 + at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
5536 +
5537 + /* Program temporizing period (300us) */
5538 + udelay(300);
5539 +
5540 + nb_trial = 0;
5541 + Status = at91_twi_read(AT91_TWI_SR);
5542 + while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
5543 + nb_trial++;
5544 + if (Status & AT91_TWI_ERROR) {
5545 + /* If Underrun OR NACK - Start again */
5546 + at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
5547 +
5548 + /* Program temporizing period (300us) */
5549 + udelay(300);
5550 + }
5551 + Status = at91_twi_read(AT91_TWI_SR);
5552 + };
5553 +
5554 + if (Status & AT91_TWI_TXCOMP)
5555 + return ICS1523_ACCESS_OK;
5556 + else
5557 + return ICS1523_ACCESS_ERROR;
5558 +}
5559 +
5560 +/* -----------------------------------------------------------------------------
5561 + * Initialization of the Clock Generator ICS1523
5562 + * ----------------------------------------------------------------------------- */
5563 +
5564 +int at91_ics1523_init(void)
5565 +{
5566 + int nb_trial;
5567 + int ack = ICS1523_ACCESS_OK;
5568 + unsigned int status = 0xffffffff;
5569 + struct clk *twi_clk;
5570 +
5571 + /* Map in TWI peripheral */
5572 + twi_base = ioremap(AT91RM9200_BASE_TWI, SZ_16K);
5573 + if (!twi_base)
5574 + return -ENOMEM;
5575 +
5576 + /* pins used for TWI interface */
5577 + at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
5578 + at91_set_multi_drive(AT91_PIN_PA25, 1);
5579 + at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
5580 + at91_set_multi_drive(AT91_PIN_PA26, 1);
5581 +
5582 + /* Enable the TWI clock */
5583 + twi_clk = clk_get(NULL, "twi_clk");
5584 + if (IS_ERR(twi_clk))
5585 + return ICS1523_ACCESS_ERROR;
5586 + clk_enable(twi_clk);
5587 +
5588 + /* Disable interrupts */
5589 + at91_twi_write(AT91_TWI_IDR, -1);
5590 +
5591 + /* Reset peripheral */
5592 + at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST);
5593 +
5594 + /* Set Master mode */
5595 + at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);
5596 +
5597 + /* Set TWI Clock Waveform Generator Register */
5598 + at91_ics1523_SetTwiClock(60000); /* MCK in KHz = 60000 KHz */
5599 +
5600 + /* ICS1523 Initialisation */
5601 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0);
5602 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK));
5603 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F));
5604 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0);
5605 +
5606 + nb_trial = 0;
5607 + do {
5608 + nb_trial++;
5609 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/));
5610 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD));
5611 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */
5612 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00);
5613 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR));
5614 +
5615 + /* Program 1ms temporizing period */
5616 + mdelay(1);
5617 +
5618 + at91_ics1523_ReadByte ((unsigned char) ICS_SR, (char *)&status);
5619 + } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10));
5620 +
5621 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */
5622 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR));
5623 +
5624 + /* Program 1ms temporizing period */
5625 + mdelay(1);
5626 +
5627 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00);
5628 +
5629 + /* Program 1ms temporizing period */
5630 + mdelay(1);
5631 +
5632 + /* All done - cleanup */
5633 + iounmap(twi_base);
5634 + clk_disable(twi_clk);
5635 + clk_put(twi_clk);
5636 +
5637 + return ack;
5638 +}
5639 --- a/arch/arm/mach-at91/pm.c
5640 +++ b/arch/arm/mach-at91/pm.c
5641 @@ -26,12 +26,144 @@
5642 #include <asm/mach-types.h>
5643
5644 #include <asm/arch/at91_pmc.h>
5645 -#include <asm/arch/at91rm9200_mc.h>
5646 #include <asm/arch/gpio.h>
5647 #include <asm/arch/cpu.h>
5648
5649 #include "generic.h"
5650
5651 +#ifdef CONFIG_ARCH_AT91RM9200
5652 +#include <asm/arch/at91rm9200_mc.h>
5653 +
5654 +/*
5655 + * The AT91RM9200 goes into self-refresh mode with this command, and will
5656 + * terminate self-refresh automatically on the next SDRAM access.
5657 + */
5658 +#define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1)
5659 +#define sdram_selfrefresh_disable() do {} while (0)
5660 +
5661 +#elif defined(CONFIG_ARCH_AT91CAP9)
5662 +#include <asm/arch/at91cap9_ddrsdr.h>
5663 +
5664 +static u32 saved_lpr;
5665 +
5666 +static inline void sdram_selfrefresh_enable(void)
5667 +{
5668 + u32 lpr;
5669 +
5670 + saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
5671 +
5672 + lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
5673 + at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
5674 +}
5675 +
5676 +#define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
5677 +
5678 +#else
5679 +#include <asm/arch/at91sam9_sdramc.h>
5680 +
5681 +#ifdef CONFIG_ARCH_AT91SAM9263
5682 +/*
5683 + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
5684 + * handle those cases both here and in the Suspend-To-RAM support.
5685 + */
5686 +#define AT91_SDRAMC AT91_SDRAMC0
5687 +#warning Assuming EB1 SDRAM controller is *NOT* used
5688 +#endif
5689 +
5690 +static u32 saved_lpr;
5691 +
5692 +static inline void sdram_selfrefresh_enable(void)
5693 +{
5694 + u32 lpr;
5695 +
5696 + saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
5697 +
5698 + lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
5699 + at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
5700 +}
5701 +
5702 +#define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
5703 +
5704 +/*
5705 + * FIXME: The AT91SAM9263 has a second EBI controller which may have
5706 + * additional SDRAM. pm_slowclock.S will require a similar fix.
5707 + */
5708 +
5709 +#endif
5710 +
5711 +
5712 +/*
5713 + * Show the reason for the previous system reset.
5714 + */
5715 +#if defined(AT91_SHDWC)
5716 +
5717 +#include <asm/arch/at91_rstc.h>
5718 +#include <asm/arch/at91_shdwc.h>
5719 +
5720 +static void __init show_reset_status(void)
5721 +{
5722 + static char reset[] __initdata = "reset";
5723 +
5724 + static char general[] __initdata = "general";
5725 + static char wakeup[] __initdata = "wakeup";
5726 + static char watchdog[] __initdata = "watchdog";
5727 + static char software[] __initdata = "software";
5728 + static char user[] __initdata = "user";
5729 + static char unknown[] __initdata = "unknown";
5730 +
5731 + static char signal[] __initdata = "signal";
5732 + static char rtc[] __initdata = "rtc";
5733 + static char rtt[] __initdata = "rtt";
5734 + static char restore[] __initdata = "power-restored";
5735 +
5736 + char *reason, *r2 = reset;
5737 + u32 reset_type, wake_type;
5738 +
5739 + reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
5740 + wake_type = at91_sys_read(AT91_SHDW_SR);
5741 +
5742 + switch (reset_type) {
5743 + case AT91_RSTC_RSTTYP_GENERAL:
5744 + reason = general;
5745 + break;
5746 + case AT91_RSTC_RSTTYP_WAKEUP:
5747 + /* board-specific code enabled the wakeup sources */
5748 + reason = wakeup;
5749 +
5750 + /* "wakeup signal" */
5751 + if (wake_type & AT91_SHDW_WAKEUP0)
5752 + r2 = signal;
5753 + else {
5754 + r2 = reason;
5755 + if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */
5756 + reason = rtt;
5757 + else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */
5758 + reason = rtc;
5759 + else if (wake_type == 0) /* power-restored wakeup */
5760 + reason = restore;
5761 + else /* unknown wakeup */
5762 + reason = unknown;
5763 + }
5764 + break;
5765 + case AT91_RSTC_RSTTYP_WATCHDOG:
5766 + reason = watchdog;
5767 + break;
5768 + case AT91_RSTC_RSTTYP_SOFTWARE:
5769 + reason = software;
5770 + break;
5771 + case AT91_RSTC_RSTTYP_USER:
5772 + reason = user;
5773 + break;
5774 + default:
5775 + reason = unknown;
5776 + break;
5777 + }
5778 + pr_info("AT91: Starting after %s %s\n", reason, r2);
5779 +}
5780 +#else
5781 +static void __init show_reset_status(void) {}
5782 +#endif
5783 +
5784
5785 static int at91_pm_valid_state(suspend_state_t state)
5786 {
5787 @@ -62,6 +194,7 @@
5788 * Verify that all the clocks are correct before entering
5789 * slow-clock mode.
5790 */
5791 +#warning "This should probably be moved to clocks.c"
5792 static int at91_pm_verify_clocks(void)
5793 {
5794 unsigned long scsr;
5795 @@ -107,24 +240,24 @@
5796 }
5797
5798 /*
5799 - * Call this from platform driver suspend() to see how deeply to suspend.
5800 + * This is called from clk_must_disable(), to see how deeply to suspend.
5801 * For example, some controllers (like OHCI) need one of the PLL clocks
5802 * in order to act as a wakeup source, and those are not available when
5803 * going into slow clock mode.
5804 - *
5805 - * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
5806 - * the very same problem (but not using at91 main_clk), and it'd be better
5807 - * to add one generic API rather than lots of platform-specific ones.
5808 */
5809 int at91_suspend_entering_slow_clock(void)
5810 {
5811 return (target_state == PM_SUSPEND_MEM);
5812 }
5813 -EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
5814
5815
5816 static void (*slow_clock)(void);
5817
5818 +#ifdef CONFIG_AT91_SLOW_CLOCK
5819 +extern void at91_slow_clock(void);
5820 +extern u32 at91_slow_clock_sz;
5821 +#endif
5822 +
5823
5824 static int at91_pm_enter(suspend_state_t state)
5825 {
5826 @@ -158,11 +291,14 @@
5827 * turning off the main oscillator; reverse on wakeup.
5828 */
5829 if (slow_clock) {
5830 +#ifdef CONFIG_AT91_SLOW_CLOCK
5831 + /* copy slow_clock handler to SRAM, and call it */
5832 + memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
5833 +#endif
5834 slow_clock();
5835 break;
5836 } else {
5837 - /* DEVELOPMENT ONLY */
5838 - pr_info("AT91: PM - no slow clock mode yet ...\n");
5839 + pr_info("AT91: PM - no slow clock mode enabled ...\n");
5840 /* FALLTHROUGH leaving master clock alone */
5841 }
5842
5843 @@ -175,13 +311,15 @@
5844 case PM_SUSPEND_STANDBY:
5845 /*
5846 * NOTE: the Wait-for-Interrupt instruction needs to be
5847 - * in icache so the SDRAM stays in self-refresh mode until
5848 - * the wakeup IRQ occurs.
5849 + * in icache so no SDRAM accesses are needed until the
5850 + * wakeup IRQ occurs and self-refresh is terminated.
5851 */
5852 asm("b 1f; .align 5; 1:");
5853 asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
5854 - at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */
5855 - /* fall though to next state */
5856 + sdram_selfrefresh_enable();
5857 + asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
5858 + sdram_selfrefresh_disable();
5859 + break;
5860
5861 case PM_SUSPEND_ON:
5862 asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
5863 @@ -196,6 +334,7 @@
5864 at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
5865
5866 error:
5867 + sdram_selfrefresh_disable();
5868 target_state = PM_SUSPEND_ON;
5869 at91_irq_resume();
5870 at91_gpio_resume();
5871 @@ -220,21 +359,20 @@
5872
5873 static int __init at91_pm_init(void)
5874 {
5875 - printk("AT91: Power Management\n");
5876 -
5877 -#ifdef CONFIG_AT91_PM_SLOW_CLOCK
5878 - /* REVISIT allocations of SRAM should be dynamically managed.
5879 - * FIQ handlers and other components will want SRAM/TCM too...
5880 - */
5881 - slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
5882 - memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
5883 +#ifdef CONFIG_AT91_SLOW_CLOCK
5884 + slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
5885 #endif
5886
5887 - /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */
5888 + pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
5889 +
5890 +#ifdef CONFIG_ARCH_AT91RM9200
5891 + /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
5892 at91_sys_write(AT91_SDRAMC_LPR, 0);
5893 +#endif
5894
5895 suspend_set_ops(&at91_pm_ops);
5896
5897 + show_reset_status();
5898 return 0;
5899 }
5900 arch_initcall(at91_pm_init);
5901 --- /dev/null
5902 +++ b/arch/arm/mach-at91/pm_slowclock.S
5903 @@ -0,0 +1,283 @@
5904 +/*
5905 + * arch/arm/mach-at91/pm_slow_clock.S
5906 + *
5907 + * Copyright (C) 2006 Savin Zlobec
5908 + *
5909 + * AT91SAM9 support:
5910 + * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
5911 + *
5912 + * This program is free software; you can redistribute it and/or modify
5913 + * it under the terms of the GNU General Public License version 2 as
5914 + * published by the Free Software Foundation.
5915 + *
5916 + */
5917 +
5918 +#include <linux/linkage.h>
5919 +#include <asm/hardware.h>
5920 +#include <asm/arch/at91_pmc.h>
5921 +
5922 +#ifdef CONFIG_ARCH_AT91RM9200
5923 +#include <asm/arch/at91rm9200_mc.h>
5924 +#elif defined(CONFIG_ARCH_AT91CAP9)
5925 +#include <asm/arch/at91cap9_ddrsdr.h>
5926 +#else
5927 +#include <asm/arch/at91sam9_sdramc.h>
5928 +#endif
5929 +
5930 +
5931 +#ifdef CONFIG_ARCH_AT91SAM9263
5932 +/*
5933 + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
5934 + * handle those cases both here and in the Suspend-To-RAM support.
5935 + */
5936 +#define AT91_SDRAMC AT91_SDRAMC0
5937 +#warning Assuming EB1 SDRAM controller is *NOT* used
5938 +#endif
5939 +
5940 +/*
5941 + * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
5942 + * clock during suspend by adjusting its prescalar and divisor.
5943 + * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
5944 + * are errata regarding adjusting the prescalar and divisor.
5945 + */
5946 +#undef SLOWDOWN_MASTER_CLOCK
5947 +
5948 +#define MCKRDY_TIMEOUT 1000
5949 +#define MOSCRDY_TIMEOUT 1000
5950 +#define PLLALOCK_TIMEOUT 1000
5951 +#define PLLBLOCK_TIMEOUT 1000
5952 +
5953 +
5954 +/*
5955 + * Wait until master clock is ready (after switching master clock source)
5956 + */
5957 + .macro wait_mckrdy
5958 + mov r4, #MCKRDY_TIMEOUT
5959 +1: sub r4, r4, #1
5960 + cmp r4, #0
5961 + beq 2f
5962 + ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
5963 + tst r3, #AT91_PMC_MCKRDY
5964 + beq 1b
5965 +2:
5966 + .endm
5967 +
5968 +/*
5969 + * Wait until master oscillator has stabilized.
5970 + */
5971 + .macro wait_moscrdy
5972 + mov r4, #MOSCRDY_TIMEOUT
5973 +1: sub r4, r4, #1
5974 + cmp r4, #0
5975 + beq 2f
5976 + ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
5977 + tst r3, #AT91_PMC_MOSCS
5978 + beq 1b
5979 +2:
5980 + .endm
5981 +
5982 +/*
5983 + * Wait until PLLA has locked.
5984 + */
5985 + .macro wait_pllalock
5986 + mov r4, #PLLALOCK_TIMEOUT
5987 +1: sub r4, r4, #1
5988 + cmp r4, #0
5989 + beq 2f
5990 + ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
5991 + tst r3, #AT91_PMC_LOCKA
5992 + beq 1b
5993 +2:
5994 + .endm
5995 +
5996 +/*
5997 + * Wait until PLLB has locked.
5998 + */
5999 + .macro wait_pllblock
6000 + mov r4, #PLLBLOCK_TIMEOUT
6001 +1: sub r4, r4, #1
6002 + cmp r4, #0
6003 + beq 2f
6004 + ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
6005 + tst r3, #AT91_PMC_LOCKB
6006 + beq 1b
6007 +2:
6008 + .endm
6009 +
6010 + .text
6011 +
6012 +ENTRY(at91_slow_clock)
6013 + /* Save registers on stack */
6014 + stmfd sp!, {r0 - r12, lr}
6015 +
6016 + /*
6017 + * Register usage:
6018 + * R1 = Base address of AT91_PMC
6019 + * R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
6020 + * R3 = temporary register
6021 + * R4 = temporary register
6022 + */
6023 + ldr r1, .at91_va_base_pmc
6024 + ldr r2, .at91_va_base_sdramc
6025 +
6026 + /* Drain write buffer */
6027 + mcr p15, 0, r0, c7, c10, 4
6028 +
6029 +#ifdef CONFIG_ARCH_AT91RM9200
6030 + /* Put SDRAM in self-refresh mode */
6031 + mov r3, #1
6032 + str r3, [r2, #AT91_SDRAMC_SRR]
6033 +#elif defined(CONFIG_ARCH_AT91CAP9)
6034 + /* Enable SDRAM self-refresh mode */
6035 + ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
6036 + str r3, .saved_sam9_lpr
6037 +
6038 + mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
6039 + str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
6040 +#else
6041 + /* Enable SDRAM self-refresh mode */
6042 + ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
6043 + str r3, .saved_sam9_lpr
6044 +
6045 + mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
6046 + str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
6047 +#endif
6048 +
6049 + /* Save Master clock setting */
6050 + ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
6051 + str r3, .saved_mckr
6052 +
6053 + /*
6054 + * Set the Master clock source to slow clock
6055 + */
6056 + bic r3, r3, #AT91_PMC_CSS
6057 + str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
6058 +
6059 + wait_mckrdy
6060 +
6061 +#ifdef SLOWDOWN_MASTER_CLOCK
6062 + /*
6063 + * Set the Master Clock PRES and MDIV fields.
6064 + *
6065 + * See AT91RM9200 errata #27 and #28 for details.
6066 + */
6067 + mov r3, #0
6068 + str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
6069 +
6070 + wait_mckrdy
6071 +#endif
6072 +
6073 + /* Save PLLA setting and disable it */
6074 + ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
6075 + str r3, .saved_pllar
6076 +
6077 + mov r3, #AT91_PMC_PLLCOUNT
6078 + orr r3, r3, #(1 << 29) /* bit 29 always set */
6079 + str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
6080 +
6081 + wait_pllalock
6082 +
6083 + /* Save PLLB setting and disable it */
6084 + ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
6085 + str r3, .saved_pllbr
6086 +
6087 + mov r3, #AT91_PMC_PLLCOUNT
6088 + str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
6089 +
6090 + wait_pllblock
6091 +
6092 + /* Turn off the main oscillator */
6093 + ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
6094 + bic r3, r3, #AT91_PMC_MOSCEN
6095 + str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
6096 +
6097 + /* Wait for interrupt */
6098 + mcr p15, 0, r0, c7, c0, 4
6099 +
6100 + /* Turn on the main oscillator */
6101 + ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
6102 + orr r3, r3, #AT91_PMC_MOSCEN
6103 + str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
6104 +
6105 + wait_moscrdy
6106 +
6107 + /* Restore PLLB setting */
6108 + ldr r3, .saved_pllbr
6109 + str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
6110 +
6111 + wait_pllblock
6112 +
6113 + /* Restore PLLA setting */
6114 + ldr r3, .saved_pllar
6115 + str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
6116 +
6117 + wait_pllalock
6118 +
6119 +#ifdef SLOWDOWN_MASTER_CLOCK
6120 + /*
6121 + * First set PRES if it was not 0,
6122 + * than set CSS and MDIV fields.
6123 + *
6124 + * See AT91RM9200 errata #27 and #28 for details.
6125 + */
6126 + ldr r3, .saved_mckr
6127 + tst r3, #AT91_PMC_PRES
6128 + beq 2f
6129 + and r3, r3, #AT91_PMC_PRES
6130 + str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
6131 +
6132 + wait_mckrdy
6133 +#endif
6134 +
6135 + /*
6136 + * Restore master clock setting
6137 + */
6138 +2: ldr r3, .saved_mckr
6139 + str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
6140 +
6141 + wait_mckrdy
6142 +
6143 +#ifdef CONFIG_ARCH_AT91RM9200
6144 + /* Do nothing - self-refresh is automatically disabled. */
6145 +#elif defined(CONFIG_ARCH_AT91CAP9)
6146 + /* Restore LPR on AT91CAP9 */
6147 + ldr r3, .saved_sam9_lpr
6148 + str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
6149 +#else
6150 + /* Restore LPR on AT91SAM9 */
6151 + ldr r3, .saved_sam9_lpr
6152 + str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
6153 +#endif
6154 +
6155 + /* Restore registers, and return */
6156 + ldmfd sp!, {r0 - r12, pc}
6157 +
6158 +
6159 +.saved_mckr:
6160 + .word 0
6161 +
6162 +.saved_pllar:
6163 + .word 0
6164 +
6165 +.saved_pllbr:
6166 + .word 0
6167 +
6168 +.saved_sam9_lpr:
6169 + .word 0
6170 +
6171 +.at91_va_base_pmc:
6172 + .word AT91_VA_BASE_SYS + AT91_PMC
6173 +
6174 +#ifdef CONFIG_ARCH_AT91RM9200
6175 +.at91_va_base_sdramc:
6176 + .word AT91_VA_BASE_SYS
6177 +#elif defined(CONFIG_ARCH_AT91CAP9)
6178 +.at91_va_base_sdramc:
6179 + .word AT91_VA_BASE_SYS + AT91_DDRSDRC
6180 +#else
6181 +.at91_va_base_sdramc:
6182 + .word AT91_VA_BASE_SYS + AT91_SDRAMC
6183 +#endif
6184 +
6185 +ENTRY(at91_slow_clock_sz)
6186 + .word .-at91_slow_clock
6187 --- a/arch/arm/mach-ks8695/Makefile
6188 +++ b/arch/arm/mach-ks8695/Makefile
6189 @@ -11,5 +11,8 @@
6190 # PCI support is optional
6191 obj-$(CONFIG_PCI) += pci.o
6192
6193 +# LEDs
6194 +obj-$(CONFIG_LEDS) += leds.o
6195 +
6196 # Board-specific support
6197 obj-$(CONFIG_MACH_KS8695) += board-micrel.o
6198 --- a/arch/arm/mach-ks8695/devices.c
6199 +++ b/arch/arm/mach-ks8695/devices.c
6200 @@ -176,6 +176,27 @@
6201 #endif
6202
6203
6204 +/* --------------------------------------------------------------------
6205 + * LEDs
6206 + * -------------------------------------------------------------------- */
6207 +
6208 +#if defined(CONFIG_LEDS)
6209 +short ks8695_leds_cpu = -1;
6210 +short ks8695_leds_timer = -1;
6211 +
6212 +void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
6213 +{
6214 + /* Enable GPIO to access the LEDs */
6215 + gpio_direction_output(cpu_led, 1);
6216 + gpio_direction_output(timer_led, 1);
6217 +
6218 + ks8695_leds_cpu = cpu_led;
6219 + ks8695_leds_timer = timer_led;
6220 +}
6221 +#else
6222 +void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
6223 +#endif
6224 +
6225 /* -------------------------------------------------------------------- */
6226
6227 /*
6228 --- a/arch/arm/mach-ks8695/gpio.c
6229 +++ b/arch/arm/mach-ks8695/gpio.c
6230 @@ -136,9 +136,9 @@
6231 /* set line state */
6232 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
6233 if (state)
6234 - x |= (1 << pin);
6235 + x |= IOPD_(pin);
6236 else
6237 - x &= ~(1 << pin);
6238 + x &= ~IOPD_(pin);
6239 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
6240
6241 /* set pin as output */
6242 @@ -168,9 +168,9 @@
6243 /* set output line state */
6244 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
6245 if (state)
6246 - x |= (1 << pin);
6247 + x |= IOPD_(pin);
6248 else
6249 - x &= ~(1 << pin);
6250 + x &= ~IOPD_(pin);
6251 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
6252
6253 local_irq_restore(flags);
6254 @@ -189,7 +189,7 @@
6255 return -EINVAL;
6256
6257 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
6258 - return (x & (1 << pin)) != 0;
6259 + return (x & IOPD_(pin)) != 0;
6260 }
6261 EXPORT_SYMBOL(gpio_get_value);
6262
6263 --- /dev/null
6264 +++ b/arch/arm/mach-ks8695/leds.c
6265 @@ -0,0 +1,94 @@
6266 +/*
6267 + * LED driver for KS8695-based boards.
6268 + *
6269 + * Copyright (C) Andrew Victor
6270 + *
6271 + * This program is free software; you can redistribute it and/or modify
6272 + * it under the terms of the GNU General Public License version 2 as
6273 + * published by the Free Software Foundation.
6274 + */
6275 +
6276 +#include <linux/kernel.h>
6277 +#include <linux/module.h>
6278 +#include <linux/init.h>
6279 +
6280 +#include <asm/mach-types.h>
6281 +#include <asm/leds.h>
6282 +#include <asm/arch/devices.h>
6283 +#include <asm/arch/gpio.h>
6284 +
6285 +
6286 +static inline void ks8695_led_on(unsigned int led)
6287 +{
6288 + gpio_set_value(led, 0);
6289 +}
6290 +
6291 +static inline void ks8695_led_off(unsigned int led)
6292 +{
6293 + gpio_set_value(led, 1);
6294 +}
6295 +
6296 +static inline void ks8695_led_toggle(unsigned int led)
6297 +{
6298 + unsigned long is_off = gpio_get_value(led);
6299 + if (is_off)
6300 + ks8695_led_on(led);
6301 + else
6302 + ks8695_led_off(led);
6303 +}
6304 +
6305 +
6306 +/*
6307 + * Handle LED events.
6308 + */
6309 +static void ks8695_leds_event(led_event_t evt)
6310 +{
6311 + unsigned long flags;
6312 +
6313 + local_irq_save(flags);
6314 +
6315 + switch(evt) {
6316 + case led_start: /* System startup */
6317 + ks8695_led_on(ks8695_leds_cpu);
6318 + break;
6319 +
6320 + case led_stop: /* System stop / suspend */
6321 + ks8695_led_off(ks8695_leds_cpu);
6322 + break;
6323 +
6324 +#ifdef CONFIG_LEDS_TIMER
6325 + case led_timer: /* Every 50 timer ticks */
6326 + ks8695_led_toggle(ks8695_leds_timer);
6327 + break;
6328 +#endif
6329 +
6330 +#ifdef CONFIG_LEDS_CPU
6331 + case led_idle_start: /* Entering idle state */
6332 + ks8695_led_off(ks8695_leds_cpu);
6333 + break;
6334 +
6335 + case led_idle_end: /* Exit idle state */
6336 + ks8695_led_on(ks8695_leds_cpu);
6337 + break;
6338 +#endif
6339 +
6340 + default:
6341 + break;
6342 + }
6343 +
6344 + local_irq_restore(flags);
6345 +}
6346 +
6347 +
6348 +static int __init leds_init(void)
6349 +{
6350 + if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
6351 + return -ENODEV;
6352 +
6353 + leds_event = ks8695_leds_event;
6354 +
6355 + leds_event(led_start);
6356 + return 0;
6357 +}
6358 +
6359 +__initcall(leds_init);
6360 --- a/arch/arm/mach-ks8695/pci.c
6361 +++ b/arch/arm/mach-ks8695/pci.c
6362 @@ -141,7 +141,7 @@
6363 .write = ks8695_pci_writeconfig,
6364 };
6365
6366 -static struct pci_bus *ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
6367 +static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
6368 {
6369 return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys);
6370 }
6371 --- a/drivers/char/Kconfig
6372 +++ b/drivers/char/Kconfig
6373 @@ -1056,5 +1056,21 @@
6374
6375 source "drivers/s390/char/Kconfig"
6376
6377 +config AT91_SPI
6378 + bool "SPI driver (legacy) for AT91RM9200 processors"
6379 + depends on ARCH_AT91RM9200
6380 + default y
6381 + help
6382 + The SPI driver gives access to this serial bus on the AT91RM9200
6383 + processor.
6384 +
6385 +config AT91_SPIDEV
6386 + bool "SPI device interface (legacy) for AT91RM9200 processors"
6387 + depends on ARCH_AT91RM9200 && AT91_SPI
6388 + default n
6389 + help
6390 + The SPI driver gives user mode access to this serial
6391 + bus on the AT91RM9200 processor.
6392 +
6393 endmenu
6394
6395 --- a/drivers/char/Makefile
6396 +++ b/drivers/char/Makefile
6397 @@ -98,6 +98,8 @@
6398 obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
6399 obj-$(CONFIG_GPIO_TB0219) += tb0219.o
6400 obj-$(CONFIG_TELCLOCK) += tlclk.o
6401 +obj-$(CONFIG_AT91_SPI) += at91_spi.o
6402 +obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o
6403
6404 obj-$(CONFIG_MWAVE) += mwave/
6405 obj-$(CONFIG_AGP) += agp/
6406 --- /dev/null
6407 +++ b/drivers/char/at91_spi.c
6408 @@ -0,0 +1,337 @@
6409 +/*
6410 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
6411 + *
6412 + * Copyright (C) SAN People (Pty) Ltd
6413 + *
6414 + * This program is free software; you can redistribute it and/or
6415 + * modify it under the terms of the GNU General Public License
6416 + * as published by the Free Software Foundation; either version
6417 + * 2 of the License, or (at your option) any later version.
6418 + */
6419 +
6420 +#include <linux/init.h>
6421 +#include <linux/dma-mapping.h>
6422 +#include <linux/module.h>
6423 +#include <linux/sched.h>
6424 +#include <linux/completion.h>
6425 +#include <linux/interrupt.h>
6426 +#include <linux/clk.h>
6427 +#include <linux/platform_device.h>
6428 +#include <linux/atmel_pdc.h>
6429 +#include <asm/io.h>
6430 +#include <asm/semaphore.h>
6431 +
6432 +#include <asm/arch/at91_spi.h>
6433 +#include <asm/arch/board.h>
6434 +#include <asm/arch/spi.h>
6435 +
6436 +#undef DEBUG_SPI
6437 +
6438 +static struct spi_local spi_dev[NR_SPI_DEVICES]; /* state of the SPI devices */
6439 +static int spi_enabled = 0;
6440 +static struct semaphore spi_lock; /* protect access to SPI bus */
6441 +static int current_device = -1; /* currently selected SPI device */
6442 +static struct clk *spi_clk; /* SPI clock */
6443 +static void __iomem *spi_base; /* SPI peripheral base-address */
6444 +
6445 +DECLARE_COMPLETION(transfer_complete);
6446 +
6447 +
6448 +#define at91_spi_read(reg) __raw_readl(spi_base + (reg))
6449 +#define at91_spi_write(reg, val) __raw_writel((val), spi_base + (reg))
6450 +
6451 +
6452 +/* ......................................................................... */
6453 +
6454 +/*
6455 + * Access and enable the SPI bus.
6456 + * This MUST be called before any transfers are performed.
6457 + */
6458 +void spi_access_bus(short device)
6459 +{
6460 + /* Ensure that requested device is valid */
6461 + if ((device < 0) || (device >= NR_SPI_DEVICES))
6462 + panic("at91_spi: spi_access_bus called with invalid device");
6463 +
6464 + if (spi_enabled == 0) {
6465 + clk_enable(spi_clk); /* Enable Peripheral clock */
6466 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */
6467 +#ifdef DEBUG_SPI
6468 + printk("SPI on\n");
6469 +#endif
6470 + }
6471 + spi_enabled++;
6472 +
6473 + /* Lock the SPI bus */
6474 + down(&spi_lock);
6475 + current_device = device;
6476 +
6477 + /* Configure SPI bus for device */
6478 + at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16));
6479 +}
6480 +
6481 +/*
6482 + * Relinquish control of the SPI bus.
6483 + */
6484 +void spi_release_bus(short device)
6485 +{
6486 + if (device != current_device)
6487 + panic("at91_spi: spi_release called with invalid device");
6488 +
6489 + /* Release the SPI bus */
6490 + current_device = -1;
6491 + up(&spi_lock);
6492 +
6493 + spi_enabled--;
6494 + if (spi_enabled == 0) {
6495 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */
6496 + clk_disable(spi_clk); /* Disable Peripheral clock */
6497 +#ifdef DEBUG_SPI
6498 + printk("SPI off\n");
6499 +#endif
6500 + }
6501 +}
6502 +
6503 +/*
6504 + * Perform a data transfer over the SPI bus
6505 + */
6506 +int spi_transfer(struct spi_transfer_list* list)
6507 +{
6508 + struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
6509 + int tx_size;
6510 +
6511 + if (!list)
6512 + panic("at91_spi: spi_transfer called with NULL transfer list");
6513 + if (current_device == -1)
6514 + panic("at91_spi: spi_transfer called without acquiring bus");
6515 +
6516 +#ifdef DEBUG_SPI
6517 + printk("SPI transfer start [%i]\n", list->nr_transfers);
6518 +#endif
6519 +
6520 + /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
6521 + tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
6522 +
6523 + /* Store transfer list */
6524 + device->xfers = list;
6525 + list->curr = 0;
6526 +
6527 + /* Assume there must be at least one transfer */
6528 + device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE);
6529 + device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE);
6530 +
6531 + /* Program PDC registers */
6532 + at91_spi_write(ATMEL_PDC_TPR, device->tx);
6533 + at91_spi_write(ATMEL_PDC_RPR, device->rx);
6534 + at91_spi_write(ATMEL_PDC_TCR, list->txlen[0] / tx_size);
6535 + at91_spi_write(ATMEL_PDC_RCR, list->rxlen[0] / tx_size);
6536 +
6537 + /* Is there a second transfer? */
6538 + if (list->nr_transfers > 1) {
6539 + device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE);
6540 + device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE);
6541 +
6542 + /* Program Next PDC registers */
6543 + at91_spi_write(ATMEL_PDC_TNPR, device->txnext);
6544 + at91_spi_write(ATMEL_PDC_RNPR, device->rxnext);
6545 + at91_spi_write(ATMEL_PDC_TNCR, list->txlen[1] / tx_size);
6546 + at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[1] / tx_size);
6547 + }
6548 + else {
6549 + device->txnext = 0;
6550 + device->rxnext = 0;
6551 + at91_spi_write(ATMEL_PDC_TNCR, 0);
6552 + at91_spi_write(ATMEL_PDC_RNCR, 0);
6553 + }
6554 +
6555 + // TODO: If we are doing consecutive transfers (at high speed, or
6556 + // small buffers), then it might be worth modifying the 'Delay between
6557 + // Consecutive Transfers' in the CSR registers.
6558 + // This is an issue if we cannot chain the next buffer fast enough
6559 + // in the interrupt handler.
6560 +
6561 + /* Enable transmitter and receiver */
6562 + at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN | ATMEL_PDC_TXTEN);
6563 +
6564 + at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX); /* enable buffer complete interrupt */
6565 + wait_for_completion(&transfer_complete);
6566 +
6567 +#ifdef DEBUG_SPI
6568 + printk("SPI transfer end\n");
6569 +#endif
6570 +
6571 + return 0;
6572 +}
6573 +
6574 +/* ......................................................................... */
6575 +
6576 +/*
6577 + * Handle interrupts from the SPI controller.
6578 + */
6579 +static irqreturn_t at91spi_interrupt(int irq, void *dev_id)
6580 +{
6581 + unsigned int status;
6582 + struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
6583 + struct spi_transfer_list *list = device->xfers;
6584 +
6585 +#ifdef DEBUG_SPI
6586 + printk("SPI interrupt %i\n", current_device);
6587 +#endif
6588 +
6589 + if (!list)
6590 + panic("at91_spi: spi_interrupt with a NULL transfer list");
6591 +
6592 + status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR); /* read status */
6593 +
6594 + dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE);
6595 + dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE);
6596 +
6597 + device->tx = device->txnext; /* move next transfer to current transfer */
6598 + device->rx = device->rxnext;
6599 +
6600 + list->curr = list->curr + 1;
6601 + if (list->curr == list->nr_transfers) { /* all transfers complete */
6602 + at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX); /* disable interrupt */
6603 +
6604 + /* Disable transmitter and receiver */
6605 + at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
6606 +
6607 + device->xfers = NULL;
6608 + complete(&transfer_complete);
6609 + }
6610 + else if (list->curr+1 == list->nr_transfers) { /* no more next transfers */
6611 + device->txnext = 0;
6612 + device->rxnext = 0;
6613 + at91_spi_write(ATMEL_PDC_TNCR, 0);
6614 + at91_spi_write(ATMEL_PDC_RNCR, 0);
6615 + }
6616 + else {
6617 + int i = (list->curr)+1;
6618 +
6619 + /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
6620 + int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
6621 +
6622 + device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE);
6623 + device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE);
6624 + at91_spi_write(ATMEL_PDC_TNPR, device->txnext);
6625 + at91_spi_write(ATMEL_PDC_RNPR, device->rxnext);
6626 + at91_spi_write(ATMEL_PDC_TNCR, list->txlen[i] / tx_size);
6627 + at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[i] / tx_size);
6628 + }
6629 + return IRQ_HANDLED;
6630 +}
6631 +
6632 +/* ......................................................................... */
6633 +
6634 +/*
6635 + * Initialize the SPI controller
6636 + */
6637 +static int __init at91spi_probe(struct platform_device *pdev)
6638 +{
6639 + int i;
6640 + unsigned long scbr;
6641 + struct resource *res;
6642 +
6643 + init_MUTEX(&spi_lock);
6644 +
6645 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6646 + if (!res)
6647 + return -ENXIO;
6648 +
6649 + if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi"))
6650 + return -EBUSY;
6651 +
6652 + spi_base = ioremap(res->start, res->end - res->start + 1);
6653 + if (!spi_base) {
6654 + release_mem_region(res->start, res->end - res->start + 1);
6655 + return -ENOMEM;
6656 + }
6657 +
6658 + spi_clk = clk_get(NULL, "spi_clk");
6659 + if (IS_ERR(spi_clk)) {
6660 + printk(KERN_ERR "at91_spi: no clock defined\n");
6661 + iounmap(spi_base);
6662 + release_mem_region(res->start, res->end - res->start + 1);
6663 + return -ENODEV;
6664 + }
6665 +
6666 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST); /* software reset of SPI controller */
6667 +
6668 + /*
6669 + * Calculate the correct SPI baud-rate divisor.
6670 + */
6671 + scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK);
6672 + scbr = scbr + 1; /* round up */
6673 +
6674 + printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr));
6675 +
6676 + /* Set Chip Select registers to good defaults */
6677 + for (i = 0; i < 4; i++) {
6678 + at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8));
6679 + }
6680 +
6681 + at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
6682 +
6683 + memset(&spi_dev, 0, sizeof(spi_dev));
6684 + spi_dev[0].pcs = 0xE;
6685 + spi_dev[1].pcs = 0xD;
6686 + spi_dev[2].pcs = 0xB;
6687 + spi_dev[3].pcs = 0x7;
6688 +
6689 + if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) {
6690 + clk_put(spi_clk);
6691 + iounmap(spi_base);
6692 + release_mem_region(res->start, res->end - res->start + 1);
6693 + return -EBUSY;
6694 + }
6695 +
6696 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */
6697 +
6698 + return 0;
6699 +}
6700 +
6701 +static int __devexit at91spi_remove(struct platform_device *pdev)
6702 +{
6703 + struct resource *res;
6704 +
6705 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */
6706 + clk_put(spi_clk);
6707 +
6708 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6709 + iounmap(spi_base);
6710 + release_mem_region(res->start, res->end - res->start + 1);
6711 +
6712 + free_irq(AT91RM9200_ID_SPI, 0);
6713 + return 0;
6714 +}
6715 +
6716 +static struct platform_driver at91spi_driver = {
6717 + .probe = at91spi_probe,
6718 + .remove = __devexit_p(at91spi_remove),
6719 + .driver = {
6720 + .name = "at91_spi",
6721 + .owner = THIS_MODULE,
6722 + },
6723 +};
6724 +
6725 +static int __init at91spi_init(void)
6726 +{
6727 + return platform_driver_register(&at91spi_driver);
6728 +}
6729 +
6730 +static void __exit at91spi_exit(void)
6731 +{
6732 + platform_driver_unregister(&at91spi_driver);
6733 +}
6734 +
6735 +EXPORT_SYMBOL(spi_access_bus);
6736 +EXPORT_SYMBOL(spi_release_bus);
6737 +EXPORT_SYMBOL(spi_transfer);
6738 +
6739 +module_init(at91spi_init);
6740 +module_exit(at91spi_exit);
6741 +
6742 +MODULE_LICENSE("GPL")
6743 +MODULE_AUTHOR("Andrew Victor")
6744 +MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200")
6745 +MODULE_ALIAS("platform:at91_spi");
6746 --- /dev/null
6747 +++ b/drivers/char/at91_spidev.c
6748 @@ -0,0 +1,233 @@
6749 +/*
6750 + * User-space interface to the SPI bus on Atmel AT91RM9200
6751 + *
6752 + * Copyright (C) 2003 SAN People (Pty) Ltd
6753 + *
6754 + * Based on SPI driver by Rick Bronson
6755 + *
6756 + * This program is free software; you can redistribute it and/or
6757 + * modify it under the terms of the GNU General Public License
6758 + * as published by the Free Software Foundation; either version
6759 + * 2 of the License, or (at your option) any later version.
6760 + */
6761 +
6762 +#include <linux/module.h>
6763 +#include <linux/init.h>
6764 +#include <linux/slab.h>
6765 +#include <linux/highmem.h>
6766 +#include <linux/pagemap.h>
6767 +#include <asm/arch/spi.h>
6768 +
6769 +#ifdef CONFIG_DEVFS_FS
6770 +#include <linux/devfs_fs_kernel.h>
6771 +#endif
6772 +
6773 +
6774 +#undef DEBUG_SPIDEV
6775 +
6776 +/* ......................................................................... */
6777 +
6778 +/*
6779 + * Read or Write to SPI bus.
6780 + */
6781 +static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset)
6782 +{
6783 + unsigned int spi_device = (unsigned int) file->private_data;
6784 +
6785 + struct mm_struct * mm;
6786 + struct page ** maplist;
6787 + struct spi_transfer_list* list;
6788 + int pgcount;
6789 +
6790 + unsigned int ofs, pagelen;
6791 + int res, i, err;
6792 +
6793 + if (!count) {
6794 + return 0;
6795 + }
6796 +
6797 + list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
6798 + if (!list) {
6799 + return -ENOMEM;
6800 + }
6801 +
6802 + mm = current->mm;
6803 +
6804 + pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE;
6805 +
6806 + if (pgcount >= MAX_SPI_TRANSFERS) {
6807 + kfree(list);
6808 + return -EFBIG;
6809 + }
6810 +
6811 + maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL);
6812 +
6813 + if (!maplist) {
6814 + kfree(list);
6815 + return -ENOMEM;
6816 + }
6817 + flush_cache_all();
6818 + down_read(&mm->mmap_sem);
6819 + err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);
6820 + up_read(&mm->mmap_sem);
6821 +
6822 + if (err < 0) {
6823 + kfree(list);
6824 + kfree(maplist);
6825 + return err;
6826 + }
6827 + pgcount = err;
6828 +
6829 +#ifdef DEBUG_SPIDEV
6830 + printk("spidev_rd_rw: %i %i\n", count, pgcount);
6831 +#endif
6832 +
6833 + /* Set default return value = transfer length */
6834 + res = count;
6835 +
6836 + /*
6837 + * At this point, the virtual area buf[0] .. buf[count-1] will have
6838 + * corresponding pages mapped in the physical memory and locked until
6839 + * we unmap the kiobuf. The pages cannot be swapped out or moved
6840 + * around.
6841 + */
6842 + ofs = (unsigned long) buf & (PAGE_SIZE -1);
6843 + pagelen = PAGE_SIZE - ofs;
6844 + if (count < pagelen)
6845 + pagelen = count;
6846 +
6847 + for (i = 0; i < pgcount; i++) {
6848 + flush_dcache_page(maplist[i]);
6849 +
6850 + list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs;
6851 + list->txlen[i] = list->rxlen[i] = pagelen;
6852 +
6853 +#ifdef DEBUG_SPIDEV
6854 + printk(" %i: %x (%i)\n", i, list->tx[i], list->txlen[i]);
6855 +#endif
6856 +
6857 + ofs = 0; /* all subsequent transfers start at beginning of a page */
6858 + count = count - pagelen;
6859 + pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE;
6860 + }
6861 + list->nr_transfers = pgcount;
6862 +
6863 + /* Perform transfer on SPI bus */
6864 + spi_access_bus(spi_device);
6865 + spi_transfer(list);
6866 + spi_release_bus(spi_device);
6867 +
6868 + while (pgcount--) {
6869 + page_cache_release (maplist[pgcount]);
6870 + }
6871 + flush_cache_all();
6872 +
6873 + kfree(maplist);
6874 + kfree(list);
6875 +
6876 + return res;
6877 +}
6878 +
6879 +static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
6880 +{
6881 + int spi_device = MINOR(inode->i_rdev);
6882 +
6883 + if (spi_device >= NR_SPI_DEVICES)
6884 + return -ENODEV;
6885 +
6886 + // TODO: This interface can be used to configure the SPI bus.
6887 + // Configurable options could include: Speed, Clock Polarity, Clock Phase
6888 +
6889 + switch(cmd) {
6890 + default:
6891 + return -ENOIOCTLCMD;
6892 + }
6893 +}
6894 +
6895 +/*
6896 + * Open the SPI device
6897 + */
6898 +static int spidev_open(struct inode *inode, struct file *file)
6899 +{
6900 + unsigned int spi_device = MINOR(inode->i_rdev);
6901 +
6902 + if (spi_device >= NR_SPI_DEVICES)
6903 + return -ENODEV;
6904 +
6905 + /*
6906 + * 'private_data' is actually a pointer, but we overload it with the
6907 + * value we want to store.
6908 + */
6909 + file->private_data = (void *)spi_device;
6910 +
6911 + return 0;
6912 +}
6913 +
6914 +/*
6915 + * Close the SPI device
6916 + */
6917 +static int spidev_close(struct inode *inode, struct file *file)
6918 +{
6919 + return 0;
6920 +}
6921 +
6922 +/* ......................................................................... */
6923 +
6924 +static struct file_operations spidev_fops = {
6925 + .owner = THIS_MODULE,
6926 + .llseek = no_llseek,
6927 + .read = spidev_rd_wr,
6928 + .write = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr,
6929 + .ioctl = spidev_ioctl,
6930 + .open = spidev_open,
6931 + .release = spidev_close,
6932 +};
6933 +
6934 +/*
6935 + * Install the SPI /dev interface driver
6936 + */
6937 +static int __init at91_spidev_init(void)
6938 +{
6939 +#ifdef CONFIG_DEVFS_FS
6940 + int i;
6941 +#endif
6942 +
6943 + if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) {
6944 + printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR);
6945 + return -EIO;
6946 + }
6947 +
6948 +#ifdef CONFIG_DEVFS_FS
6949 + devfs_mk_dir("spi");
6950 + for (i = 0; i < NR_SPI_DEVICES; i++) {
6951 + devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i);
6952 + }
6953 +#endif
6954 + printk(KERN_INFO "AT91 SPI driver loaded\n");
6955 +
6956 + return 0;
6957 +}
6958 +
6959 +/*
6960 + * Remove the SPI /dev interface driver
6961 + */
6962 +static void __exit at91_spidev_exit(void)
6963 +{
6964 +#ifdef CONFIG_DEVFS_FS
6965 + int i;
6966 + for (i = 0; i < NR_SPI_DEVICES; i++) {
6967 + devfs_remove("spi/%d", i);
6968 + }
6969 +
6970 + devfs_remove("spi");
6971 +#endif
6972 +
6973 + unregister_chrdev(SPI_MAJOR, "spi");
6974 +}
6975 +
6976 +module_init(at91_spidev_init);
6977 +module_exit(at91_spidev_exit);
6978 +
6979 +MODULE_LICENSE("GPL")
6980 +MODULE_AUTHOR("Andrew Victor")
6981 +MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200")
6982 --- a/drivers/i2c/busses/Kconfig
6983 +++ b/drivers/i2c/busses/Kconfig
6984 @@ -88,6 +88,14 @@
6985 to support combined I2C messages. Use the i2c-gpio driver
6986 unless your system can cope with those limitations.
6987
6988 +config I2C_AT91_CLOCKRATE
6989 + prompt "Atmel AT91 I2C/TWI clock-rate"
6990 + depends on I2C_AT91
6991 + int
6992 + default 100000
6993 + help
6994 + Set the AT91 I2C/TWI clock-rate.
6995 +
6996 config I2C_AU1550
6997 tristate "Au1550/Au1200 SMBus interface"
6998 depends on SOC_AU1550 || SOC_AU1200
6999 @@ -626,6 +634,14 @@
7000 This driver can also be built as a module. If so, the module
7001 will be called i2c-voodoo3.
7002
7003 +config I2C_PCA
7004 + tristate "PCA9564"
7005 + depends on I2C
7006 + select I2C_ALGOPCA
7007 + help
7008 + This driver support the Philips PCA 9564 Parallel bus to I2C
7009 + bus controller.
7010 +
7011 config I2C_PCA_ISA
7012 tristate "PCA9564 on an ISA bus"
7013 depends on ISA
7014 --- a/drivers/i2c/busses/Makefile
7015 +++ b/drivers/i2c/busses/Makefile
7016 @@ -29,6 +29,7 @@
7017 obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
7018 obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
7019 obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
7020 +obj-$(CONFIG_I2C_PCA) += i2c-pca.o
7021 obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
7022 obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
7023 obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
7024 --- a/drivers/i2c/busses/i2c-at91.c
7025 +++ b/drivers/i2c/busses/i2c-at91.c
7026 @@ -31,8 +31,11 @@
7027 #include <asm/arch/board.h>
7028 #include <asm/arch/cpu.h>
7029
7030 -#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */
7031
7032 +/* Clockrate is configurable - max 400 Kbits/sec */
7033 +static unsigned int clockrate = CONFIG_I2C_AT91_CLOCKRATE;
7034 +module_param(clockrate, uint, 0);
7035 +MODULE_PARM_DESC(clockrate, "The TWI clockrate");
7036
7037 static struct clk *twi_clk;
7038 static void __iomem *twi_base;
7039 @@ -53,7 +56,7 @@
7040 at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */
7041
7042 /* Calcuate clock dividers */
7043 - cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3;
7044 + cdiv = (clk_get_rate(twi_clk) / (2 * clockrate)) - 3;
7045 cdiv = cdiv + 1; /* round up */
7046 ckdiv = 0;
7047 while (cdiv > 255) {
7048 @@ -61,11 +64,12 @@
7049 cdiv = cdiv >> 1;
7050 }
7051
7052 - if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */
7053 - if (ckdiv > 5) {
7054 - printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n");
7055 - ckdiv = 5;
7056 - }
7057 + if (cpu_is_at91rm9200() && (ckdiv > 5)) { /* AT91RM9200 Errata #22 */
7058 + printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n");
7059 + ckdiv = 5;
7060 + } else if (ckdiv > 7) {
7061 + printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n");
7062 + ckdiv = 7;
7063 }
7064
7065 at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv);
7066 --- /dev/null
7067 +++ b/drivers/i2c/busses/i2c-pca.c
7068 @@ -0,0 +1,213 @@
7069 +/*
7070 + * Platform driver for PCA9564 I2C bus controller.
7071 + *
7072 + * (C) 2006 Andrew Victor
7073 + *
7074 + * Based on i2c-pca-isa.c driver for PCA9564 on ISA boards
7075 + * Copyright (C) 2004 Arcom Control Systems
7076 + *
7077 + * This program is free software; you can redistribute it and/or modify
7078 + * it under the terms of the GNU General Public License as published by
7079 + * the Free Software Foundation; either version 2 of the License, or
7080 + * (at your option) any later version.
7081 + *
7082 + * This program is distributed in the hope that it will be useful,
7083 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7084 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7085 + * GNU General Public License for more details.
7086 + *
7087 + * You should have received a copy of the GNU General Public License
7088 + * along with this program; if not, write to the Free Software
7089 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
7090 + */
7091 +
7092 +#include <linux/kernel.h>
7093 +#include <linux/module.h>
7094 +#include <linux/moduleparam.h>
7095 +#include <linux/delay.h>
7096 +#include <linux/init.h>
7097 +#include <linux/interrupt.h>
7098 +#include <linux/wait.h>
7099 +#include <linux/platform_device.h>
7100 +
7101 +#include <linux/i2c.h>
7102 +#include <linux/i2c-algo-pca.h>
7103 +
7104 +#include <asm/io.h>
7105 +
7106 +#include "../algos/i2c-algo-pca.h"
7107 +
7108 +#define PCA_OWN_ADDRESS 0x55 /* our address for slave mode */
7109 +#define PCA_CLOCK I2C_PCA_CON_59kHz
7110 +
7111 +//#define REG_SHIFT 2
7112 +#define REG_SHIFT 0
7113 +
7114 +//#define DEBUG_IO
7115 +
7116 +#define PCA_IO_SIZE 4
7117 +
7118 +static void __iomem *base_addr;
7119 +static int irq;
7120 +static wait_queue_head_t pca_wait;
7121 +
7122 +static int pca_getown(struct i2c_algo_pca_data *adap)
7123 +{
7124 + return PCA_OWN_ADDRESS;
7125 +}
7126 +
7127 +static int pca_getclock(struct i2c_algo_pca_data *adap)
7128 +{
7129 + return PCA_CLOCK;
7130 +}
7131 +
7132 +static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
7133 +{
7134 +#ifdef DEBUG_IO
7135 + static char *names[] = { "T/O", "DAT", "ADR", "CON" };
7136 + printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val);
7137 +#endif
7138 + udelay(1);
7139 + outb(val, base_addr + (reg << REG_SHIFT));
7140 +}
7141 +
7142 +static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg)
7143 +{
7144 + int res;
7145 +
7146 + udelay(1);
7147 + res = inb(base_addr + (reg << REG_SHIFT));
7148 +#ifdef DEBUG_IO
7149 + {
7150 + static char *names[] = { "STA", "DAT", "ADR", "CON" };
7151 + printk("*** read %s => %#04x\n", names[reg], res);
7152 + }
7153 +#endif
7154 + return res;
7155 +}
7156 +
7157 +static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap)
7158 +{
7159 + int ret = 0;
7160 +
7161 + if (irq > -1) {
7162 + ret = wait_event_interruptible(pca_wait,
7163 + pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
7164 + } else {
7165 + while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
7166 + udelay(100);
7167 + }
7168 + return ret;
7169 +}
7170 +
7171 +static irqreturn_t pca_handler(int this_irq, void *dev_id)
7172 +{
7173 + wake_up_interruptible(&pca_wait);
7174 + return IRQ_HANDLED;
7175 +}
7176 +
7177 +static struct i2c_algo_pca_data pca_i2c_data = {
7178 + .get_own = pca_getown,
7179 + .get_clock = pca_getclock,
7180 + .write_byte = pca_writebyte,
7181 + .read_byte = pca_readbyte,
7182 + .wait_for_interrupt = pca_waitforinterrupt,
7183 +};
7184 +
7185 +static struct i2c_adapter pca_i2c_ops = {
7186 + .owner = THIS_MODULE,
7187 + .id = I2C_HW_A_PLAT,
7188 + .algo_data = &pca_i2c_data,
7189 + .name = "PCA9564",
7190 + .class = I2C_CLASS_HWMON,
7191 +};
7192 +
7193 +static int __devinit pca_i2c_probe(struct platform_device *pdev)
7194 +{
7195 + struct resource *res;
7196 +
7197 + init_waitqueue_head(&pca_wait);
7198 +
7199 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7200 + if (!res)
7201 + return -ENODEV;
7202 +
7203 + if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564"))
7204 + return -ENXIO;
7205 +
7206 + base_addr = ioremap(res->start, PCA_IO_SIZE);
7207 + if (base_addr == NULL)
7208 + goto out_region;
7209 +
7210 + irq = platform_get_irq(pdev, 0);
7211 + if (irq > -1) {
7212 + if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) {
7213 + printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq);
7214 + goto out_remap;
7215 + }
7216 + }
7217 +
7218 + /* set up the driverfs linkage to our parent device */
7219 + pca_i2c_ops.dev.parent = &pdev->dev;
7220 +
7221 + if (i2c_pca_add_bus(&pca_i2c_ops) < 0) {
7222 + printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n");
7223 + goto out_irq;
7224 + }
7225 +
7226 + return 0;
7227 +
7228 + out_irq:
7229 + if (irq > -1)
7230 + free_irq(irq, &pca_i2c_ops);
7231 +
7232 + out_remap:
7233 + iounmap(base_addr);
7234 +
7235 + out_region:
7236 + release_mem_region(res->start, PCA_IO_SIZE);
7237 + return -ENODEV;
7238 +}
7239 +
7240 +static int __devexit pca_i2c_remove(struct platform_device *pdev)
7241 +{
7242 + struct resource *res;
7243 +
7244 + i2c_del_adapter(&pca_i2c_ops);
7245 +
7246 + if (irq > 0)
7247 + free_irq(irq, NULL);
7248 +
7249 + iounmap(base_addr);
7250 +
7251 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7252 + release_mem_region(res->start, PCA_IO_SIZE);
7253 +
7254 + return 0;
7255 +}
7256 +
7257 +static struct platform_driver pca_i2c_driver = {
7258 + .probe = pca_i2c_probe,
7259 + .remove = __devexit_p(pca_i2c_remove),
7260 + .driver = {
7261 + .name = "pca9564",
7262 + .owner = THIS_MODULE,
7263 + },
7264 +};
7265 +
7266 +static int __init pca_i2c_init(void)
7267 +{
7268 + return platform_driver_register(&pca_i2c_driver);
7269 +}
7270 +
7271 +static void __exit pca_i2c_exit(void)
7272 +{
7273 + platform_driver_unregister(&pca_i2c_driver);
7274 +}
7275 +
7276 +module_init(pca_i2c_init);
7277 +module_exit(pca_i2c_exit);
7278 +
7279 +MODULE_AUTHOR("Andrew Victor");
7280 +MODULE_DESCRIPTION("PCA9564 platform driver");
7281 +MODULE_LICENSE("GPL");
7282 --- a/drivers/mmc/host/at91_mci.c
7283 +++ b/drivers/mmc/host/at91_mci.c
7284 @@ -659,13 +659,14 @@
7285 /* maybe switch power to the card */
7286 if (host->board->vcc_pin) {
7287 switch (ios->power_mode) {
7288 - case MMC_POWER_OFF:
7289 - gpio_set_value(host->board->vcc_pin, 0);
7290 - break;
7291 - case MMC_POWER_UP:
7292 - case MMC_POWER_ON:
7293 - gpio_set_value(host->board->vcc_pin, 1);
7294 - break;
7295 + case MMC_POWER_OFF:
7296 + gpio_set_value(host->board->vcc_pin, 0);
7297 + break;
7298 + case MMC_POWER_UP:
7299 + gpio_set_value(host->board->vcc_pin, 1);
7300 + break;
7301 + default:
7302 + break;
7303 }
7304 }
7305 }
7306 --- a/drivers/mtd/devices/Kconfig
7307 +++ b/drivers/mtd/devices/Kconfig
7308 @@ -270,5 +270,17 @@
7309 LinuxBIOS or if you need to recover a DiskOnChip Millennium on which
7310 you have managed to wipe the first block.
7311
7312 -endmenu
7313 +config MTD_AT91_DATAFLASH
7314 + tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)"
7315 + depends on MTD && ARCH_AT91RM9200 && AT91_SPI
7316 + help
7317 + This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200.
7318 + If you have such a board, say 'Y'.
7319 +
7320 +config DATAFLASH_ALWAYS_ADD_DEVICE
7321 + bool "Register whole DataFlash device"
7322 + depends on MTD_AT91_DATAFLASH
7323 + help
7324 + Always add the whole DataFlash device when using MTD partitions.
7325
7326 +endmenu
7327 --- a/drivers/mtd/devices/Makefile
7328 +++ b/drivers/mtd/devices/Makefile
7329 @@ -17,3 +17,4 @@
7330 obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
7331 obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
7332 obj-$(CONFIG_MTD_M25P80) += m25p80.o
7333 +obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o
7334 --- /dev/null
7335 +++ b/drivers/mtd/devices/at91_dataflash.c
7336 @@ -0,0 +1,673 @@
7337 +/*
7338 + * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder)
7339 + *
7340 + * Copyright (C) SAN People (Pty) Ltd
7341 + *
7342 + * This program is free software; you can redistribute it and/or
7343 + * modify it under the terms of the GNU General Public License
7344 + * as published by the Free Software Foundation; either version
7345 + * 2 of the License, or (at your option) any later version.
7346 +*/
7347 +
7348 +#include <linux/module.h>
7349 +#include <linux/init.h>
7350 +#include <linux/slab.h>
7351 +#include <linux/pci.h>
7352 +#include <linux/mtd/mtd.h>
7353 +#include <linux/mtd/partitions.h>
7354 +
7355 +#include <asm/mach-types.h>
7356 +
7357 +#include <asm/arch/spi.h>
7358 +
7359 +
7360 +#undef DEBUG_DATAFLASH
7361 +
7362 +#define DATAFLASH_MAX_DEVICES 4 /* max number of dataflash devices */
7363 +
7364 +#define OP_READ_CONTINUOUS 0xE8
7365 +#define OP_READ_PAGE 0xD2
7366 +#define OP_READ_BUFFER1 0xD4
7367 +#define OP_READ_BUFFER2 0xD6
7368 +#define OP_READ_STATUS 0xD7
7369 +
7370 +#define OP_ERASE_PAGE 0x81
7371 +#define OP_ERASE_BLOCK 0x50
7372 +
7373 +#define OP_TRANSFER_BUF1 0x53
7374 +#define OP_TRANSFER_BUF2 0x55
7375 +#define OP_COMPARE_BUF1 0x60
7376 +#define OP_COMPARE_BUF2 0x61
7377 +
7378 +#define OP_PROGRAM_VIA_BUF1 0x82
7379 +#define OP_PROGRAM_VIA_BUF2 0x85
7380 +
7381 +struct dataflash_local
7382 +{
7383 + int spi; /* SPI chip-select number */
7384 +
7385 + unsigned int page_size; /* number of bytes per page */
7386 + unsigned short page_offset; /* page offset in flash address */
7387 +};
7388 +
7389 +
7390 +/* Detected DataFlash devices */
7391 +static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES];
7392 +static int nr_devices = 0;
7393 +
7394 +/* ......................................................................... */
7395 +
7396 +#ifdef CONFIG_MTD_PARTITIONS
7397 +
7398 +static struct mtd_partition static_partitions_2M[] =
7399 +{
7400 + {
7401 + .name = "bootloader",
7402 + .offset = 0,
7403 + .size = 1 * 32 * 8 * 528, /* 1st sector = 32 blocks * 8 pages * 528 bytes */
7404 + .mask_flags = MTD_WRITEABLE, /* read-only */
7405 + },
7406 + {
7407 + .name = "kernel",
7408 + .offset = MTDPART_OFS_NXTBLK,
7409 + .size = 6 * 32 * 8 * 528, /* 6 sectors */
7410 + },
7411 + {
7412 + .name = "filesystem",
7413 + .offset = MTDPART_OFS_NXTBLK,
7414 + .size = MTDPART_SIZ_FULL, /* rest = 9 sectors */
7415 + }
7416 +};
7417 +
7418 +static struct mtd_partition static_partitions_4M[] =
7419 +{
7420 + {
7421 + .name = "bootloader",
7422 + .offset = 0,
7423 + .size = 1 * 64 * 8 * 528, /* 1st sector = 64 blocks * 8 pages * 528 bytes */
7424 + .mask_flags = MTD_WRITEABLE, /* read-only */
7425 + },
7426 + {
7427 + .name = "kernel",
7428 + .offset = MTDPART_OFS_NXTBLK,
7429 + .size = 4 * 64 * 8 * 528, /* 4 sectors */
7430 + },
7431 + {
7432 + .name = "filesystem",
7433 + .offset = MTDPART_OFS_NXTBLK,
7434 + .size = MTDPART_SIZ_FULL, /* rest = 11 sectors */
7435 + }
7436 +};
7437 +
7438 +#if defined(CONFIG_MACH_KAFA)
7439 +static struct mtd_partition static_partitions_8M[] =
7440 +{
7441 + {
7442 + name: "romboot",
7443 + offset: 0,
7444 + size: 16 * 1056, /* 160 Kb */
7445 + mask_flags: MTD_WRITEABLE, /* read-only */
7446 + },
7447 + {
7448 + name: "uboot",
7449 + offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
7450 + size: 128 * 1056, /* 1 MB */
7451 + },
7452 + {
7453 + name: "kernel",
7454 + offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
7455 + size: 1024 * 1056, /* 1 MB */
7456 + },
7457 + {
7458 + name: "filesystem",
7459 + offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
7460 + size: MTDPART_SIZ_FULL,
7461 + }
7462 +};
7463 +
7464 +#elif defined(CONFIG_MACH_MULTMDP)
7465 +
7466 +static struct mtd_partition static_partitions_8M[] =
7467 +{
7468 + {
7469 + .name = "bootloader",
7470 + .offset = 0,
7471 + .size = 12 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
7472 + .mask_flags = MTD_WRITEABLE, /* read-only */
7473 + },
7474 + {
7475 + .name = "configuration",
7476 + .offset = MTDPART_OFS_NXTBLK,
7477 + .size = 20 * 1056,
7478 + },
7479 + {
7480 + .name = "kernel",
7481 + .offset = MTDPART_OFS_NXTBLK,
7482 + .size = 1520 * 1056,
7483 + },
7484 + {
7485 + .name = "filesystem",
7486 + .offset = MTDPART_OFS_NXTBLK,
7487 + .size = MTDPART_SIZ_FULL,
7488 + }
7489 +};
7490 +
7491 +#else
7492 +
7493 +static struct mtd_partition static_partitions_8M[] =
7494 +{
7495 + {
7496 + .name = "bootloader",
7497 + .offset = 0,
7498 + .size = 1 * 32 * 8 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
7499 + .mask_flags = MTD_WRITEABLE, /* read-only */
7500 + },
7501 + {
7502 + .name = "kernel",
7503 + .offset = MTDPART_OFS_NXTBLK,
7504 + .size = 5 * 32 * 8 * 1056, /* 5 sectors */
7505 + },
7506 + {
7507 + .name = "filesystem",
7508 + .offset = MTDPART_OFS_NXTBLK,
7509 + .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */
7510 + }
7511 +};
7512 +#endif
7513 +
7514 +static const char *part_probes[] = { "cmdlinepart", NULL, };
7515 +
7516 +#endif
7517 +
7518 +/* ......................................................................... */
7519 +
7520 +/* Allocate a single SPI transfer descriptor. We're assuming that if multiple
7521 + SPI transfers occur at the same time, spi_access_bus() will serialize them.
7522 + If this is not valid, then either (i) each dataflash 'priv' structure
7523 + needs it's own transfer descriptor, (ii) we lock this one, or (iii) use
7524 + another mechanism. */
7525 +static struct spi_transfer_list* spi_transfer_desc;
7526 +
7527 +/*
7528 + * Perform a SPI transfer to access the DataFlash device.
7529 + */
7530 +static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len,
7531 + char* txnext, int txnext_len, char* rxnext, int rxnext_len)
7532 +{
7533 + struct spi_transfer_list* list = spi_transfer_desc;
7534 +
7535 + list->tx[0] = tx; list->txlen[0] = tx_len;
7536 + list->rx[0] = rx; list->rxlen[0] = rx_len;
7537 +
7538 + list->tx[1] = txnext; list->txlen[1] = txnext_len;
7539 + list->rx[1] = rxnext; list->rxlen[1] = rxnext_len;
7540 +
7541 + list->nr_transfers = nr;
7542 +
7543 + return spi_transfer(list);
7544 +}
7545 +
7546 +/* ......................................................................... */
7547 +
7548 +/*
7549 + * Poll the DataFlash device until it is READY.
7550 + */
7551 +static void at91_dataflash_waitready(void)
7552 +{
7553 + char* command = kmalloc(2, GFP_KERNEL);
7554 +
7555 + if (!command)
7556 + return;
7557 +
7558 + do {
7559 + command[0] = OP_READ_STATUS;
7560 + command[1] = 0;
7561 +
7562 + do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
7563 + } while ((command[1] & 0x80) == 0);
7564 +
7565 + kfree(command);
7566 +}
7567 +
7568 +/*
7569 + * Return the status of the DataFlash device.
7570 + */
7571 +static unsigned short at91_dataflash_status(void)
7572 +{
7573 + unsigned short status;
7574 + char* command = kmalloc(2, GFP_KERNEL);
7575 +
7576 + if (!command)
7577 + return 0;
7578 +
7579 + command[0] = OP_READ_STATUS;
7580 + command[1] = 0;
7581 +
7582 + do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
7583 + status = command[1];
7584 +
7585 + kfree(command);
7586 + return status;
7587 +}
7588 +
7589 +/* ......................................................................... */
7590 +
7591 +/*
7592 + * Erase blocks of flash.
7593 + */
7594 +static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
7595 +{
7596 + struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
7597 + unsigned int pageaddr;
7598 + char* command;
7599 +
7600 +#ifdef DEBUG_DATAFLASH
7601 + printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len);
7602 +#endif
7603 +
7604 + /* Sanity checks */
7605 + if (instr->addr + instr->len > mtd->size)
7606 + return -EINVAL;
7607 + if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0))
7608 + return -EINVAL;
7609 + if ((instr->addr % priv->page_size) != 0)
7610 + return -EINVAL;
7611 +
7612 + command = kmalloc(4, GFP_KERNEL);
7613 + if (!command)
7614 + return -ENOMEM;
7615 +
7616 + while (instr->len > 0) {
7617 + /* Calculate flash page address */
7618 + pageaddr = (instr->addr / priv->page_size) << priv->page_offset;
7619 +
7620 + command[0] = OP_ERASE_PAGE;
7621 + command[1] = (pageaddr & 0x00FF0000) >> 16;
7622 + command[2] = (pageaddr & 0x0000FF00) >> 8;
7623 + command[3] = 0;
7624 +#ifdef DEBUG_DATAFLASH
7625 + printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr);
7626 +#endif
7627 +
7628 + /* Send command to SPI device */
7629 + spi_access_bus(priv->spi);
7630 + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
7631 +
7632 + at91_dataflash_waitready(); /* poll status until ready */
7633 + spi_release_bus(priv->spi);
7634 +
7635 + instr->addr += priv->page_size; /* next page */
7636 + instr->len -= priv->page_size;
7637 + }
7638 +
7639 + kfree(command);
7640 +
7641 + /* Inform MTD subsystem that erase is complete */
7642 + instr->state = MTD_ERASE_DONE;
7643 + if (instr->callback)
7644 + instr->callback(instr);
7645 +
7646 + return 0;
7647 +}
7648 +
7649 +/*
7650 + * Read from the DataFlash device.
7651 + * from : Start offset in flash device
7652 + * len : Amount to read
7653 + * retlen : About of data actually read
7654 + * buf : Buffer containing the data
7655 + */
7656 +static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
7657 +{
7658 + struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
7659 + unsigned int addr;
7660 + char* command;
7661 +
7662 +#ifdef DEBUG_DATAFLASH
7663 + printk("dataflash_read: %lli .. %lli\n", from, from+len);
7664 +#endif
7665 +
7666 + *retlen = 0;
7667 +
7668 + /* Sanity checks */
7669 + if (!len)
7670 + return 0;
7671 + if (from + len > mtd->size)
7672 + return -EINVAL;
7673 +
7674 + /* Calculate flash page/byte address */
7675 + addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size);
7676 +
7677 + command = kmalloc(8, GFP_KERNEL);
7678 + if (!command)
7679 + return -ENOMEM;
7680 +
7681 + command[0] = OP_READ_CONTINUOUS;
7682 + command[1] = (addr & 0x00FF0000) >> 16;
7683 + command[2] = (addr & 0x0000FF00) >> 8;
7684 + command[3] = (addr & 0x000000FF);
7685 +#ifdef DEBUG_DATAFLASH
7686 + printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
7687 +#endif
7688 +
7689 + /* Send command to SPI device */
7690 + spi_access_bus(priv->spi);
7691 + do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len);
7692 + spi_release_bus(priv->spi);
7693 +
7694 + *retlen = len;
7695 + kfree(command);
7696 + return 0;
7697 +}
7698 +
7699 +/*
7700 + * Write to the DataFlash device.
7701 + * to : Start offset in flash device
7702 + * len : Amount to write
7703 + * retlen : Amount of data actually written
7704 + * buf : Buffer containing the data
7705 + */
7706 +static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
7707 +{
7708 + struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
7709 + unsigned int pageaddr, addr, offset, writelen;
7710 + size_t remaining;
7711 + u_char *writebuf;
7712 + unsigned short status;
7713 + int res = 0;
7714 + char* command;
7715 + char* tmpbuf = NULL;
7716 +
7717 +#ifdef DEBUG_DATAFLASH
7718 + printk("dataflash_write: %lli .. %lli\n", to, to+len);
7719 +#endif
7720 +
7721 + *retlen = 0;
7722 +
7723 + /* Sanity checks */
7724 + if (!len)
7725 + return 0;
7726 + if (to + len > mtd->size)
7727 + return -EINVAL;
7728 +
7729 + command = kmalloc(4, GFP_KERNEL);
7730 + if (!command)
7731 + return -ENOMEM;
7732 +
7733 + pageaddr = ((unsigned)to / priv->page_size);
7734 + offset = ((unsigned)to % priv->page_size);
7735 + if (offset + len > priv->page_size)
7736 + writelen = priv->page_size - offset;
7737 + else
7738 + writelen = len;
7739 + writebuf = (u_char *)buf;
7740 + remaining = len;
7741 +
7742 + /* Allocate temporary buffer */
7743 + tmpbuf = kmalloc(priv->page_size, GFP_KERNEL);
7744 + if (!tmpbuf) {
7745 + kfree(command);
7746 + return -ENOMEM;
7747 + }
7748 +
7749 + /* Gain access to the SPI bus */
7750 + spi_access_bus(priv->spi);
7751 +
7752 + while (remaining > 0) {
7753 +#ifdef DEBUG_DATAFLASH
7754 + printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen);
7755 +#endif
7756 +
7757 + /* (1) Transfer to Buffer1 */
7758 + if (writelen != priv->page_size) {
7759 + addr = pageaddr << priv->page_offset;
7760 + command[0] = OP_TRANSFER_BUF1;
7761 + command[1] = (addr & 0x00FF0000) >> 16;
7762 + command[2] = (addr & 0x0000FF00) >> 8;
7763 + command[3] = 0;
7764 +#ifdef DEBUG_DATAFLASH
7765 + printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
7766 +#endif
7767 + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
7768 + at91_dataflash_waitready();
7769 + }
7770 +
7771 + /* (2) Program via Buffer1 */
7772 + addr = (pageaddr << priv->page_offset) + offset;
7773 + command[0] = OP_PROGRAM_VIA_BUF1;
7774 + command[1] = (addr & 0x00FF0000) >> 16;
7775 + command[2] = (addr & 0x0000FF00) >> 8;
7776 + command[3] = (addr & 0x000000FF);
7777 +#ifdef DEBUG_DATAFLASH
7778 + printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
7779 +#endif
7780 + do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen);
7781 + at91_dataflash_waitready();
7782 +
7783 + /* (3) Compare to Buffer1 */
7784 + addr = pageaddr << priv->page_offset;
7785 + command[0] = OP_COMPARE_BUF1;
7786 + command[1] = (addr & 0x00FF0000) >> 16;
7787 + command[2] = (addr & 0x0000FF00) >> 8;
7788 + command[3] = 0;
7789 +#ifdef DEBUG_DATAFLASH
7790 + printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
7791 +#endif
7792 + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
7793 + at91_dataflash_waitready();
7794 +
7795 + /* Get result of the compare operation */
7796 + status = at91_dataflash_status();
7797 + if (status & 0x40) {
7798 + printk("at91_dataflash: Write error on page %i\n", pageaddr);
7799 + remaining = 0;
7800 + writelen = 0;
7801 + res = -EIO;
7802 + }
7803 +
7804 + remaining = remaining - writelen;
7805 + pageaddr++;
7806 + offset = 0;
7807 + writebuf += writelen;
7808 + *retlen += writelen;
7809 +
7810 + if (remaining > priv->page_size)
7811 + writelen = priv->page_size;
7812 + else
7813 + writelen = remaining;
7814 + }
7815 +
7816 + /* Release SPI bus */
7817 + spi_release_bus(priv->spi);
7818 +
7819 + kfree(tmpbuf);
7820 + kfree(command);
7821 + return res;
7822 +}
7823 +
7824 +/* ......................................................................... */
7825 +
7826 +/*
7827 + * Initialize and register DataFlash device with MTD subsystem.
7828 + */
7829 +static int __init add_dataflash(int channel, char *name, int IDsize,
7830 + int nr_pages, int pagesize, int pageoffset)
7831 +{
7832 + struct mtd_info *device;
7833 + struct dataflash_local *priv;
7834 +#ifdef CONFIG_MTD_PARTITIONS
7835 + struct mtd_partition *mtd_parts = 0;
7836 + int mtd_parts_nr = 0;
7837 +#endif
7838 +
7839 + if (nr_devices >= DATAFLASH_MAX_DEVICES) {
7840 + printk(KERN_ERR "at91_dataflash: Too many devices detected\n");
7841 + return 0;
7842 + }
7843 +
7844 + device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL);
7845 + if (!device)
7846 + return -ENOMEM;
7847 + memset(device, 0, sizeof(struct mtd_info));
7848 +
7849 + device->name = (char *)&device[1];
7850 + sprintf(device->name, "%s.spi%d", name, channel);
7851 + device->size = nr_pages * pagesize;
7852 + device->erasesize = pagesize;
7853 + device->writesize = pagesize;
7854 + device->owner = THIS_MODULE;
7855 + device->type = MTD_DATAFLASH;
7856 + device->flags = MTD_WRITEABLE;
7857 + device->erase = at91_dataflash_erase;
7858 + device->read = at91_dataflash_read;
7859 + device->write = at91_dataflash_write;
7860 +
7861 + priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL);
7862 + if (!priv) {
7863 + kfree(device);
7864 + return -ENOMEM;
7865 + }
7866 + memset(priv, 0, sizeof(struct dataflash_local));
7867 +
7868 + priv->spi = channel;
7869 + priv->page_size = pagesize;
7870 + priv->page_offset = pageoffset;
7871 + device->priv = priv;
7872 +
7873 + mtd_devices[nr_devices] = device;
7874 + nr_devices++;
7875 + printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size);
7876 +
7877 +#ifdef CONFIG_MTD_PARTITIONS
7878 +#ifdef CONFIG_MTD_CMDLINE_PARTS
7879 + mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0);
7880 +#endif
7881 + if (mtd_parts_nr <= 0) {
7882 + switch (IDsize) {
7883 + case SZ_2M:
7884 + mtd_parts = static_partitions_2M;
7885 + mtd_parts_nr = ARRAY_SIZE(static_partitions_2M);
7886 + break;
7887 + case SZ_4M:
7888 + mtd_parts = static_partitions_4M;
7889 + mtd_parts_nr = ARRAY_SIZE(static_partitions_4M);
7890 + break;
7891 + case SZ_8M:
7892 + mtd_parts = static_partitions_8M;
7893 + mtd_parts_nr = ARRAY_SIZE(static_partitions_8M);
7894 + break;
7895 + }
7896 + }
7897 +
7898 + if (mtd_parts_nr > 0) {
7899 +#ifdef CONFIG_DATAFLASH_ALWAYS_ADD_DEVICE
7900 + add_mtd_device(device);
7901 +#endif
7902 + return add_mtd_partitions(device, mtd_parts, mtd_parts_nr);
7903 + }
7904 +#endif
7905 + return add_mtd_device(device); /* add whole device */
7906 +}
7907 +
7908 +/*
7909 + * Detect and initialize DataFlash device connected to specified SPI channel.
7910 + *
7911 + * Device Density ID code Nr Pages Page Size Page offset
7912 + * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
7913 + * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9
7914 + * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
7915 + * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
7916 + * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
7917 + * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
7918 + * AT45DB0642 64Mbit (8M) xx1111xx (0x3c) 8192 1056 11
7919 + * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
7920 + */
7921 +static int __init at91_dataflash_detect(int channel)
7922 +{
7923 + int res = 0;
7924 + unsigned short status;
7925 +
7926 + spi_access_bus(channel);
7927 + status = at91_dataflash_status();
7928 + spi_release_bus(channel);
7929 + if (status != 0xff) { /* no dataflash device there */
7930 + switch (status & 0x3c) {
7931 + case 0x0c: /* 0 0 1 1 */
7932 + res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9);
7933 + break;
7934 + case 0x14: /* 0 1 0 1 */
7935 + res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9);
7936 + break;
7937 + case 0x1c: /* 0 1 1 1 */
7938 + res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9);
7939 + break;
7940 + case 0x24: /* 1 0 0 1 */
7941 + res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9);
7942 + break;
7943 + case 0x2c: /* 1 0 1 1 */
7944 + res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10);
7945 + break;
7946 + case 0x34: /* 1 1 0 1 */
7947 + res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10);
7948 + break;
7949 + case 0x3c: /* 1 1 1 1 */
7950 + res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11);
7951 + break;
7952 +// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands.
7953 +// case 0x10: /* 0 1 0 0 */
7954 +// res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11);
7955 +// break;
7956 + default:
7957 + printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c);
7958 + }
7959 + }
7960 +
7961 + return res;
7962 +}
7963 +
7964 +static int __init at91_dataflash_init(void)
7965 +{
7966 + spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
7967 + if (!spi_transfer_desc)
7968 + return -ENOMEM;
7969 +
7970 + /* DataFlash (SPI chip select 0) */
7971 + at91_dataflash_detect(0);
7972 +
7973 + if (machine_is_sweda_tms())
7974 + at91_dataflash_detect(1); /* DataFlash device (SPI chip select 1) */
7975 +
7976 +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
7977 + /* DataFlash card (SPI chip select 3) */
7978 + at91_dataflash_detect(3);
7979 +#endif
7980 +
7981 + return 0;
7982 +}
7983 +
7984 +static void __exit at91_dataflash_exit(void)
7985 +{
7986 + int i;
7987 +
7988 + for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) {
7989 + if (mtd_devices[i]) {
7990 +#ifdef CONFIG_MTD_PARTITIONS
7991 + del_mtd_partitions(mtd_devices[i]);
7992 +#else
7993 + del_mtd_device(mtd_devices[i]);
7994 +#endif
7995 + kfree(mtd_devices[i]->priv);
7996 + kfree(mtd_devices[i]);
7997 + }
7998 + }
7999 + nr_devices = 0;
8000 + kfree(spi_transfer_desc);
8001 +}
8002 +
8003 +
8004 +module_init(at91_dataflash_init);
8005 +module_exit(at91_dataflash_exit);
8006 +
8007 +MODULE_LICENSE("GPL");
8008 +MODULE_AUTHOR("Andrew Victor");
8009 +MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200");
8010 --- a/drivers/mtd/nand/Kconfig
8011 +++ b/drivers/mtd/nand/Kconfig
8012 @@ -273,12 +273,53 @@
8013 If you say "m", the module will be called "cs553x_nand.ko".
8014
8015 config MTD_NAND_AT91
8016 - bool "Support for NAND Flash / SmartMedia on AT91"
8017 + tristate "Support for NAND Flash / SmartMedia on AT91"
8018 depends on ARCH_AT91
8019 help
8020 Enables support for NAND Flash / Smart Media Card interface
8021 on Atmel AT91 processors.
8022
8023 +choice
8024 + prompt "ECC management for NAND Flash / SmartMedia on AT91"
8025 + depends on MTD_NAND_AT91
8026 +
8027 +config MTD_NAND_AT91_ECC_SOFT
8028 + bool "Software ECC"
8029 + depends on MTD_NAND_AT91
8030 + help
8031 + Uses software ECC.
8032 +
8033 + NB : hardware and software ECC schemes are incompatible.
8034 + If you switch from one to another, you'll have to erase your
8035 + mtd partition.
8036 +
8037 +config MTD_NAND_AT91_ECC_HW
8038 + bool "Hardware ECC"
8039 + depends on MTD_NAND_AT91 && (ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9)
8040 + help
8041 + Uses hardware ECC provided by the AT91 processor
8042 + instead of software ECC.
8043 + The hardware ECC controller is capable of single bit error
8044 + correction and 2-bit random detection per page.
8045 +
8046 + NB : hardware and software ECC schemes are incompatible.
8047 + If you switch from one to another, you'll have to erase your
8048 + mtd partition.
8049 +
8050 + If unsure, say Y
8051 +
8052 +config MTD_NAND_AT91_ECC_NONE
8053 + bool "No ECC (Testing Only)"
8054 + depends on MTD_NAND_AT91
8055 + help
8056 + No ECC will be used.
8057 + It's not a good idea and it should be reserved for testing
8058 + purpose only.
8059 +
8060 + If unsure, say N
8061 +
8062 +endchoice
8063 +
8064 config MTD_NAND_CM_X270
8065 tristate "Support for NAND Flash on CM-X270 modules"
8066 depends on MTD_NAND && MACH_ARMCORE
8067 --- a/drivers/mtd/nand/at91_nand.c
8068 +++ b/drivers/mtd/nand/at91_nand.c
8069 @@ -9,6 +9,15 @@
8070 * Derived from drivers/mtd/spia.c
8071 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
8072 *
8073 + *
8074 + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
8075 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
8076 + *
8077 + * Derived from Das U-Boot source code
8078 + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
8079 + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8080 + *
8081 + *
8082 * This program is free software; you can redistribute it and/or modify
8083 * it under the terms of the GNU General Public License version 2 as
8084 * published by the Free Software Foundation.
8085 @@ -28,15 +37,75 @@
8086 #include <asm/hardware.h>
8087 #include <asm/arch/board.h>
8088 #include <asm/arch/gpio.h>
8089 +#include <asm/arch/at91_ecc.h>
8090 +
8091 +#ifdef CONFIG_MTD_NAND_AT91_ECC_HW
8092 +#define hard_ecc 1
8093 +#else
8094 +#define hard_ecc 0
8095 +#endif
8096 +
8097 +#ifdef CONFIG_MTD_NAND_AT91_ECC_NONE
8098 +#define no_ecc 1
8099 +#else
8100 +#define no_ecc 0
8101 +#endif
8102 +
8103 +/* Register access macros */
8104 +#define ecc_readl(base, reg) __raw_readl(base + reg)
8105 +#define ecc_writel(base, reg, value) __raw_writel((value), base + reg)
8106 +
8107 +
8108 +/*
8109 + * OOB layout for large page size.
8110 + * bad block info is on bytes 0 and 1
8111 + * the bytes must be consecutives to avoid several NAND_CMD_RNDOUT during read.
8112 + */
8113 +static struct nand_ecclayout at91_oobinfo_large = {
8114 + .eccbytes = 4,
8115 + .eccpos = {60, 61, 62, 63},
8116 + .oobfree = { {2, 58} },
8117 +};
8118 +
8119 +/*
8120 + * OOB layout for small page size
8121 + * bad block info is on bytes 4 and 5
8122 + * the bytes must be consecutives to avoid several NAND_CMD_RNDOUT during read.
8123 + */
8124 +static struct nand_ecclayout at91_oobinfo_small = {
8125 + .eccbytes = 4,
8126 + .eccpos = {0, 1, 2, 3},
8127 + .oobfree = { {6, 10} },
8128 +};
8129
8130 struct at91_nand_host {
8131 struct nand_chip nand_chip;
8132 struct mtd_info mtd;
8133 void __iomem *io_base;
8134 struct at91_nand_data *board;
8135 + struct device *dev;
8136 + void __iomem *ecc;
8137 };
8138
8139 /*
8140 + * Enable NAND chip-select.
8141 + */
8142 +static void at91_nand_enable(struct at91_nand_host *host)
8143 +{
8144 + if (host->board->enable_pin)
8145 + at91_set_gpio_value(host->board->enable_pin, 0);
8146 +}
8147 +
8148 +/*
8149 + * Disable NAND chip-select.
8150 + */
8151 +static void at91_nand_disable(struct at91_nand_host *host)
8152 +{
8153 + if (host->board->enable_pin)
8154 + at91_set_gpio_value(host->board->enable_pin, 1);
8155 +}
8156 +
8157 +/*
8158 * Hardware specific access to control-lines
8159 */
8160 static void at91_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
8161 @@ -44,6 +113,13 @@
8162 struct nand_chip *nand_chip = mtd->priv;
8163 struct at91_nand_host *host = nand_chip->priv;
8164
8165 + if (ctrl & NAND_CTRL_CHANGE) {
8166 + if (ctrl & NAND_NCE)
8167 + at91_nand_enable(host);
8168 + else
8169 + at91_nand_disable(host);
8170 + }
8171 +
8172 if (cmd == NAND_CMD_NONE)
8173 return;
8174
8175 @@ -65,27 +141,249 @@
8176 }
8177
8178 /*
8179 - * Enable NAND.
8180 + * write oob for small pages
8181 */
8182 -static void at91_nand_enable(struct at91_nand_host *host)
8183 +static int at91_nand_write_oob_512(struct mtd_info *mtd,
8184 + struct nand_chip *chip, int page)
8185 {
8186 - if (host->board->enable_pin)
8187 - at91_set_gpio_value(host->board->enable_pin, 0);
8188 + int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
8189 + int eccsize = chip->ecc.size, length = mtd->oobsize;
8190 + int len, pos, status = 0;
8191 + const uint8_t *bufpoi = chip->oob_poi;
8192 +
8193 + pos = eccsize + chunk;
8194 +
8195 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
8196 + len = min_t(int, length, chunk);
8197 + chip->write_buf(mtd, bufpoi, len);
8198 + bufpoi += len;
8199 + length -= len;
8200 + if (length > 0)
8201 + chip->write_buf(mtd, bufpoi, length);
8202 +
8203 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
8204 + status = chip->waitfunc(mtd, chip);
8205 +
8206 + return status & NAND_STATUS_FAIL ? -EIO : 0;
8207 +
8208 }
8209
8210 /*
8211 - * Disable NAND.
8212 + * read oob for small pages
8213 */
8214 -static void at91_nand_disable(struct at91_nand_host *host)
8215 +static int at91_nand_read_oob_512(struct mtd_info *mtd,
8216 + struct nand_chip *chip, int page, int sndcmd)
8217 {
8218 - if (host->board->enable_pin)
8219 - at91_set_gpio_value(host->board->enable_pin, 1);
8220 + if (sndcmd) {
8221 + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
8222 + sndcmd = 0;
8223 + }
8224 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8225 + return sndcmd;
8226 +}
8227 +
8228 +/*
8229 + * Calculate HW ECC
8230 + *
8231 + * mtd: MTD block structure
8232 + * dat: raw data (unused)
8233 + * ecc_code: buffer for ECC
8234 + */
8235 +static int at91_nand_calculate(struct mtd_info *mtd,
8236 + const u_char *dat, unsigned char *ecc_code)
8237 +{
8238 + struct nand_chip *nand_chip = mtd->priv;
8239 + struct at91_nand_host *host = nand_chip->priv;
8240 + uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
8241 + unsigned int ecc_value;
8242 +
8243 + /* get the first 2 ECC bytes */
8244 + ecc_value = ecc_readl(host->ecc, AT91_ECC_PR) & (AT91_ECC_BITADDR | AT91_ECC_WORDADDR);
8245 +
8246 + ecc_code[eccpos[0]] = ecc_value & 0xFF;
8247 + ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;
8248 +
8249 + /* get the last 2 ECC bytes */
8250 + ecc_value = ecc_readl(host->ecc, AT91_ECC_NPR) & AT91_ECC_NPARITY;
8251 +
8252 + ecc_code[eccpos[2]] = ecc_value & 0xFF;
8253 + ecc_code[eccpos[3]] = (ecc_value >> 8) & 0xFF;
8254 +
8255 + return 0;
8256 }
8257
8258 +/*
8259 + * HW ECC read page function
8260 + *
8261 + * mtd: mtd info structure
8262 + * chip: nand chip info structure
8263 + * buf: buffer to store read data
8264 + */
8265 +static int at91_nand_read_page(struct mtd_info *mtd,
8266 + struct nand_chip *chip, uint8_t *buf)
8267 +{
8268 + int eccsize = chip->ecc.size;
8269 + int eccbytes = chip->ecc.bytes;
8270 + uint32_t *eccpos = chip->ecc.layout->eccpos;
8271 + uint8_t *p = buf;
8272 + uint8_t *oob = chip->oob_poi;
8273 + uint8_t *ecc_pos;
8274 + int stat;
8275 +
8276 + /* read the page */
8277 + chip->read_buf(mtd, p, eccsize);
8278 +
8279 + /* move to ECC position if needed */
8280 + if (eccpos[0] != 0) {
8281 + /*
8282 + * This only works on large pages because the ECC controller
8283 + * waits for NAND_CMD_RNDOUTSTART after the NAND_CMD_RNDOUT.
8284 + * Anyway, for small pages, the eccpos[0] == 0
8285 + */
8286 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
8287 + mtd->writesize + eccpos[0], -1);
8288 + }
8289 +
8290 + /* the ECC controller needs to read the ECC just after the data */
8291 + ecc_pos = oob + eccpos[0];
8292 + chip->read_buf(mtd, ecc_pos, eccbytes);
8293 +
8294 + /* check if there's an error */
8295 + stat = chip->ecc.correct(mtd, p, oob, NULL);
8296 +
8297 + if (stat < 0)
8298 + mtd->ecc_stats.failed++;
8299 + else
8300 + mtd->ecc_stats.corrected += stat;
8301 +
8302 + /* get back to oob start (end of page) */
8303 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
8304 +
8305 + /* read the oob */
8306 + chip->read_buf(mtd, oob, mtd->oobsize);
8307 +
8308 + return 0;
8309 +}
8310 +
8311 +/*
8312 + * HW ECC Correction
8313 + *
8314 + * mtd: MTD block structure
8315 + * dat: raw data read from the chip
8316 + * read_ecc: ECC from the chip (unused)
8317 + * isnull: unused
8318 + *
8319 + * Detect and correct a 1 bit error for a page
8320 + */
8321 +static int at91_nand_correct(struct mtd_info *mtd, u_char *dat,
8322 + u_char *read_ecc, u_char *isnull)
8323 +{
8324 + struct nand_chip *nand_chip = mtd->priv;
8325 + struct at91_nand_host *host = nand_chip->priv;
8326 + unsigned int ecc_status;
8327 + unsigned int ecc_word, ecc_bit;
8328 +
8329 + /* get the status from the Status Register */
8330 + ecc_status = ecc_readl(host->ecc, AT91_ECC_SR);
8331 +
8332 + /* if there's no error */
8333 + if (likely(!(ecc_status & AT91_ECC_RECERR)))
8334 + return 0;
8335 +
8336 + /* get error bit offset (4 bits) */
8337 + ecc_bit = ecc_readl(host->ecc, AT91_ECC_PR) & AT91_ECC_BITADDR;
8338 + /* get word address (12 bits) */
8339 + ecc_word = ecc_readl(host->ecc, AT91_ECC_PR) & AT91_ECC_WORDADDR;
8340 + ecc_word >>= 4;
8341 +
8342 + /* if there are multiple errors */
8343 + if (ecc_status & AT91_ECC_MULERR) {
8344 + /* Check if it is a freshly erased block (filled with 0xff) */
8345 + if ((ecc_bit == AT91_ECC_BITADDR)
8346 + && (ecc_word == (AT91_ECC_WORDADDR >> 4))) {
8347 + /* the block has just been erased, return OK */
8348 + return 0;
8349 + }
8350 + /*
8351 + * It doesn't seems to be a freshly-erased block.
8352 + * We can't correct so many errors.
8353 + */
8354 + dev_dbg(host->dev, "at91_nand : multiple errors detected."
8355 + " Unable to correct.\n");
8356 + return -EIO;
8357 + }
8358 +
8359 + /* if there's a single bit error : we can correct it */
8360 + if (ecc_status & AT91_ECC_ECCERR) {
8361 + /*
8362 + * There's nothing much to do here.
8363 + * The bit error is on the ECC itself.
8364 + */
8365 + dev_dbg(host->dev, "at91_nand : one bit error on ECC code."
8366 + " Nothing to correct\n");
8367 + return 0;
8368 + }
8369 +
8370 + dev_dbg(host->dev, "at91_nand : one bit error on data."
8371 + " (word offset in the page :"
8372 + " 0x%x bit offset : 0x%x)\n",
8373 + ecc_word, ecc_bit);
8374 + /* correct the error */
8375 + if (nand_chip->options & NAND_BUSWIDTH_16) {
8376 + /* 16 bits words */
8377 + ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
8378 + } else {
8379 + /* 8 bits words */
8380 + dat[ecc_word] ^= (1 << ecc_bit);
8381 + }
8382 + dev_dbg(host->dev, "at91_nand : error corrected\n");
8383 + return 1;
8384 +}
8385 +
8386 +/*
8387 + * Enable HW ECC : unsused
8388 + */
8389 +static void at91_nand_hwctl(struct mtd_info *mtd, int mode) { ; }
8390 +
8391 +/*
8392 + * Over-ride the standard functions with our optimized versions.
8393 + * We can use read/write blocks to move data to/from the controller.
8394 + */
8395 +static void at91_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
8396 +{
8397 + struct nand_chip *nand_chip = mtd->priv;
8398 +
8399 + __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
8400 +}
8401 +
8402 +static void at91_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
8403 +{
8404 + struct nand_chip *nand_chip = mtd->priv;
8405 +
8406 + __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
8407 +}
8408 +
8409 +static void at91_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
8410 +{
8411 + struct nand_chip *nand_chip = mtd->priv;
8412 +
8413 + __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
8414 +}
8415 +
8416 +static void at91_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
8417 +{
8418 + struct nand_chip *nand_chip = mtd->priv;
8419 +
8420 + __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
8421 +}
8422 +
8423 +
8424 #ifdef CONFIG_MTD_PARTITIONS
8425 -const char *part_probes[] = { "cmdlinepart", NULL };
8426 +static const char *part_probes[] = { "cmdlinepart", NULL };
8427 #endif
8428
8429 +static char* ecc_modes[] __initdata = { "No", "Software", "Hardware" };
8430 +
8431 /*
8432 * Probe for the NAND device.
8433 */
8434 @@ -94,6 +392,8 @@
8435 struct at91_nand_host *host;
8436 struct mtd_info *mtd;
8437 struct nand_chip *nand_chip;
8438 + struct resource *regs;
8439 + struct resource *mem;
8440 int res;
8441
8442 #ifdef CONFIG_MTD_PARTITIONS
8443 @@ -108,8 +408,13 @@
8444 return -ENOMEM;
8445 }
8446
8447 - host->io_base = ioremap(pdev->resource[0].start,
8448 - pdev->resource[0].end - pdev->resource[0].start + 1);
8449 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8450 + if (!mem) {
8451 + printk(KERN_ERR "at91_nand: can't get I/O resource mem\n");
8452 + return -ENXIO;
8453 + }
8454 +
8455 + host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
8456 if (host->io_base == NULL) {
8457 printk(KERN_ERR "at91_nand: ioremap failed\n");
8458 kfree(host);
8459 @@ -119,6 +424,7 @@
8460 mtd = &host->mtd;
8461 nand_chip = &host->nand_chip;
8462 host->board = pdev->dev.platform_data;
8463 + host->dev = &pdev->dev;
8464
8465 nand_chip->priv = host; /* link the private data structures */
8466 mtd->priv = nand_chip;
8467 @@ -132,11 +438,40 @@
8468 if (host->board->rdy_pin)
8469 nand_chip->dev_ready = at91_nand_device_ready;
8470
8471 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
8472 + if (!regs && hard_ecc) {
8473 + printk(KERN_ERR "at91_nand: can't get I/O resource "
8474 + "regs\nFalling back on software ECC\n");
8475 + }
8476 +
8477 nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
8478 + if (no_ecc)
8479 + nand_chip->ecc.mode = NAND_ECC_NONE;
8480 + if (hard_ecc && regs) {
8481 + host->ecc = (void __force __iomem *) (AT91_VA_BASE_SYS - AT91_BASE_SYS);
8482 + host->ecc += regs->start;
8483 +
8484 + nand_chip->ecc.mode = NAND_ECC_HW_SYNDROME; /* HW SYNDROME ECC */
8485 + nand_chip->ecc.calculate = at91_nand_calculate; /* function called after a write */
8486 + nand_chip->ecc.correct = at91_nand_correct; /* function called after a read */
8487 + nand_chip->ecc.hwctl = at91_nand_hwctl; /* unused */
8488 + nand_chip->ecc.read_page = at91_nand_read_page; /* read page function */
8489 + nand_chip->ecc.bytes = 4; /* 4 ECC bytes for any page size */
8490 + nand_chip->ecc.prepad = 0;
8491 + nand_chip->ecc.postpad = 0;
8492 + }
8493 +
8494 nand_chip->chip_delay = 20; /* 20us command delay time */
8495
8496 - if (host->board->bus_width_16) /* 16-bit bus width */
8497 + if (host->board->bus_width_16) { /* 16-bit bus width */
8498 nand_chip->options |= NAND_BUSWIDTH_16;
8499 + nand_chip->read_buf = at91_read_buf16;
8500 + nand_chip->write_buf = at91_write_buf16;
8501 + }
8502 + else {
8503 + nand_chip->read_buf = at91_read_buf8;
8504 + nand_chip->write_buf = at91_write_buf8;
8505 + }
8506
8507 platform_set_drvdata(pdev, host);
8508 at91_nand_enable(host);
8509 @@ -149,8 +484,60 @@
8510 }
8511 }
8512
8513 - /* Scan to find existance of the device */
8514 - if (nand_scan(mtd, 1)) {
8515 + /* first scan to find the device and get the page size */
8516 + if (nand_scan_ident(mtd, 1)) {
8517 + res = -ENXIO;
8518 + goto out;
8519 + }
8520 +
8521 + if (nand_chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
8522 + /* ECC is calculated for the whole page (1 step) */
8523 + nand_chip->ecc.size = mtd->writesize;
8524 +
8525 + /* set ECC page size and oob layout */
8526 + switch (mtd->writesize) {
8527 + case 512:
8528 + nand_chip->ecc.layout = &at91_oobinfo_small;
8529 + nand_chip->ecc.read_oob = at91_nand_read_oob_512;
8530 + nand_chip->ecc.write_oob = at91_nand_write_oob_512;
8531 + ecc_writel(host->ecc, AT91_ECC_MR, AT91_ECC_PAGESIZE_528);
8532 + break;
8533 + case 1024:
8534 + nand_chip->ecc.layout = &at91_oobinfo_large;
8535 + ecc_writel(host->ecc, AT91_ECC_MR, AT91_ECC_PAGESIZE_1056);
8536 + break;
8537 + case 2048:
8538 + nand_chip->ecc.layout = &at91_oobinfo_large;
8539 + ecc_writel(host->ecc, AT91_ECC_MR, AT91_ECC_PAGESIZE_2112);
8540 + break;
8541 + case 4096:
8542 + nand_chip->ecc.layout = &at91_oobinfo_large;
8543 + ecc_writel(host->ecc, AT91_ECC_MR, AT91_ECC_PAGESIZE_4224);
8544 + break;
8545 + default:
8546 + /*
8547 + * Page size not supported by HW ECC.
8548 + * So switch back to soft ECC
8549 + */
8550 + nand_chip->ecc.mode = NAND_ECC_SOFT;
8551 + nand_chip->ecc.calculate = NULL;
8552 + nand_chip->ecc.correct = NULL;
8553 + nand_chip->ecc.hwctl = NULL;
8554 + nand_chip->ecc.read_page = NULL;
8555 + nand_chip->ecc.postpad = 0;
8556 + nand_chip->ecc.prepad = 0;
8557 + nand_chip->ecc.bytes = 0;
8558 + break;
8559 + }
8560 + }
8561 +
8562 + printk(KERN_INFO "AT91 NAND: %i-bit, %s ECC\n",
8563 + (nand_chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
8564 + ecc_modes[nand_chip->ecc.mode]
8565 + );
8566 +
8567 + /* second phase scan */
8568 + if (nand_scan_tail(mtd)) {
8569 res = -ENXIO;
8570 goto out;
8571 }
8572 @@ -179,8 +566,11 @@
8573 if (!res)
8574 return res;
8575
8576 +#ifdef CONFIG_MTD_PARTITIONS
8577 release:
8578 +#endif
8579 nand_release(mtd);
8580 +
8581 out:
8582 at91_nand_disable(host);
8583 platform_set_drvdata(pdev, NULL);
8584 @@ -192,7 +582,7 @@
8585 /*
8586 * Remove a NAND device.
8587 */
8588 -static int __devexit at91_nand_remove(struct platform_device *pdev)
8589 +static int __exit at91_nand_remove(struct platform_device *pdev)
8590 {
8591 struct at91_nand_host *host = platform_get_drvdata(pdev);
8592 struct mtd_info *mtd = &host->mtd;
8593 @@ -208,8 +598,7 @@
8594 }
8595
8596 static struct platform_driver at91_nand_driver = {
8597 - .probe = at91_nand_probe,
8598 - .remove = at91_nand_remove,
8599 + .remove = __exit_p(at91_nand_remove),
8600 .driver = {
8601 .name = "at91_nand",
8602 .owner = THIS_MODULE,
8603 @@ -218,7 +607,7 @@
8604
8605 static int __init at91_nand_init(void)
8606 {
8607 - return platform_driver_register(&at91_nand_driver);
8608 + return platform_driver_probe(&at91_nand_driver, at91_nand_probe);
8609 }
8610
8611
8612 @@ -233,4 +622,4 @@
8613
8614 MODULE_LICENSE("GPL");
8615 MODULE_AUTHOR("Rick Bronson");
8616 -MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200");
8617 +MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200 / AT91SAM9 / AT91CAP9");
8618 --- a/drivers/net/arm/Kconfig
8619 +++ b/drivers/net/arm/Kconfig
8620 @@ -47,3 +47,10 @@
8621 help
8622 This is a driver for the ethernet hardware included in EP93xx CPUs.
8623 Say Y if you are building a kernel for EP93xx based devices.
8624 +
8625 +config ARM_KS8695_ETHER
8626 + tristate "KS8695 Ethernet support"
8627 + depends on NET_ETHERNET && ARM && ARCH_KS8695
8628 + help
8629 + If you wish to compile a kernel for an KS8695-based board
8630 + and enable Ethernet support, then select this option.
8631 --- a/drivers/net/arm/Makefile
8632 +++ b/drivers/net/arm/Makefile
8633 @@ -9,3 +9,4 @@
8634 obj-$(CONFIG_ARM_ETHER1) += ether1.o
8635 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
8636 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
8637 +obj-$(CONFIG_ARM_KS8695_ETHER) += ks8695_ether.o
8638 --- a/drivers/net/arm/at91_ether.c
8639 +++ b/drivers/net/arm/at91_ether.c
8640 @@ -220,7 +220,7 @@
8641 if (!(phy & (1 << 0)))
8642 goto done;
8643 }
8644 - else if (lp->phy_type == MII_KS8721_ID) {
8645 + else if ((lp->phy_type == MII_KS8721_ID) || (lp->phy_type == MII_KSZ8041_ID)) {
8646 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
8647 if (!(phy & ((1 << 2) | 1)))
8648 goto done;
8649 @@ -286,7 +286,7 @@
8650 dsintr = (1 << 15) | ( 1 << 14);
8651 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
8652 }
8653 - else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
8654 + else if ((lp->phy_type == MII_KS8721_ID) || (lp->phy_type == MII_KSZ8041_ID)) { /* for Micrel PHY */
8655 dsintr = (1 << 10) | ( 1 << 8);
8656 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
8657 }
8658 @@ -341,7 +341,7 @@
8659 dsintr = ~(1 << 14);
8660 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
8661 }
8662 - else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
8663 + else if ((lp->phy_type == MII_KS8721_ID) || (lp->phy_type == MII_KSZ8041_ID)) { /* for Micrel PHY */
8664 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
8665 dsintr = ~((1 << 10) | (1 << 8));
8666 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
8667 @@ -820,7 +820,7 @@
8668 lp->skb = skb;
8669 lp->skb_length = skb->len;
8670 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
8671 - lp->stats.tx_bytes += skb->len;
8672 + dev->stats.tx_bytes += skb->len;
8673
8674 /* Set address of the data in the Transmit Address register */
8675 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
8676 @@ -843,34 +843,32 @@
8677 */
8678 static struct net_device_stats *at91ether_stats(struct net_device *dev)
8679 {
8680 - struct at91_private *lp = netdev_priv(dev);
8681 - int ale, lenerr, seqe, lcol, ecol;
8682 + int ale, lenerr, seqe, ecol;
8683
8684 if (netif_running(dev)) {
8685 - lp->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
8686 + dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
8687 ale = at91_emac_read(AT91_EMAC_ALE);
8688 - lp->stats.rx_frame_errors += ale; /* Alignment errors */
8689 + dev->stats.rx_frame_errors += ale; /* Alignment errors */
8690 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
8691 - lp->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
8692 + dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
8693 seqe = at91_emac_read(AT91_EMAC_SEQE);
8694 - lp->stats.rx_crc_errors += seqe; /* CRC error */
8695 - lp->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
8696 - lp->stats.rx_errors += (ale + lenerr + seqe
8697 + dev->stats.rx_crc_errors += seqe; /* CRC error */
8698 + dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
8699 + dev->stats.rx_errors += (ale + lenerr + seqe
8700 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
8701
8702 - lp->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
8703 - lp->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
8704 - lp->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
8705 - lp->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
8706 + dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
8707 + dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
8708 + dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
8709 + dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
8710
8711 - lcol = at91_emac_read(AT91_EMAC_LCOL);
8712 + dev->stats.tx_window_errors += at91_emac_read(AT91_EMAC_LCOL); /* Late collisions */
8713 ecol = at91_emac_read(AT91_EMAC_ECOL);
8714 - lp->stats.tx_window_errors += lcol; /* Late collisions */
8715 - lp->stats.tx_aborted_errors += ecol; /* 16 collisions */
8716 + dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
8717
8718 - lp->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
8719 + dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + ecol);
8720 }
8721 - return &lp->stats;
8722 + return &dev->stats;
8723 }
8724
8725 /*
8726 @@ -896,16 +894,16 @@
8727
8728 skb->protocol = eth_type_trans(skb, dev);
8729 dev->last_rx = jiffies;
8730 - lp->stats.rx_bytes += pktlen;
8731 + dev->stats.rx_bytes += pktlen;
8732 netif_rx(skb);
8733 }
8734 else {
8735 - lp->stats.rx_dropped += 1;
8736 + dev->stats.rx_dropped += 1;
8737 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
8738 }
8739
8740 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
8741 - lp->stats.multicast++;
8742 + dev->stats.multicast++;
8743
8744 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
8745 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
8746 @@ -934,7 +932,7 @@
8747 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
8748 /* The TCOM bit is set even if the transmission failed. */
8749 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
8750 - lp->stats.tx_errors += 1;
8751 + dev->stats.tx_errors += 1;
8752
8753 if (lp->skb) {
8754 dev_kfree_skb_irq(lp->skb);
8755 @@ -978,15 +976,22 @@
8756 struct net_device *dev;
8757 struct at91_private *lp;
8758 unsigned int val;
8759 - int res;
8760 + struct resource *res;
8761 + int ret;
8762 DECLARE_MAC_BUF(mac);
8763
8764 dev = alloc_etherdev(sizeof(struct at91_private));
8765 if (!dev)
8766 return -ENOMEM;
8767
8768 - dev->base_addr = AT91_VA_BASE_EMAC;
8769 - dev->irq = AT91RM9200_ID_EMAC;
8770 + /* Get I/O base address and IRQ */
8771 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8772 + if (!res) {
8773 + free_netdev(dev);
8774 + return -ENODEV;
8775 + }
8776 + dev->base_addr = res->start;
8777 + dev->irq = platform_get_irq(pdev, 0);
8778
8779 /* Install the interrupt handler */
8780 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
8781 @@ -1043,7 +1048,9 @@
8782 } else if (machine_is_csb337()) {
8783 /* mix link activity status into LED2 link state */
8784 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
8785 - }
8786 + } else if (machine_is_ecbat91())
8787 + write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
8788 +
8789 disable_mdi();
8790 spin_unlock_irq(&lp->lock);
8791
8792 @@ -1058,12 +1065,12 @@
8793 lp->phy_address = phy_address; /* MDI address of PHY */
8794
8795 /* Register the network interface */
8796 - res = register_netdev(dev);
8797 - if (res) {
8798 + ret = register_netdev(dev);
8799 + if (ret) {
8800 free_irq(dev->irq, dev);
8801 free_netdev(dev);
8802 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
8803 - return res;
8804 + return ret;
8805 }
8806
8807 /* Determine current link speed */
8808 @@ -1101,6 +1108,8 @@
8809 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
8810 else if (phy_type == MII_AC101L_ID)
8811 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
8812 + else if (phy_type == MII_KSZ8041_ID)
8813 + printk(KERN_INFO "%s: Micrel KSZ8041 PHY\n", dev->name);
8814 else if (phy_type == MII_KS8721_ID)
8815 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
8816 else if (phy_type == MII_T78Q21x3_ID)
8817 @@ -1146,6 +1155,7 @@
8818 case MII_DP83847_ID: /* National Semiconductor DP83847: */
8819 case MII_DP83848_ID: /* National Semiconductor DP83848: */
8820 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
8821 + case MII_KSZ8041_ID: /* Micrel KSZ8041: PHY_ID1 = 0x22, PHY_ID2 = 0x1512 */
8822 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
8823 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
8824 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
8825 @@ -1246,3 +1256,4 @@
8826 MODULE_LICENSE("GPL");
8827 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
8828 MODULE_AUTHOR("Andrew Victor");
8829 +MODULE_ALIAS("platform:" DRV_NAME);
8830 --- a/drivers/net/arm/at91_ether.h
8831 +++ b/drivers/net/arm/at91_ether.h
8832 @@ -48,6 +48,9 @@
8833 /* Altima AC101L PHY */
8834 #define MII_AC101L_ID 0x00225520
8835
8836 +/* Micrel KSZ8041 PHY */
8837 +#define MII_KSZ8041_ID 0x00221510
8838 +
8839 /* Micrel KS8721 PHY */
8840 #define MII_KS8721_ID 0x00221610
8841
8842 @@ -84,7 +87,6 @@
8843
8844 struct at91_private
8845 {
8846 - struct net_device_stats stats;
8847 struct mii_if_info mii; /* ethtool support */
8848 struct at91_eth_data board_data; /* board-specific configuration */
8849 struct clk *ether_clk; /* clock */
8850 --- /dev/null
8851 +++ b/drivers/net/arm/ks8695_ether.c
8852 @@ -0,0 +1,1009 @@
8853 +/*
8854 + * Ethernet driver for the Kendin/Micrel KS8695.
8855 + *
8856 + * Copyright (C) 2006 Andrew Victor
8857 + *
8858 + * This program is free software; you can redistribute it and/or
8859 + * modify it under the terms of the GNU General Public License
8860 + * as published by the Free Software Foundation; either version
8861 + * 2 of the License, or (at your option) any later version.
8862 + */
8863 +
8864 +#include <linux/module.h>
8865 +#include <linux/init.h>
8866 +#include <linux/mii.h>
8867 +#include <linux/netdevice.h>
8868 +#include <linux/etherdevice.h>
8869 +#include <linux/skbuff.h>
8870 +#include <linux/dma-mapping.h>
8871 +#include <linux/delay.h>
8872 +#include <linux/ethtool.h>
8873 +#include <linux/platform_device.h>
8874 +
8875 +#include <asm/io.h>
8876 +#include <asm/mach/irq.h>
8877 +#include <asm/uaccess.h>
8878 +#include <asm/arch/regs-wan.h>
8879 +#include <asm/arch/regs-lan.h>
8880 +#include <asm/arch/regs-hpna.h>
8881 +#include <asm/arch/regs-switch.h>
8882 +#include <asm/arch/regs-misc.h>
8883 +
8884 +#include <asm/arch/regs-irq.h>
8885 +
8886 +#include "ks8695_ether.h"
8887 +
8888 +
8889 +#define DRV_NAME "ks8695_ether"
8890 +#define DRV_VERSION "0.01"
8891 +
8892 +/* ..................................................................... */
8893 +
8894 +static inline unsigned long ks8695_read(struct net_device *dev, unsigned int reg)
8895 +{
8896 + return __raw_readl(dev->base_addr + reg);
8897 +}
8898 +
8899 +static inline void ks8695_write(struct net_device *dev, unsigned int reg, unsigned long value)
8900 +{
8901 + __raw_writel(value, dev->base_addr + reg);
8902 +}
8903 +
8904 +
8905 +/* ......................... ADDRESS MANAGEMENT ........................ */
8906 +
8907 +#define KS8695_NR_ADDRESSES 16
8908 +
8909 +/*
8910 + * Add the specified multicast addresses to the Additional Station
8911 + * Address registers.
8912 + */
8913 +static void ks8695_set_mcast_address(struct net_device *dev, struct dev_mc_list *addr, int nr_addr)
8914 +{
8915 + unsigned long low, high;
8916 + int i;
8917 +
8918 + /* Set multicast addresses in Additional Station Address registers */
8919 + for (i = 0; i < nr_addr; i++, addr = addr->next) {
8920 + if (!addr) break; /* unexpected end of list */
8921 + else if (i == KS8695_NR_ADDRESSES) break; /* too many addresses */
8922 +
8923 + low = (addr->dmi_addr[2] << 24) | (addr->dmi_addr[3] << 16) | (addr->dmi_addr[4] << 8) | (addr->dmi_addr[5]);
8924 + high = (addr->dmi_addr[0] << 8) | (addr->dmi_addr[1]);
8925 +
8926 + ks8695_write(dev, KS8695_WMAAL_(i), low);
8927 + ks8695_write(dev, KS8695_WMAAH_(i), WMAAH_E | high);
8928 + }
8929 +
8930 + /* Clear the remaining Additional Station Addresses */
8931 + for (; i < KS8695_NR_ADDRESSES; i++) {
8932 + ks8695_write(dev, KS8695_WMAAL_(i), 0);
8933 + ks8695_write(dev, KS8695_WMAAH_(i), 0);
8934 + }
8935 +}
8936 +
8937 +/*
8938 + * Enable/Disable promiscuous and multicast modes.
8939 + */
8940 +static void ks8695eth_set_multi(struct net_device *dev)
8941 +{
8942 + unsigned long ctrl;
8943 +
8944 + ctrl = ks8695_read(dev, KS8695_WMDRXC);
8945 +
8946 + if (dev->flags & IFF_PROMISC) /* enable promiscuous mode */
8947 + ctrl |= WMDRXC_WMRA;
8948 + else if (dev->flags & ~IFF_PROMISC) /* disable promiscuous mode */
8949 + ctrl &= ~WMDRXC_WMRA;
8950 +
8951 + if (dev->flags & IFF_ALLMULTI) /* enable all multicast mode */
8952 + ctrl |= WMDRXC_WMRM;
8953 + else if (dev->mc_count > KS8695_NR_ADDRESSES) /* more specific multicast addresses than can be handled in hardware */
8954 + ctrl |= WMDRXC_WMRM;
8955 + else if (dev->mc_count > 0) { /* enable specific multicasts */
8956 + ctrl &= ~WMDRXC_WMRM;
8957 + ks8695_set_mcast_address(dev, dev->mc_list, dev->mc_count);
8958 + }
8959 + else if (dev->flags & ~IFF_ALLMULTI) { /* disable multicast mode */
8960 + ctrl &= ~WMDRXC_WMRM;
8961 + ks8695_set_mcast_address(dev, NULL, 0);
8962 + }
8963 +
8964 + ks8695_write(dev, KS8695_WMDRXC, ctrl);
8965 +}
8966 +
8967 +/*
8968 + * Program the hardware MAC address from dev->dev_addr.
8969 + */
8970 +static void update_mac_address(struct net_device *dev)
8971 +{
8972 + unsigned long low, high;
8973 +
8974 + low = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | (dev->dev_addr[4] << 8) | (dev->dev_addr[5]);
8975 + high = (dev->dev_addr[0] << 8) | (dev->dev_addr[1]);
8976 +
8977 + ks8695_write(dev, KS8695_WMAL, low);
8978 + ks8695_write(dev, KS8695_WMAH, high);
8979 +}
8980 +
8981 +/*
8982 + * Store the new hardware address in dev->dev_addr, and update the MAC.
8983 + */
8984 +static int ks8695eth_set_mac(struct net_device *dev, void* addr)
8985 +{
8986 + struct sockaddr *address = addr;
8987 + DECLARE_MAC_BUF(mac);
8988 +
8989 + if (!is_valid_ether_addr(address->sa_data))
8990 + return -EADDRNOTAVAIL;
8991 +
8992 + memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
8993 + update_mac_address(dev);
8994 +
8995 + printk("%s: Setting MAC address to %s\n", dev->name, print_mac(mac, dev->dev_addr));
8996 +
8997 + return 0;
8998 +}
8999 +
9000 +/*
9001 + * Retrieve the MAC address set by the bootloader.
9002 + */
9003 +static void __init get_mac_address(struct net_device *dev)
9004 +{
9005 + unsigned char addr[6];
9006 + unsigned long low, high;
9007 +
9008 + low = ks8695_read(dev, KS8695_WMAL);
9009 + high = ks8695_read(dev, KS8695_WMAH);
9010 +
9011 + addr[0] = (high & 0xff00) >> 8;
9012 + addr[1] = (high & 0xff);
9013 + addr[2] = (low & 0xff000000) >> 24;
9014 + addr[3] = (low & 0xff0000) >> 16;
9015 + addr[4] = (low & 0xff00) >> 8;
9016 + addr[5] = (low & 0xff);
9017 +
9018 + if (is_valid_ether_addr(addr))
9019 + memcpy(dev->dev_addr, &addr, 6);
9020 +}
9021 +
9022 +
9023 +/* ......................... ETHTOOL SUPPORT ........................... */
9024 +
9025 +/*
9026 + * Get device-specific settings.
9027 + */
9028 +static int ks8695eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9029 +{
9030 + unsigned long ctrl;
9031 +
9032 + /* the defaults for all ports */
9033 + cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
9034 + | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
9035 + | SUPPORTED_TP | SUPPORTED_MII;
9036 + cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
9037 + cmd->port = PORT_MII;
9038 + cmd->transceiver = XCVR_INTERNAL;
9039 +
9040 + if (dev->base_addr == KS8695_HPNA_VA) {
9041 + cmd->phy_address = 0;
9042 + cmd->autoneg = AUTONEG_DISABLE; /* not supported for HPNA */
9043 +
9044 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_HMC);
9045 + cmd->speed = (ctrl & HMC_HSS) ? SPEED_100 : SPEED_10;
9046 + cmd->duplex = (ctrl & HMC_HDS) ? DUPLEX_FULL : DUPLEX_HALF;
9047 + }
9048 + else if (dev->base_addr == KS8695_WAN_VA) {
9049 + cmd->supported |= (SUPPORTED_Autoneg | SUPPORTED_Pause);
9050 + cmd->phy_address = 0;
9051 +
9052 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC);
9053 + if ((ctrl & WMC_WAND) == 0) { /* auto-negotiation is enabled */
9054 + cmd->advertising |= ADVERTISED_Autoneg;
9055 + if (ctrl & WMC_WANA100F)
9056 + cmd->advertising |= ADVERTISED_100baseT_Full;
9057 + if (ctrl & WMC_WANA100H)
9058 + cmd->advertising |= ADVERTISED_100baseT_Half;
9059 + if (ctrl & WMC_WANA10F)
9060 + cmd->advertising |= ADVERTISED_10baseT_Full;
9061 + if (ctrl & WMC_WANA10H)
9062 + cmd->advertising |= ADVERTISED_10baseT_Half;
9063 + if (ctrl & WMC_WANAP)
9064 + cmd->advertising |= ADVERTISED_Pause;
9065 + cmd->autoneg = AUTONEG_ENABLE;
9066 +
9067 + cmd->speed = (ctrl & WMC_WSS) ? SPEED_100 : SPEED_10;
9068 + cmd->duplex = (ctrl & WMC_WDS) ? DUPLEX_FULL : DUPLEX_HALF;
9069 + }
9070 + else { /* auto-negotiation is disabled */
9071 + cmd->autoneg = AUTONEG_DISABLE;
9072 +
9073 + cmd->speed = (ctrl & WMC_WANF100) ? SPEED_100 : SPEED_10;
9074 + cmd->duplex = (ctrl & WMC_WANFF) ? DUPLEX_FULL : DUPLEX_HALF;
9075 + }
9076 + }
9077 + else if (dev->base_addr == KS8695_LAN_VA) {
9078 + // TODO: Implement for Switch ports
9079 + }
9080 +
9081 + return 0;
9082 +}
9083 +
9084 +/*
9085 + * Set device-specific settings.
9086 + */
9087 +static int ks8695eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9088 +{
9089 + unsigned long ctrl;
9090 +
9091 + if ((cmd->speed != SPEED_10) && (cmd->speed != SPEED_100))
9092 + return -EINVAL;
9093 + if ((cmd->duplex != DUPLEX_HALF) && (cmd->duplex != DUPLEX_FULL))
9094 + return -EINVAL;
9095 + if (cmd->port != PORT_MII)
9096 + return -EINVAL;
9097 + if (cmd->transceiver != XCVR_INTERNAL)
9098 + return -EINVAL;
9099 + if ((cmd->autoneg != AUTONEG_DISABLE) && (cmd->autoneg != AUTONEG_ENABLE))
9100 + return -EINVAL;
9101 +
9102 + if (cmd->autoneg == AUTONEG_ENABLE) {
9103 + if ((cmd->advertising & (ADVERTISED_10baseT_Half |
9104 + ADVERTISED_10baseT_Full |
9105 + ADVERTISED_100baseT_Half |
9106 + ADVERTISED_100baseT_Full)) == 0)
9107 + return -EINVAL;
9108 +
9109 + if (dev->base_addr == KS8695_HPNA_VA)
9110 + return -EINVAL; /* HPNA does not support auto-negotiation. */
9111 + else if (dev->base_addr == KS8695_WAN_VA) {
9112 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC);
9113 +
9114 + ctrl &= ~(WMC_WAND | WMC_WANA100F | WMC_WANA100H | WMC_WANA10F | WMC_WANA10H);
9115 + if (cmd->advertising & ADVERTISED_100baseT_Full)
9116 + ctrl |= WMC_WANA100F;
9117 + if (cmd->advertising & ADVERTISED_100baseT_Half)
9118 + ctrl |= WMC_WANA100H;
9119 + if (cmd->advertising & ADVERTISED_10baseT_Full)
9120 + ctrl |= WMC_WANA10F;
9121 + if (cmd->advertising & ADVERTISED_10baseT_Half)
9122 + ctrl |= WMC_WANA10H;
9123 +
9124 + ctrl |= WMC_WANR; /* force a re-negotiation */
9125 + __raw_writel(ctrl, KS8695_MISC_VA + KS8695_WMC);
9126 + }
9127 + else if (dev->base_addr == KS8695_LAN_VA) {
9128 + // TODO: Implement for Switch ports
9129 + }
9130 +
9131 + }
9132 + else {
9133 + if (dev->base_addr == KS8695_HPNA_VA) {
9134 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_HMC);
9135 +
9136 + ctrl &= ~(HMC_HSS | HMC_HDS);
9137 + if (cmd->speed == SPEED_100)
9138 + ctrl |= HMC_HSS;
9139 + if (cmd->duplex == DUPLEX_FULL)
9140 + ctrl |= HMC_HDS;
9141 +
9142 + __raw_writel(ctrl, KS8695_MISC_VA + KS8695_HMC);
9143 + }
9144 + else if (dev->base_addr == KS8695_WAN_VA) {
9145 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC);
9146 +
9147 + ctrl |= WMC_WAND; /* disable auto-negotiation */
9148 + ctrl &= ~(WMC_WANF100 | WMC_WANFF);
9149 + if (cmd->speed == SPEED_100)
9150 + ctrl |= WMC_WANF100;
9151 + if (cmd->duplex == DUPLEX_FULL)
9152 + ctrl |= WMC_WANFF;
9153 +
9154 + __raw_writel(ctrl, KS8695_MISC_VA + KS8695_WMC);
9155 + }
9156 + else if (dev->base_addr == KS8695_LAN_VA) {
9157 + // TODO: Implement for Switch ports
9158 + }
9159 + }
9160 +
9161 + return 0;
9162 +}
9163 +
9164 +/*
9165 + * Restart the auto-negotiation.
9166 + */
9167 +static int ks8695eth_nwayreset(struct net_device *dev)
9168 +{
9169 + unsigned long ctrl;
9170 +
9171 + if (dev->base_addr == KS8695_HPNA_VA) /* HPNA has no auto-negotiation */
9172 + return -EINVAL;
9173 + else if (dev->base_addr == KS8695_WAN_VA) {
9174 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC);
9175 +
9176 + if ((ctrl & WMC_WAND) == 0)
9177 + __raw_writel(ctrl | WMC_WANR, KS8695_MISC_VA + KS8695_WMC);
9178 + else
9179 + return -EINVAL; /* auto-negitiation not enabled */
9180 + }
9181 + else if (dev->base_addr == KS8695_LAN_VA) {
9182 + // TODO: Implement for Switch ports
9183 + }
9184 +
9185 + return 0;
9186 +}
9187 +
9188 +static void ks8695eth_get_pause(struct net_device *dev, struct ethtool_pauseparam *param)
9189 +{
9190 + unsigned long ctrl;
9191 +
9192 + if (dev->base_addr == KS8695_HPNA_VA)
9193 + return;
9194 + else if (dev->base_addr == KS8695_WAN_VA) {
9195 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC); /* advertise Pause */
9196 + param->autoneg = (ctrl & WMC_WANAP);
9197 +
9198 + ctrl = ks8695_read(dev, KS8695_WMDRXC); /* current Tx Flow-control */
9199 + param->rx_pause = (ctrl & WMDRXC_WMRFCE);
9200 +
9201 + ctrl = ks8695_read(dev, KS8695_WMDRXC); /* current Rx Flow-control */
9202 + param->tx_pause = (ctrl & WMDTXC_WMTFCE);
9203 + }
9204 + else if (dev->base_addr == KS8695_LAN_VA) {
9205 + // TODO: Implement for Switch ports
9206 + }
9207 +}
9208 +
9209 +static int ks8695eth_set_pause(struct net_device *dev, struct ethtool_pauseparam *param)
9210 +{
9211 + // TODO.
9212 +
9213 + return 0;
9214 +}
9215 +
9216 +static u32 ks8695eth_get_link(struct net_device *dev)
9217 +{
9218 + unsigned long ctrl;
9219 +
9220 + if (dev->base_addr == KS8695_HPNA_VA)
9221 + return 1; /* HPNA always has link */
9222 + else if (dev->base_addr == KS8695_WAN_VA) {
9223 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC);
9224 + return (ctrl & WMC_WLS);
9225 + }
9226 + else if (dev->base_addr == KS8695_LAN_VA) {
9227 + // TODO: Implement for Switch ports
9228 + }
9229 +
9230 + return 0;
9231 +}
9232 +
9233 +/*
9234 + * Report driver information.
9235 + */
9236 +static void ks8695eth_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9237 +{
9238 + strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
9239 + strlcpy(info->version, DRV_VERSION, sizeof(info->version));
9240 + strlcpy(info->bus_info, dev->dev.parent->bus_id, sizeof(info->bus_info));
9241 +}
9242 +
9243 +static struct ethtool_ops ks8695eth_ethtool_ops = {
9244 + .get_settings = ks8695eth_get_settings,
9245 + .set_settings = ks8695eth_set_settings,
9246 + .get_drvinfo = ks8695eth_get_drvinfo,
9247 + .nway_reset = ks8695eth_nwayreset,
9248 + .get_pauseparam = ks8695eth_get_pause,
9249 + .set_pauseparam = ks8695eth_set_pause,
9250 + .get_link = ks8695eth_get_link,
9251 +};
9252 +
9253 +
9254 +/* ................................ MAC ................................ */
9255 +
9256 +/*
9257 + * Setup the RX DMA descriptors, and enable and start the DMA receiver.
9258 + */
9259 +static void ks8695eth_start_rx(struct net_device *dev)
9260 +{
9261 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9262 + unsigned long ctrl;
9263 + int i;
9264 +
9265 + /* Setup the DMA descriptors */
9266 + for (i = 0; i < MAX_RX_DESC; i++) {
9267 + lp->rxdma[i].length = MAX_RXBUF_SIZE;
9268 + lp->rxdma[i].addr = (unsigned long) lp->rxSkb[i].dma;
9269 + lp->rxdma[i].next = (unsigned long) lp->rxdma_phys + (sizeof(struct rx_descriptor) * (i+1));
9270 + lp->rxdma[i].status = RDES_OWN;
9271 + }
9272 +
9273 + /* Create ring of DMA descriptors */
9274 + lp->rxdma[MAX_RX_DESC-1].next = (unsigned long) lp->rxdma_phys; /* phys address of 1st descriptor */
9275 +
9276 + /* Reset receive index (since hardware was reset) */
9277 + lp->rx_idx = 0;
9278 +
9279 + /* Program address of 1st descriptor in KS8695 */
9280 + ks8695_write(dev, KS8695_WRDLB, (unsigned long) lp->rxdma_phys);
9281 +
9282 + /* Enable and start the DMA Receiver */
9283 + ctrl = ks8695_read(dev, KS8695_WMDRXC);
9284 + ks8695_write(dev, KS8695_WMDRXC, ctrl | WMDRXC_WMRE);
9285 + ks8695_write(dev, KS8695_WMDRSC, 0);
9286 +}
9287 +
9288 +/*
9289 + * Stop the DMA receiver.
9290 + */
9291 +static void ks8695eth_stop_rx(struct net_device *dev)
9292 +{
9293 + unsigned long ctrl;
9294 +
9295 + /* Disable receive DMA */
9296 + ctrl = ks8695_read(dev, KS8695_WMDRXC);
9297 + ks8695_write(dev, KS8695_WMDRXC, ctrl & ~WMDRXC_WMRE);
9298 +}
9299 +
9300 +/*
9301 + * Setup the TX DMA descriptors, and enable DMA transmitter.
9302 + */
9303 +static void ks8695eth_start_tx(struct net_device *dev)
9304 +{
9305 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9306 + unsigned long ctrl;
9307 + int i;
9308 +
9309 + /* Setup the DMA descriptors */
9310 + for (i = 0; i < MAX_TX_DESC; i++) {
9311 + lp->txdma[i].ownership = 0;
9312 + lp->txdma[i].status = 0;
9313 + lp->txdma[i].addr = 0;
9314 + lp->txdma[i].next = (unsigned long) lp->txdma_phys + (sizeof(struct tx_descriptor) * (i+1));
9315 + }
9316 +
9317 + /* Create ring of DMA descriptors */
9318 + lp->txdma[MAX_TX_DESC-1].next = (unsigned long) lp->txdma_phys; /* phys address of 1st desc */
9319 +
9320 + /* Reset transmit indexes (since hardware was reset) */
9321 + lp->tx_head = 0;
9322 + lp->tx_tail = 0;
9323 +
9324 + /* Program address of 1st descriptor in KS8695 */
9325 + ks8695_write(dev, KS8695_WTDLB, (unsigned long) lp->txdma_phys);
9326 +
9327 + /* Enable the DMA transmitter (will be started on first packet) */
9328 + ctrl = ks8695_read(dev, KS8695_WMDTXC);
9329 + ks8695_write(dev, KS8695_WMDTXC, ctrl | WMDTXC_WMTE);
9330 +}
9331 +
9332 +/*
9333 + * Stop the DMA transmitter.
9334 + */
9335 +static void ks8695eth_stop_tx(struct net_device *dev)
9336 +{
9337 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9338 + unsigned long ctrl;
9339 + int i;
9340 +
9341 + /* Disable transmit DMA */
9342 + ctrl = ks8695_read(dev, KS8695_WMDTXC);
9343 + ks8695_write(dev, KS8695_WMDTXC, ctrl & ~WMDTXC_WMTE);
9344 +
9345 + /* Clear any pending skb's still on transmit queue */
9346 + for (i = 0; i < MAX_TX_DESC; i++) {
9347 + lp->txdma[i].ownership = 0;
9348 + lp->txdma[i].status = 0;
9349 + lp->txdma[i].addr = 0;
9350 +
9351 + if (lp->txSkb[i].skb) {
9352 + dma_unmap_single(lp->dev, lp->txSkb[i].dma, lp->txSkb[i].length, DMA_TO_DEVICE);
9353 + dev_kfree_skb_irq(lp->txSkb[i].skb);
9354 + lp->txSkb[i].skb = NULL;
9355 + }
9356 + }
9357 +}
9358 +
9359 +/*
9360 + * Reset the MAC hardware.
9361 + */
9362 +static void ks8695eth_hw_reset(struct net_device *dev)
9363 +{
9364 + /* Perform hardware reset */
9365 + ks8695_write(dev, KS8695_WMDTXC, WMDTXC_WMTRST);
9366 + while (ks8695_read(dev, KS8695_WMDTXC) & WMDTXC_WMTRST) { barrier(); }
9367 +
9368 + /* Initialize the hardware */
9369 + ks8695_write(dev, KS8695_WMDRXC, WMDRXC_WMRU | WMDRXC_WMRB); /* RX: receive Unicast & Broadcast */
9370 + ks8695_write(dev, KS8695_WMDTXC, WMDTXC_WMTEP | WMDTXC_WMTAC); /* TX: add Padding & CRC */
9371 +
9372 + // TODO: Can set Rx/Tx PBL: (Micrel using 8)
9373 + // TODO: Enable hardware checksumming.
9374 + // TODO: Enable Rx/Tx flow-control
9375 +}
9376 +
9377 +/*
9378 + * Enable or Disable the IRQs associated with a network interface.
9379 + */
9380 +static void ks8695eth_set_irq(struct net_device *dev, short enable)
9381 +{
9382 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9383 + int i;
9384 +
9385 + for (i = 0; i < NR_IRQS; i++) {
9386 + if (lp->irqs & (1 << i)) {
9387 + if (enable)
9388 + enable_irq(i);
9389 + else
9390 + disable_irq(i);
9391 + }
9392 + }
9393 +}
9394 +
9395 +/*
9396 + * Open the ethernet interface.
9397 + */
9398 +static int ks8695eth_open(struct net_device *dev)
9399 +{
9400 + if (!is_valid_ether_addr(dev->dev_addr))
9401 + return -EADDRNOTAVAIL;
9402 +
9403 + /* MUST reset hardware in _open() */
9404 + ks8695eth_hw_reset(dev);
9405 +
9406 + /* Update the MAC address (incase user has changed it) */
9407 + update_mac_address(dev);
9408 +
9409 + /* Start DMA */
9410 + ks8695eth_start_tx(dev);
9411 + ks8695eth_start_rx(dev);
9412 +
9413 + /* Enable interrupts */
9414 + ks8695eth_set_irq(dev, 1);
9415 +
9416 + netif_start_queue(dev);
9417 + return 0;
9418 +}
9419 +
9420 +/*
9421 + * Close the ethernet interface.
9422 + */
9423 +static int ks8695eth_close(struct net_device *dev)
9424 +{
9425 + /* Stop DMA */
9426 + ks8695eth_stop_rx(dev);
9427 + ks8695eth_stop_tx(dev);
9428 +
9429 + /* Disable interrupts */
9430 + ks8695eth_set_irq(dev, 0);
9431 +
9432 + netif_stop_queue(dev);
9433 + return 0;
9434 +}
9435 +
9436 +/*
9437 + * Return the current statistics.
9438 + */
9439 +static struct net_device_stats *ks8695eth_stats(struct net_device *dev)
9440 +{
9441 + return &dev->stats;
9442 +}
9443 +
9444 +/*
9445 + * Queue a packet for transmission in next TX DMA descriptor.
9446 + */
9447 +static int ks8695eth_xmit_frame(struct sk_buff *skb, struct net_device *dev)
9448 +{
9449 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9450 + int i;
9451 +
9452 + /* Packets are added to head of array */
9453 + i = lp->tx_head;
9454 +
9455 + /* Store packet information */
9456 + lp->txSkb[i].skb = skb;
9457 + lp->txSkb[i].length = skb->len;
9458 + lp->txSkb[i].dma = dma_map_single(lp->dev, skb->data, skb->len, DMA_TO_DEVICE);
9459 +
9460 + spin_lock_irq(&lp->tx_lock);
9461 +
9462 + /* Set Tx descriptor information */
9463 + lp->txdma[i].addr = lp->txSkb[i].dma;
9464 + lp->txdma[i].status = TDES_IC | TDES_FS | TDES_LS | (lp->txSkb[i].length & TDES_TBS);
9465 + lp->txdma[i].ownership = TDES_OWN;
9466 +
9467 + /* Start the DMA transmitter (if necessary) */
9468 + ks8695_write(dev, KS8695_WMDTSC, 0);
9469 +
9470 + lp->tx_head = (lp->tx_head + 1) % MAX_TX_DESC;
9471 + if (lp->tx_head == lp->tx_tail) /* no more descriptors */
9472 + netif_stop_queue(dev);
9473 +
9474 + spin_unlock_irq(&lp->tx_lock);
9475 +
9476 + dev->trans_start = jiffies;
9477 + return 0;
9478 +}
9479 +
9480 +/* ..................................................................... */
9481 +
9482 +/*
9483 + * The link state of the WAN port has changed.
9484 + * (Called from interrupt context)
9485 + */
9486 +static void ks8695eth_wan_link(struct net_device *dev)
9487 +{
9488 + unsigned long ctrl;
9489 +
9490 + ctrl = __raw_readl(KS8695_MISC_VA + KS8695_WMC);
9491 + if (ctrl & WMC_WLS) {
9492 + netif_carrier_on(dev);
9493 + printk(KERN_INFO "%s: Link is now %s-%s\n", dev->name,
9494 + (ctrl & WMC_WSS) ? "100" : "10",
9495 + (ctrl & WMC_WDS) ? "FullDuplex" : "HalfDuplex");
9496 + }
9497 + else {
9498 + netif_carrier_off(dev);
9499 + printk(KERN_INFO "%s: Link down.\n", dev->name);
9500 + }
9501 +}
9502 +
9503 +/* ..................................................................... */
9504 +
9505 +/*
9506 + * A frame has been received. Exteract from buffer descriptor and deliver to
9507 + * upper layers.
9508 + * (Called from interrupt context)
9509 + */
9510 +static void ks8695eth_rx_interrupt(struct net_device *dev)
9511 +{
9512 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9513 + struct sk_buff *skb;
9514 + unsigned long flags;
9515 + unsigned int pktlen;
9516 +
9517 + while (!(lp->rxdma[lp->rx_idx].status & RDES_OWN)) {
9518 + flags = lp->rxdma[lp->rx_idx].status;
9519 +
9520 + if ((flags & (RDES_FS | RDES_LS)) != (RDES_FS | RDES_LS)) {
9521 + printk(KERN_ERR "%s: Spanning packet detected\n", dev->name);
9522 + goto rx_complete;
9523 + }
9524 +
9525 + /* handle errors */
9526 + if (flags & (RDES_ES | RDES_RE)) {
9527 + dev->stats.rx_errors++;
9528 +
9529 + if (flags & RDES_TL) /* Frame too long */
9530 + dev->stats.rx_length_errors++;
9531 + else if (flags & RDES_RF) /* Runt frame */
9532 + dev->stats.rx_length_errors++;
9533 + else if (flags & RDES_CE) /* CRC error */
9534 + dev->stats.rx_crc_errors++;
9535 + else if (flags & RDES_RE) /* MII error */
9536 + dev->stats.rx_missed_errors++;
9537 + // TODO: If hardware checksumming, then check IP/TCP/UDP errors.
9538 +
9539 + goto rx_complete;
9540 + }
9541 +
9542 + pktlen = flags & RDES_FLEN;
9543 + pktlen = pktlen - 4; /* remove CRC */
9544 +
9545 + // OLD CALL: consistent_sync(lp->rxSkb[lp->rx_idx].skb->data, MAX_RXBUF_SIZE, DMA_FROM_DEVICE);
9546 + dma_sync_single_for_cpu(lp->dev, lp->rxSkb[lp->rx_idx].dma, MAX_RXBUF_SIZE, DMA_FROM_DEVICE);
9547 +
9548 + skb = dev_alloc_skb(pktlen+2); /* +2 to align IP header */
9549 + if (!skb) {
9550 + dev->stats.rx_dropped++;
9551 + printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
9552 + goto rx_complete;
9553 + }
9554 +
9555 + skb_reserve(skb, 2); /* align IP header */
9556 + memcpy(skb_put(skb, pktlen), lp->rxSkb[lp->rx_idx].skb->data, pktlen);
9557 +
9558 + skb->protocol = eth_type_trans(skb, dev);
9559 + netif_rx(skb);
9560 +
9561 + /* update statistics */
9562 + dev->stats.rx_packets++;
9563 + dev->stats.rx_bytes += pktlen;
9564 + if (flags & RDES_MF)
9565 + dev->stats.multicast++;
9566 + dev->last_rx = jiffies;
9567 +
9568 +rx_complete:
9569 + lp->rxdma[lp->rx_idx].status = RDES_OWN; /* reset ownership bit */
9570 +
9571 + lp->rx_idx = (lp->rx_idx + 1) % MAX_RX_DESC; /* next descriptor */
9572 + }
9573 +
9574 + /* restart DMA receiver incase it was suspended */
9575 + ks8695_write(dev, KS8695_WMDRSC, 0);
9576 +}
9577 +
9578 +/*
9579 + * A packet has been transmitted.
9580 + * (Called from interrupt context)
9581 + */
9582 +static void ks8695eth_tx_interrupt(struct net_device *dev)
9583 +{
9584 + struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9585 + int i;
9586 +
9587 + /* Packets are removed from tail of array */
9588 + i = lp->tx_tail;
9589 +
9590 + // TODO: Loop through multiple times?
9591 +
9592 + if (lp->txSkb[i].skb) {
9593 + /* update statistics */
9594 + dev->stats.tx_packets++;
9595 + dev->stats.tx_bytes += lp->txSkb[i].length;
9596 +
9597 + /* free packet */
9598 + dma_unmap_single(lp->dev, lp->txSkb[i].dma, lp->txSkb[i].length, DMA_TO_DEVICE);
9599 + dev_kfree_skb_irq(lp->txSkb[i].skb);
9600 + lp->txSkb[i].skb = NULL;
9601 +
9602 + /* Not necessary to clear descriptor since we still own it */
9603 + }
9604 +
9605 + lp->tx_tail = (lp->tx_tail + 1) % MAX_TX_DESC;
9606 +
9607 + netif_wake_queue(dev);
9608 +}
9609 +
9610 +/*
9611 + * MAC interrupt handler
9612 + */
9613 +static irqreturn_t ks8695eth_interrupt(int irq, void *dev_id)
9614 +{
9615 + struct net_device *dev = (struct net_device *) dev_id;
9616 +
9617 + switch (irq) {
9618 + case KS8695_IRQ_LAN_RX_STATUS:
9619 + case KS8695_IRQ_HPNA_RX_STATUS:
9620 + case KS8695_IRQ_WAN_RX_STATUS:
9621 + ks8695eth_rx_interrupt(dev);
9622 + return IRQ_HANDLED;
9623 +
9624 + case KS8695_IRQ_LAN_TX_STATUS:
9625 + case KS8695_IRQ_HPNA_TX_STATUS:
9626 + case KS8695_IRQ_WAN_TX_STATUS:
9627 + ks8695eth_tx_interrupt(dev);
9628 + return IRQ_HANDLED;
9629 +
9630 + case KS8695_IRQ_WAN_LINK:
9631 + ks8695eth_wan_link(dev);
9632 + return IRQ_HANDLED;
9633 +
9634 + default:
9635 + return IRQ_NONE;
9636 + }
9637 +}
9638 +
9639 +
9640 +/* ..................................................................... */
9641 +
9642 +/*
9643 + * Initialize the WAN hardware to known defaults.
9644 + */
9645 +static void __init ks8695eth_init_wan(void)
9646 +{
9647 + unsigned long ctrl;
9648 +
9649 + /* Support auto-negotiation */
9650 + ctrl = WMC_WANAP | WMC_WANA100F | WMC_WANA100H | WMC_WANA10F | WMC_WANA10H;
9651 +
9652 + /* LED0 = Activity , LED1 = Link */
9653 + ctrl |= (WLED0S_ACTIVITY | WLED1S_LINK);
9654 +
9655 + /* Restart Auto-negotiation */
9656 + ctrl |= WMC_WANR;
9657 +
9658 + __raw_writel(ctrl, KS8695_MISC_VA + KS8695_WMC);
9659 +
9660 + __raw_writel(0, KS8695_MISC_VA + KS8695_WPPM);
9661 + __raw_writel(0, KS8695_MISC_VA + KS8695_PPS);
9662 +}
9663 +
9664 +/*
9665 + * Initialize the LAN Switch hardware to known defaults.
9666 + */
9667 +static void __init ks8695eth_init_switch(void)
9668 +{
9669 + unsigned long ctrl;
9670 +
9671 + ctrl = 0x40819e00; /* default */
9672 +
9673 + /* LED0 = Speed LED1 = Link/Activity */
9674 + ctrl &= ~(SEC0_LLED1S | SEC0_LLED0S);
9675 + ctrl |= (LLED0S_LINK | LLED1S_LINK_ACTIVITY);
9676 +
9677 + /* Enable Switch */
9678 + ctrl |= SEC0_ENABLE;
9679 +
9680 + __raw_writel(ctrl, KS8695_SWITCH_VA + KS8695_SEC0);
9681 +
9682 + __raw_writel(0x9400100, KS8695_SWITCH_VA + KS8695_SEC1); /* reset defaults */
9683 +}
9684 +
9685 +static int ks8695eth_hook_irqs(struct platform_device *pdev, struct net_device *dev, unsigned long *irqset)
9686 +{
9687 + struct resource *res;
9688 + int i = 0, ret;
9689 +
9690 + while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, i))) {
9691 + set_irq_flags(res->start, IRQF_VALID | IRQF_NOAUTOEN);
9692 +
9693 + ret = request_irq(res->start, ks8695eth_interrupt, IRQF_DISABLED | IRQF_SHARED, res->name, dev);
9694 + if (ret) {
9695 + printk(KERN_ERR "%s: return_irq %u failed\n", dev->name, res->start);
9696 + return -EBUSY;
9697 + }
9698 +
9699 + *irqset |= (1 << res->start);
9700 +
9701 + // TODO: Can set different priorities for interrupts [0x BB AA FF].
9702 +
9703 + i++;
9704 + }
9705 +
9706 + return 0;
9707 +}
9708 +
9709 +static int __init ks8695eth_probe(struct platform_device *pdev)
9710 +{
9711 + struct net_device *dev;
9712 + struct ks8695eth_priv *lp;
9713 + struct resource *res;
9714 + int i = 0, ret, size;
9715 + DECLARE_MAC_BUF(mac);
9716 +
9717 + /* Create ethernet device */
9718 + dev = alloc_etherdev(sizeof(struct ks8695eth_priv));
9719 + if (!dev)
9720 + return -ENOMEM;
9721 +
9722 + /* Get I/O base address */
9723 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9724 + if (!res) {
9725 + free_netdev(dev);
9726 + return -ENODEV;
9727 + }
9728 + dev->base_addr = res->start;
9729 +
9730 + lp = (struct ks8695eth_priv *) dev->priv;
9731 +
9732 + /* Retreive MAC address before the MAC registers are reset */
9733 + get_mac_address(dev);
9734 +
9735 + /* Reset the hardware */
9736 + ks8695_write(dev, KS8695_WMDTXC, WMDTXC_WMTRST);
9737 + while (ks8695_read(dev, KS8695_WMDTXC) & WMDTXC_WMTRST) { barrier(); }
9738 +
9739 + /* Get IRQ's */
9740 + dev->irq = platform_get_irq(pdev, 0);
9741 + ret = ks8695eth_hook_irqs(pdev, dev, &lp->irqs);
9742 + if (ret) {
9743 + // Cleanup.
9744 + }
9745 +
9746 + /* Allocate DMA-able memory for Tx descriptor */
9747 + size = sizeof(struct tx_descriptor) * MAX_TX_DESC;
9748 + lp->txdma = dma_alloc_coherent(&pdev->dev, size, &lp->txdma_phys, GFP_KERNEL);
9749 + if (lp->txdma == NULL) {
9750 + // free IRQs
9751 + free_netdev(dev);
9752 + return -ENOMEM;
9753 + }
9754 + memset(lp->txdma, 0, size);
9755 + lp->tx_head = 0;
9756 + lp->tx_tail = 0;
9757 +
9758 + /* Allocate DMA-able memory for Rx descriptor */
9759 + size = sizeof(struct rx_descriptor) * MAX_RX_DESC;
9760 + lp->rxdma = dma_alloc_coherent(&pdev->dev, size, &lp->rxdma_phys, GFP_KERNEL);
9761 + if (lp->rxdma == NULL) {
9762 + // free IRQs
9763 + // Free TX descriptor memory.
9764 + free_netdev(dev);
9765 + return -ENOMEM;
9766 + }
9767 + memset(lp->rxdma, 0, size);
9768 + lp->rx_idx = 0;
9769 +
9770 + /* Allocate DMA-able memory for Rx Data */
9771 + for (i = 0; i < MAX_RX_DESC; i++) {
9772 + lp->rxSkb[i].skb = alloc_skb(MAX_RXBUF_SIZE, GFP_KERNEL);
9773 + if (lp->rxSkb[i].skb == NULL) {
9774 + // Cleanup
9775 + return -ENOMEM;
9776 + }
9777 + lp->rxSkb[i].length = MAX_RXBUF_SIZE;
9778 + lp->rxSkb[i].dma = dma_map_single(&pdev->dev, lp->rxSkb[i].skb->data, MAX_RXBUF_SIZE, DMA_FROM_DEVICE);
9779 + }
9780 +
9781 + spin_lock_init(&lp->tx_lock);
9782 +
9783 + platform_set_drvdata(pdev, dev);
9784 +
9785 + ether_setup(dev);
9786 + dev->open = ks8695eth_open;
9787 + dev->stop = ks8695eth_close;
9788 + dev->hard_start_xmit = ks8695eth_xmit_frame;
9789 + dev->get_stats = ks8695eth_stats;
9790 + dev->set_multicast_list = ks8695eth_set_multi;
9791 + dev->set_mac_address = ks8695eth_set_mac;
9792 + dev->ethtool_ops = &ks8695eth_ethtool_ops;
9793 +
9794 + SET_NETDEV_DEV(dev, &pdev->dev);
9795 + lp->dev = &pdev->dev;
9796 +
9797 + if (dev->base_addr == KS8695_WAN_VA)
9798 + ks8695eth_init_wan();
9799 + else if (dev->base_addr == KS8695_LAN_VA)
9800 + ks8695eth_init_switch();
9801 +
9802 + /* Register the network interface */
9803 + ret = register_netdev(dev);
9804 + if (ret) {
9805 + // free IRQs
9806 + free_netdev(dev);
9807 +// dma_free_coherent(&pdev->dev, sizeof(struct ks8695_tx_dma), lp->txdma, lp->txdma_phys);
9808 +// dma_free_coherent(&pdev->dev, sizeof(struct ks8695_rx_dma), lp->rxdma, lp->rxdma_phys);
9809 + return ret;
9810 + }
9811 +
9812 + printk(KERN_INFO "%s: KS8695 ethernet (%s)\n", dev->name, print_mac(mac, dev->dev_addr));
9813 +
9814 + return 0;
9815 +}
9816 +
9817 +static int __devexit ks8695eth_remove(struct platform_device *pdev)
9818 +{
9819 + struct net_device *dev = platform_get_drvdata(pdev);
9820 +// struct ks8695eth_priv *lp = (struct ks8695eth_priv *) dev->priv;
9821 +
9822 + unregister_netdev(dev);
9823 +
9824 + // Free IRQ
9825 +// dma_free_coherent(&pdev->dev, sizeof(struct ks8695_tx_dma), lp->txdma, lp->txdma_phys);
9826 +// dma_free_coherent(&pdev->dev, sizeof(struct ks8695_rx_dma), lp->rxdma, lp->rxdma_phys);
9827 +
9828 + platform_set_drvdata(pdev, NULL);
9829 + free_netdev(dev);
9830 + return 0;
9831 +}
9832 +
9833 +static struct platform_driver ks8695ether_driver = {
9834 + .probe = ks8695eth_probe,
9835 + .remove = __devexit_p(ks8695eth_remove),
9836 +// .suspend =
9837 +// .resume =
9838 + .driver = {
9839 + .name = DRV_NAME,
9840 + .owner = THIS_MODULE,
9841 + },
9842 +};
9843 +
9844 +
9845 +static int __init ks8695eth_init(void)
9846 +{
9847 + return platform_driver_register(&ks8695ether_driver);
9848 +}
9849 +
9850 +static void __exit ks8695eth_exit(void)
9851 +{
9852 + platform_driver_unregister(&ks8695ether_driver);
9853 +}
9854 +
9855 +module_init(ks8695eth_init);
9856 +module_exit(ks8695eth_exit);
9857 +
9858 +MODULE_LICENSE("GPL");
9859 +MODULE_DESCRIPTION("KS8695 Ethernet driver");
9860 +MODULE_AUTHOR("Andrew Victor");
9861 +MODULE_ALIAS("platform:" DRV_NAME);
9862 --- /dev/null
9863 +++ b/drivers/net/arm/ks8695_ether.h
9864 @@ -0,0 +1,92 @@
9865 +/*
9866 + * Ethernet driver for the Micrel/Kendin KS8695 (Centaur)
9867 + *
9868 + * (C) 2006 Andrew Victor
9869 + *
9870 + */
9871 +
9872 +#ifndef KS8695_ETHERNET
9873 +#define KS8695_ETHERNET
9874 +
9875 +/* .... Hardware Descriptors ................................................ */
9876 +
9877 +struct rx_descriptor {
9878 + unsigned long status;
9879 + unsigned long length;
9880 + unsigned long addr;
9881 + unsigned long next;
9882 +};
9883 +
9884 +#define RDES_OWN (1 << 31) /* Ownership */
9885 +#define RDES_FS (1 << 30) /* First Descriptor */
9886 +#define RDES_LS (1 << 29) /* Last Descriptor */
9887 +#define RDES_IPE (1 << 28) /* IP Checksum error */
9888 +#define RDES_TCPE (1 << 27) /* TCP Checksum error */
9889 +#define RDES_UDPE (1 << 26) /* UDP Checksum error */
9890 +#define RDES_ES (1 << 25) /* Error summary */
9891 +#define RDES_MF (1 << 24) /* Multicast Frame */
9892 +#define RDES_RE (1 << 19) /* MII Error reported */
9893 +#define RDES_TL (1 << 18) /* Frame too Long */
9894 +#define RDES_RF (1 << 17) /* Runt Frame */
9895 +#define RDES_CE (1 << 16) /* CRC error */
9896 +#define RDES_FT (1 << 15) /* Frame Type */
9897 +#define RDES_FLEN (0x7ff) /* Frame Length */
9898 +
9899 +#define RDES_RER (1 << 25) /* Receive End of Ring */
9900 +#define RDES_RBS (0x7ff) /* Receive Buffer Size */
9901 +
9902 +
9903 +struct tx_descriptor {
9904 + unsigned long ownership;
9905 + unsigned long status;
9906 + unsigned long addr;
9907 + unsigned long next;
9908 +};
9909 +
9910 +#define TDES_OWN (1 << 31) /* Ownership */
9911 +
9912 +#define TDES_IC (1 << 31) /* Interrupt on Completion */
9913 +#define TDES_FS (1 << 30) /* First Segment */
9914 +#define TDES_LS (1 << 29) /* Last Segment */
9915 +#define TDES_IPCKG (1 << 28) /* IP Checksum generate */
9916 +#define TDES_TCPCKG (1 << 27) /* TCP Checksum generate */
9917 +#define TDES_UDPCKG (1 << 26) /* UDP Checksum generate */
9918 +#define TDES_TER (1 << 25) /* Transmit End of Ring */
9919 +#define TDES_TBS (0x7ff) /* Transmit Buffer Size */
9920 +
9921 +
9922 +/* .... ..................................................................... */
9923 +
9924 +#define MAX_RX_DESC 16 /* number of receive descriptors */
9925 +#define MAX_TX_DESC 8 /* number of transmit descriptors */
9926 +#define MAX_RXBUF_SIZE 0x600 /* 1518 rounded-up */
9927 +
9928 +struct ks8695_buffer
9929 +{
9930 + struct sk_buff *skb;
9931 + dma_addr_t dma;
9932 + unsigned long length;
9933 +};
9934 +
9935 +
9936 +struct ks8695eth_priv
9937 +{
9938 + struct device *dev;
9939 + unsigned long irqs; /* IRQ bitset */
9940 +
9941 + /* Transmit */
9942 + struct tx_descriptor *txdma; /* Tx DMA descriptors */
9943 + dma_addr_t txdma_phys; /* TX DMA descriptors (phys address) */
9944 + unsigned int tx_head; /* descriptor index (add) */
9945 + unsigned int tx_tail; /* descriptor index (remove) */
9946 + spinlock_t tx_lock;
9947 + struct ks8695_buffer txSkb[MAX_TX_DESC]; /* packets being transmitted */
9948 +
9949 + /* Receive */
9950 + struct rx_descriptor *rxdma; /* Rx DMA descriptors */
9951 + dma_addr_t rxdma_phys; /* Rx DMA descriptors (phys address) */
9952 + unsigned int rx_idx; /* descriptor index */
9953 + struct ks8695_buffer rxSkb[MAX_RX_DESC];
9954 +};
9955 +
9956 +#endif
9957 --- a/drivers/rtc/Kconfig
9958 +++ b/drivers/rtc/Kconfig
9959 @@ -487,12 +487,12 @@
9960 this is powered by the backup power supply.
9961
9962 config RTC_DRV_AT91SAM9
9963 - tristate "AT91SAM9x"
9964 + tristate "AT91SAM9x or AT91CAP9"
9965 depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40)
9966 help
9967 - RTC driver for the Atmel AT91SAM9x internal RTT (Real Time Timer).
9968 - These timers are powered by the backup power supply (such as a
9969 - small coin cell battery), but do not need to be used as RTCs.
9970 + RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT (Real
9971 + Time Timer). These timers are powered by the backup power supply
9972 + (such as a small coin cell battery), but do not need to be used as RTCs.
9973
9974 (On AT91SAM9rl chips you probably want to use the dedicated RTC
9975 module and leave the RTT available for other uses.)
9976 --- a/drivers/rtc/rtc-at91rm9200.c
9977 +++ b/drivers/rtc/rtc-at91rm9200.c
9978 @@ -29,9 +29,6 @@
9979 #include <linux/completion.h>
9980
9981 #include <asm/uaccess.h>
9982 -#include <asm/rtc.h>
9983 -
9984 -#include <asm/mach/time.h>
9985
9986 #include <asm/arch/at91_rtc.h>
9987
9988 @@ -307,12 +304,6 @@
9989 return ret;
9990 }
9991
9992 - /* cpu init code should really have flagged this device as
9993 - * being wake-capable; if it didn't, do that here.
9994 - */
9995 - if (!device_can_wakeup(&pdev->dev))
9996 - device_init_wakeup(&pdev->dev, 1);
9997 -
9998 rtc = rtc_device_register(pdev->name, &pdev->dev,
9999 &at91_rtc_ops, THIS_MODULE);
10000 if (IS_ERR(rtc)) {
10001 --- a/drivers/rtc/rtc-at91sam9.c
10002 +++ b/drivers/rtc/rtc-at91sam9.c
10003 @@ -21,6 +21,7 @@
10004
10005 #include <asm/mach/time.h>
10006 #include <asm/arch/board.h>
10007 +#include <asm/arch/cpu.h>
10008 #include <asm/arch/at91_rtt.h>
10009
10010
10011 @@ -150,6 +151,9 @@
10012 return 0;
10013 }
10014
10015 +/*
10016 + * Read alarm time and date in RTC
10017 + */
10018 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
10019 {
10020 struct sam9_rtc *rtc = dev_get_drvdata(dev);
10021 @@ -176,6 +180,9 @@
10022 return 0;
10023 }
10024
10025 +/*
10026 + * Set alarm time and date in RTC
10027 + */
10028 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
10029 {
10030 struct sam9_rtc *rtc = dev_get_drvdata(dev);
10031 @@ -321,10 +328,6 @@
10032 if (!rtc)
10033 return -ENOMEM;
10034
10035 - /* platform setup code should have handled this; sigh */
10036 - if (!device_can_wakeup(&pdev->dev))
10037 - device_init_wakeup(&pdev->dev, 1);
10038 -
10039 platform_set_drvdata(pdev, rtc);
10040 rtc->rtt = (void __force __iomem *) (AT91_VA_BASE_SYS - AT91_BASE_SYS);
10041 rtc->rtt += r->start;
10042 --- a/drivers/spi/Kconfig
10043 +++ b/drivers/spi/Kconfig
10044 @@ -113,6 +113,15 @@
10045
10046 If unsure, say N.
10047
10048 +config SPI_AT91
10049 + tristate "AT91RM9200 Bitbang SPI Master"
10050 + depends on SPI_MASTER && ARCH_AT91RM9200 && !SPI_ATMEL && EXPERIMENTAL
10051 + select SPI_BITBANG
10052 + help
10053 + This is dumb PIO bitbanging driver for the Atmel AT91RM9200.
10054 + The SPI_ATMEL driver will be its replacement, using the native
10055 + SPI hardware and its DMA controller.
10056 +
10057 config SPI_IMX
10058 tristate "Freescale iMX SPI controller"
10059 depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL
10060 --- a/drivers/spi/Makefile
10061 +++ b/drivers/spi/Makefile
10062 @@ -29,6 +29,7 @@
10063 obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
10064 obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
10065 obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
10066 +obj-$(CONFIG_SPI_AT91) += spi_at91_bitbang.o
10067 # ... add above this line ...
10068
10069 # SPI protocol drivers (device/link on bus)
10070 --- /dev/null
10071 +++ b/drivers/spi/spi_at91_bitbang.c
10072 @@ -0,0 +1,208 @@
10073 +/*
10074 + * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION)
10075 + *
10076 + * Copyright (C) 2006 David Brownell
10077 + *
10078 + * This program is free software; you can redistribute it and/or modify
10079 + * it under the terms of the GNU General Public License as published by
10080 + * the Free Software Foundation; either version 2 of the License, or
10081 + * (at your option) any later version.
10082 + *
10083 + * This program is distributed in the hope that it will be useful,
10084 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10085 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10086 + * GNU General Public License for more details.
10087 + *
10088 + * You should have received a copy of the GNU General Public License
10089 + * along with this program; if not, write to the Free Software
10090 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
10091 + */
10092 +#include <linux/kernel.h>
10093 +#include <linux/init.h>
10094 +#include <linux/platform_device.h>
10095 +
10096 +#include <linux/spi/spi.h>
10097 +#include <linux/spi/spi_bitbang.h>
10098 +
10099 +#include <asm/arch/gpio.h>
10100 +
10101 +
10102 +/*
10103 + * FIXME this bitbanging version is just to help bootstrap systems until
10104 + * there's a native SPI+IRQ+DMA controller driver ... such a driver should
10105 + * be a drop-in replacement for this one, and much faster.
10106 + *
10107 + * remember:
10108 + *
10109 + * - other at91 parts (like at91sam9) have multiple controllers
10110 + * and different pin muxing; this version is at91rm9200 specfic.
10111 + *
10112 + * - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins.
10113 + *
10114 + * - rm9200 spi chipselects drop wrongly, so the native driver
10115 + * will need to use gpios much like this does.
10116 + *
10117 + * - real hardware only allows 8..16 bits per word, while this
10118 + * bitbanger allows 1..32 (incompatible superset).
10119 + *
10120 + * - this disregards clock parameters. with inlined gpio calls,
10121 + * gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster
10122 + * than using the subroutined veresion from txrx_word().
10123 + *
10124 + * - suspend/resume and <linux/clk.h> support is missing ...
10125 + */
10126 +
10127 +#define spi_miso_bit AT91_PIN_PA0
10128 +#define spi_mosi_bit AT91_PIN_PA1
10129 +#define spi_sck_bit AT91_PIN_PA2
10130 +
10131 +struct at91_spi {
10132 + struct spi_bitbang bitbang;
10133 + struct platform_device *pdev;
10134 +};
10135 +
10136 +/*----------------------------------------------------------------------*/
10137 +
10138 +static inline void setsck(struct spi_device *spi, int is_on)
10139 +{
10140 + at91_set_gpio_value(spi_sck_bit, is_on);
10141 +}
10142 +
10143 +static inline void setmosi(struct spi_device *spi, int is_on)
10144 +{
10145 + at91_set_gpio_value(spi_mosi_bit, is_on);
10146 +}
10147 +
10148 +static inline int getmiso(struct spi_device *spi)
10149 +{
10150 + return at91_get_gpio_value(spi_miso_bit);
10151 +}
10152 +
10153 +static void at91_spi_chipselect(struct spi_device *spi, int is_active)
10154 +{
10155 + unsigned long cs = (unsigned long) spi->controller_data;
10156 +
10157 + /* set default clock polarity */
10158 + if (is_active)
10159 + setsck(spi, spi->mode & SPI_CPOL);
10160 +
10161 + /* only support active-low (default) */
10162 + at91_set_gpio_value(cs, !is_active);
10163 +}
10164 +
10165 +/*
10166 + * NOTE: this is "as fast as we can"; it should be a function of
10167 + * the device clock ...
10168 + */
10169 +#define spidelay(X) do{} while(0)
10170 +
10171 +#define EXPAND_BITBANG_TXRX
10172 +#include <linux/spi/spi_bitbang.h>
10173 +
10174 +static u32 at91_spi_txrx_word_mode0(struct spi_device *spi,
10175 + unsigned nsecs, u32 word, u8 bits)
10176 +{
10177 + return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8);
10178 +}
10179 +
10180 +static u32 at91_spi_txrx_word_mode1(struct spi_device *spi,
10181 + unsigned nsecs, u32 word, u8 bits)
10182 +{
10183 + return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8);
10184 +}
10185 +
10186 +static u32 at91_spi_txrx_word_mode2(struct spi_device *spi,
10187 + unsigned nsecs, u32 word, u8 bits)
10188 +{
10189 + return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8);
10190 +}
10191 +
10192 +static u32 at91_spi_txrx_word_mode3(struct spi_device *spi,
10193 + unsigned nsecs, u32 word, u8 bits)
10194 +{
10195 + return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8);
10196 +}
10197 +
10198 +/*----------------------------------------------------------------------*/
10199 +
10200 +static int __init at91_spi_probe(struct platform_device *pdev)
10201 +{
10202 + int status;
10203 + struct spi_master *master;
10204 + struct at91_spi *at91_spi;
10205 +
10206 + if (pdev->id != 0) /* SPI0 bus */
10207 + return -EINVAL;
10208 +
10209 + master = spi_alloc_master(&pdev->dev, sizeof *at91_spi);
10210 + if (!master)
10211 + return -ENOMEM;
10212 +
10213 + at91_spi = spi_master_get_devdata(master);
10214 + at91_spi->pdev = pdev;
10215 + platform_set_drvdata(pdev, at91_spi);
10216 +
10217 + /* SPI and bitbang hookup */
10218 + master->bus_num = 0;
10219 + master->num_chipselect = 4;
10220 +
10221 + at91_spi->bitbang.master = spi_master_get(master);
10222 + at91_spi->bitbang.chipselect = at91_spi_chipselect;
10223 + at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0;
10224 + at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1;
10225 + at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2;
10226 + at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3;
10227 +
10228 + status = spi_bitbang_start(&at91_spi->bitbang);
10229 + if (status < 0)
10230 + (void) spi_master_put(at91_spi->bitbang.master);
10231 +
10232 + return status;
10233 +}
10234 +
10235 +static int __exit at91_spi_remove(struct platform_device *pdev)
10236 +{
10237 + struct at91_spi *at91_spi = platform_get_drvdata(pdev);
10238 + int status;
10239 +
10240 + /* stop() unregisters child devices too */
10241 + status = spi_bitbang_stop(&at91_spi->bitbang);
10242 + (void) spi_master_put(at91_spi->bitbang.master);
10243 +
10244 + platform_set_drvdata(pdev, NULL);
10245 + return status;
10246 +}
10247 +
10248 +static struct platform_driver at91_spi_driver = {
10249 + .probe = at91_spi_probe,
10250 + .remove = __exit_p(at91_spi_remove),
10251 + .driver = {
10252 + .name = "at91_spi",
10253 + .owner = THIS_MODULE,
10254 + },
10255 +};
10256 +
10257 +static int __init at91_spi_init(void)
10258 +{
10259 + at91_set_gpio_output(spi_sck_bit, 0);
10260 + at91_set_gpio_output(spi_mosi_bit, 0);
10261 + at91_set_gpio_input(spi_miso_bit, 1 /* pullup */);
10262 +
10263 + /* register driver */
10264 + return platform_driver_register(&at91_spi_driver);
10265 +}
10266 +
10267 +static void __exit at91_spi_exit(void)
10268 +{
10269 + platform_driver_unregister(&at91_spi_driver);
10270 +}
10271 +
10272 +device_initcall(at91_spi_init);
10273 +module_exit(at91_spi_exit);
10274 +
10275 +MODULE_ALIAS("at91_spi.0");
10276 +
10277 +MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)");
10278 +MODULE_AUTHOR("David Brownell");
10279 +MODULE_LICENSE("GPL");
10280 +MODULE_ALIAS("platform:at91_spi");
10281 --- a/drivers/usb/gadget/Kconfig
10282 +++ b/drivers/usb/gadget/Kconfig
10283 @@ -118,10 +118,10 @@
10284 config USB_GADGET_ATMEL_USBA
10285 boolean "Atmel USBA"
10286 select USB_GADGET_DUALSPEED
10287 - depends on AVR32
10288 + depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL
10289 help
10290 USBA is the integrated high-speed USB Device controller on
10291 - the AT32AP700x processors from Atmel.
10292 + the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
10293
10294 config USB_ATMEL_USBA
10295 tristate
10296 --- a/drivers/usb/gadget/at91_udc.c
10297 +++ b/drivers/usb/gadget/at91_udc.c
10298 @@ -1827,7 +1827,7 @@
10299 */
10300 if ((!udc->suspended && udc->addr)
10301 || !wake
10302 - || at91_suspend_entering_slow_clock()) {
10303 + || clk_must_disable(udc->fclk)) {
10304 pullup(udc, 0);
10305 wake = 0;
10306 } else
10307 --- a/drivers/usb/gadget/atmel_usba_udc.c
10308 +++ b/drivers/usb/gadget/atmel_usba_udc.c
10309 @@ -18,6 +18,7 @@
10310 #include <linux/platform_device.h>
10311 #include <linux/usb/ch9.h>
10312 #include <linux/usb/gadget.h>
10313 +#include <linux/usb/atmel_usba_udc.h>
10314 #include <linux/delay.h>
10315
10316 #include <asm/gpio.h>
10317 @@ -27,6 +28,7 @@
10318
10319
10320 static struct usba_udc the_udc;
10321 +static struct usba_ep *usba_ep;
10322
10323 #ifdef CONFIG_USB_GADGET_DEBUG_FS
10324 #include <linux/debugfs.h>
10325 @@ -324,53 +326,6 @@
10326 return 1;
10327 }
10328
10329 -static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
10330 -{
10331 - unsigned long tmp;
10332 -
10333 - DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
10334 - for (; len > 0; len -= 4, buf += 4, fifo += 4) {
10335 - tmp = *(unsigned long *)buf;
10336 - if (len >= 4) {
10337 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
10338 - __raw_writel(tmp, fifo);
10339 - } else {
10340 - do {
10341 - DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
10342 - __raw_writeb(tmp >> 24, fifo);
10343 - fifo++;
10344 - tmp <<= 8;
10345 - } while (--len);
10346 - break;
10347 - }
10348 - }
10349 -}
10350 -
10351 -static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
10352 -{
10353 - union {
10354 - unsigned long *w;
10355 - unsigned char *b;
10356 - } p;
10357 - unsigned long tmp;
10358 -
10359 - DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
10360 - for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
10361 - if (len >= 4) {
10362 - tmp = __raw_readl(fifo);
10363 - *p.w = tmp;
10364 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
10365 - } else {
10366 - do {
10367 - tmp = __raw_readb(fifo);
10368 - *p.b = tmp;
10369 - DBG(DBG_FIFO, " -> %02lx\n", tmp);
10370 - fifo++, p.b++;
10371 - } while (--len);
10372 - }
10373 - }
10374 -}
10375 -
10376 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
10377 {
10378 unsigned int transaction_len;
10379 @@ -387,7 +342,7 @@
10380 ep->ep.name, req, transaction_len,
10381 req->last_transaction ? ", done" : "");
10382
10383 - copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
10384 + memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
10385 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
10386 req->req.actual += transaction_len;
10387 }
10388 @@ -476,7 +431,7 @@
10389 bytecount = req->req.length - req->req.actual;
10390 }
10391
10392 - copy_from_fifo(req->req.buf + req->req.actual,
10393 + memcpy_fromio(req->req.buf + req->req.actual,
10394 ep->fifo, bytecount);
10395 req->req.actual += bytecount;
10396
10397 @@ -1029,33 +984,6 @@
10398 .set_selfpowered = usba_udc_set_selfpowered,
10399 };
10400
10401 -#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
10402 -{ \
10403 - .ep = { \
10404 - .ops = &usba_ep_ops, \
10405 - .name = nam, \
10406 - .maxpacket = maxpkt, \
10407 - }, \
10408 - .udc = &the_udc, \
10409 - .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
10410 - .fifo_size = maxpkt, \
10411 - .nr_banks = maxbk, \
10412 - .index = idx, \
10413 - .can_dma = dma, \
10414 - .can_isoc = isoc, \
10415 -}
10416 -
10417 -static struct usba_ep usba_ep[] = {
10418 - EP("ep0", 0, 64, 1, 0, 0),
10419 - EP("ep1in-bulk", 1, 512, 2, 1, 1),
10420 - EP("ep2out-bulk", 2, 512, 2, 1, 1),
10421 - EP("ep3in-int", 3, 64, 3, 1, 0),
10422 - EP("ep4out-int", 4, 64, 3, 1, 0),
10423 - EP("ep5in-iso", 5, 1024, 3, 1, 1),
10424 - EP("ep6out-iso", 6, 1024, 3, 1, 1),
10425 -};
10426 -#undef EP
10427 -
10428 static struct usb_endpoint_descriptor usba_ep0_desc = {
10429 .bLength = USB_DT_ENDPOINT_SIZE,
10430 .bDescriptorType = USB_DT_ENDPOINT,
10431 @@ -1074,7 +1002,6 @@
10432 static struct usba_udc the_udc = {
10433 .gadget = {
10434 .ops = &usba_udc_ops,
10435 - .ep0 = &usba_ep[0].ep,
10436 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
10437 .is_dualspeed = 1,
10438 .name = "atmel_usba_udc",
10439 @@ -1231,7 +1158,7 @@
10440 } else {
10441 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
10442 usba_writel(udc, TST, USBA_TST_PKT_MODE);
10443 - copy_to_fifo(ep->fifo, test_packet_buffer,
10444 + memcpy_toio(ep->fifo, test_packet_buffer,
10445 sizeof(test_packet_buffer));
10446 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
10447 dev_info(dev, "Entering Test_Packet mode...\n");
10448 @@ -1530,13 +1457,13 @@
10449 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
10450 if (pkt_len != sizeof(crq)) {
10451 pr_warning("udc: Invalid packet length %u "
10452 - "(expected %lu)\n", pkt_len, sizeof(crq));
10453 + "(expected %zu)\n", pkt_len, sizeof(crq));
10454 set_protocol_stall(udc, ep);
10455 return;
10456 }
10457
10458 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
10459 - copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
10460 + memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
10461
10462 /* Free up one bank in the FIFO so that we can
10463 * generate or receive a reply right away. */
10464 @@ -1908,7 +1835,7 @@
10465
10466 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
10467 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
10468 - if (!regs || !fifo)
10469 + if (!regs || !fifo || !pdata)
10470 return -ENXIO;
10471
10472 irq = platform_get_irq(pdev, 0);
10473 @@ -1956,16 +1883,44 @@
10474 usba_writel(udc, CTRL, 0);
10475 clk_disable(pclk);
10476
10477 + usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
10478 + GFP_KERNEL);
10479 + if (!usba_ep)
10480 + goto err_alloc_ep;
10481 +
10482 + the_udc.gadget.ep0 = &usba_ep[0].ep;
10483 +
10484 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
10485 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
10486 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
10487 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
10488 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
10489 + usba_ep[0].ep.ops = &usba_ep_ops;
10490 + usba_ep[0].ep.name = pdata->ep[0].name;
10491 + usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
10492 + usba_ep[0].udc = &the_udc;
10493 + INIT_LIST_HEAD(&usba_ep[0].queue);
10494 + usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
10495 + usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
10496 + usba_ep[0].index = pdata->ep[0].index;
10497 + usba_ep[0].can_dma = pdata->ep[0].can_dma;
10498 + usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
10499 +
10500 + for (i = 1; i < pdata->num_ep; i++) {
10501 struct usba_ep *ep = &usba_ep[i];
10502
10503 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
10504 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
10505 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
10506 + ep->ep.ops = &usba_ep_ops;
10507 + ep->ep.name = pdata->ep[i].name;
10508 + ep->ep.maxpacket = pdata->ep[i].fifo_size;
10509 + ep->udc = &the_udc;
10510 + INIT_LIST_HEAD(&ep->queue);
10511 + ep->fifo_size = pdata->ep[i].fifo_size;
10512 + ep->nr_banks = pdata->ep[i].nr_banks;
10513 + ep->index = pdata->ep[i].index;
10514 + ep->can_dma = pdata->ep[i].can_dma;
10515 + ep->can_isoc = pdata->ep[i].can_isoc;
10516
10517 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
10518 }
10519 @@ -1984,7 +1939,7 @@
10520 goto err_device_add;
10521 }
10522
10523 - if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
10524 + if (pdata->vbus_pin >= 0) {
10525 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
10526 udc->vbus_pin = pdata->vbus_pin;
10527
10528 @@ -2004,7 +1959,7 @@
10529 }
10530
10531 usba_init_debugfs(udc);
10532 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
10533 + for (i = 1; i < pdata->num_ep; i++)
10534 usba_ep_init_debugfs(udc, &usba_ep[i]);
10535
10536 return 0;
10537 @@ -2012,6 +1967,8 @@
10538 err_device_add:
10539 free_irq(irq, udc);
10540 err_request_irq:
10541 + kfree(usba_ep);
10542 +err_alloc_ep:
10543 iounmap(udc->fifo);
10544 err_map_fifo:
10545 iounmap(udc->regs);
10546 @@ -2029,10 +1986,11 @@
10547 {
10548 struct usba_udc *udc;
10549 int i;
10550 + struct usba_platform_data *pdata = pdev->dev.platform_data;
10551
10552 udc = platform_get_drvdata(pdev);
10553
10554 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
10555 + for (i = 1; i < pdata->num_ep; i++)
10556 usba_ep_cleanup_debugfs(&usba_ep[i]);
10557 usba_cleanup_debugfs(udc);
10558
10559 --- a/drivers/usb/host/ohci-at91.c
10560 +++ b/drivers/usb/host/ohci-at91.c
10561 @@ -330,7 +330,7 @@
10562 *
10563 * REVISIT: some boards will be able to turn VBUS off...
10564 */
10565 - if (at91_suspend_entering_slow_clock()) {
10566 + if (clk_must_disable(fclk)) {
10567 ohci_usb_reset (ohci);
10568 at91_stop_clock();
10569 }
10570 --- a/drivers/video/Kconfig
10571 +++ b/drivers/video/Kconfig
10572 @@ -889,6 +889,17 @@
10573 framebuffer. Product specs at
10574 <http://www.erd.epson.com/vdc/html/products.htm>.
10575
10576 +config FB_S1D15605
10577 + tristate "Epson S1D15605 framebuffer support"
10578 + depends on FB
10579 + default m if MACH_KB9200
10580 + select FB_CFB_FILLRECT
10581 + select FB_CFB_COPYAREA
10582 + select FB_CFB_IMAGEBLIT
10583 + help
10584 + Build in support for the S1D15605 Epson Research 128x64
10585 + LCD controller as a framebuffer.
10586 +
10587 config FB_S1D13XXX
10588 tristate "Epson S1D13XXX framebuffer support"
10589 depends on FB
10590 --- a/drivers/video/Makefile
10591 +++ b/drivers/video/Makefile
10592 @@ -87,7 +87,8 @@
10593 obj-$(CONFIG_FB_SA1100) += sa1100fb.o
10594 obj-$(CONFIG_FB_HIT) += hitfb.o
10595 obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o
10596 -obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o
10597 +obj-$(CONFIG_FB_S1D15605) += s1d15605fb.o
10598 +obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o
10599 obj-$(CONFIG_FB_PVR2) += pvr2fb.o
10600 obj-$(CONFIG_FB_VOODOO1) += sstfb.o
10601 obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o
10602 --- a/drivers/video/atmel_lcdfb.c
10603 +++ b/drivers/video/atmel_lcdfb.c
10604 @@ -31,7 +31,7 @@
10605 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
10606 #define ATMEL_LCDC_DMA_BURST_LEN 8
10607
10608 -#if defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
10609 +#if defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9) || defined(CONFIG_ARCH_AT91SAM9RL)
10610 #define ATMEL_LCDC_FIFO_SIZE 2048
10611 #else
10612 #define ATMEL_LCDC_FIFO_SIZE 512
10613 @@ -903,11 +903,45 @@
10614 return 0;
10615 }
10616
10617 -static struct platform_driver atmel_lcdfb_driver = {
10618 - .remove = __exit_p(atmel_lcdfb_remove),
10619 +#ifdef CONFIG_PM
10620 +
10621 +static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
10622 +{
10623 + struct fb_info *info = platform_get_drvdata(pdev);
10624 + struct atmel_lcdfb_info *sinfo = info->par;
10625 +
10626 + sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
10627 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
10628 + if (sinfo->atmel_lcdfb_power_control)
10629 + sinfo->atmel_lcdfb_power_control(0);
10630 + atmel_lcdfb_stop_clock(sinfo);
10631
10632 -// FIXME need suspend, resume
10633 + return 0;
10634 +}
10635 +
10636 +static int atmel_lcdfb_resume(struct platform_device *pdev)
10637 +{
10638 + struct fb_info *info = platform_get_drvdata(pdev);
10639 + struct atmel_lcdfb_info *sinfo = info->par;
10640
10641 + atmel_lcdfb_start_clock(sinfo);
10642 + if (sinfo->atmel_lcdfb_power_control)
10643 + sinfo->atmel_lcdfb_power_control(1);
10644 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
10645 +
10646 + return 0;
10647 +}
10648 +
10649 +#else
10650 +#define atmel_lcdfb_suspend NULL
10651 +#define atmel_lcdfb_resume NULL
10652 +#endif
10653 +
10654 +
10655 +static struct platform_driver atmel_lcdfb_driver = {
10656 + .remove = __exit_p(atmel_lcdfb_remove),
10657 + .suspend = atmel_lcdfb_suspend,
10658 + .resume = atmel_lcdfb_resume,
10659 .driver = {
10660 .name = "atmel_lcdfb",
10661 .owner = THIS_MODULE,
10662 --- a/drivers/video/backlight/Kconfig
10663 +++ b/drivers/video/backlight/Kconfig
10664 @@ -112,3 +112,11 @@
10665 help
10666 If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
10667 backlight driver.
10668 +
10669 +config BACKLIGHT_KB920x
10670 + tristate "KwikByte KB9202 Backlight Driver"
10671 + depends on BACKLIGHT_CLASS_DEVICE && MACH_KB9200
10672 + default y
10673 + help
10674 + If you have a KwikByte KB9202 board, say Y to enable the
10675 + backlight driver.
10676 --- a/drivers/video/backlight/Makefile
10677 +++ b/drivers/video/backlight/Makefile
10678 @@ -10,3 +10,4 @@
10679 obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
10680 obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
10681 obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
10682 +obj-$(CONFIG_BACKLIGHT_KB920x) += kb920x_bl.o
10683 --- /dev/null
10684 +++ b/drivers/video/backlight/kb920x_bl.c
10685 @@ -0,0 +1,164 @@
10686 +/*
10687 + * Backlight Driver for KB9202
10688 + *
10689 + * Copyright (c) 2006 KwikByte
10690 + *
10691 + * Based on Sharp's Corgi Backlight Driver
10692 + *
10693 + * This file is subject to the terms and conditions of the GNU General Public
10694 + * License. See the file "COPYING" in the main directory of this archive
10695 + * for more details.
10696 + */
10697 +
10698 +#include <linux/module.h>
10699 +#include <linux/kernel.h>
10700 +#include <linux/init.h>
10701 +#include <linux/platform_device.h>
10702 +#include <linux/spinlock.h>
10703 +#include <linux/fb.h>
10704 +#include <linux/backlight.h>
10705 +
10706 +#include <asm/arch/gpio.h>
10707 +
10708 +/* The backlight is on(1)/off(0) */
10709 +#define KB9202_DEFAULT_INTENSITY 1
10710 +#define KB9202_MAX_INTENSITY 1
10711 +
10712 +static int kb9202bl_suspended;
10713 +static int current_intensity = 0;
10714 +static DEFINE_SPINLOCK(bl_lock);
10715 +
10716 +static int kb9202bl_set_intensity(struct backlight_device *bd)
10717 +{
10718 + unsigned long flags;
10719 + int intensity = bd->props.brightness;
10720 +
10721 + if (bd->props.power != FB_BLANK_UNBLANK)
10722 + intensity = 0;
10723 + if (bd->props.fb_blank != FB_BLANK_UNBLANK)
10724 + intensity = 0;
10725 + if (kb9202bl_suspended)
10726 + intensity = 0;
10727 +
10728 + if ((!current_intensity) && (bd->props.power == FB_BLANK_UNBLANK))
10729 + intensity = 1;
10730 +
10731 + spin_lock_irqsave(&bl_lock, flags);
10732 + if (intensity)
10733 + gpio_set_value(AT91_PIN_PC23, 1);
10734 + else
10735 + gpio_set_value(AT91_PIN_PC23, 0);
10736 + spin_unlock_irqrestore(&bl_lock, flags);
10737 +
10738 + current_intensity = intensity;
10739 +
10740 + return 0;
10741 +}
10742 +
10743 +static int kb9202bl_get_intensity(struct backlight_device *bd)
10744 +{
10745 + return current_intensity;
10746 +}
10747 +
10748 +static struct backlight_ops kb9202bl_ops = {
10749 + .get_brightness = kb9202bl_get_intensity,
10750 + .update_status = kb9202bl_set_intensity,
10751 +};
10752 +
10753 +static int __init kb9202bl_probe(struct platform_device *pdev)
10754 +{
10755 + struct backlight_device *bd;
10756 +
10757 + bd = backlight_device_register ("kb9202-bl", &pdev->dev, NULL, &kb9202bl_ops);
10758 + if (IS_ERR(bd))
10759 + return PTR_ERR(bd);
10760 +
10761 + platform_set_drvdata(pdev, bd);
10762 +
10763 + bd->props.max_brightness = KB9202_MAX_INTENSITY;
10764 + bd->props.brightness = KB9202_DEFAULT_INTENSITY;
10765 + (void) kb9202bl_set_intensity(bd);
10766 +
10767 + return 0;
10768 +}
10769 +
10770 +static int kb9202bl_remove(struct platform_device *pdev)
10771 +{
10772 + struct backlight_device *bd = platform_get_drvdata(pdev);
10773 +
10774 + bd->props.brightness = 0;
10775 + bd->props.power = 0;
10776 + (void) kb9202bl_set_intensity(bd);
10777 +
10778 + backlight_device_unregister(bd);
10779 +
10780 + return 0;
10781 +}
10782 +
10783 +#ifdef CONFIG_PM
10784 +static int kb9202bl_suspend(struct platform_device *pdev, pm_message_t state)
10785 +{
10786 + struct backlight_device *bd = platform_get_drvdata(pdev);
10787 +
10788 + kb9202bl_suspended = 1;
10789 + (void) kb9202bl_set_intensity(bd);
10790 + return 0;
10791 +}
10792 +
10793 +static int kb9202bl_resume(struct platform_device *pdev)
10794 +{
10795 + struct backlight_device *bd = platform_get_drvdata(pdev);
10796 +
10797 + kb9202bl_suspended = 0;
10798 + (void) kb9202bl_set_intensity(bd);
10799 + return 0;
10800 +}
10801 +#else
10802 +#define kb9202bl_suspend NULL
10803 +#define kb9202bl_resume NULL
10804 +#endif
10805 +
10806 +static struct platform_driver kb9202bl_driver = {
10807 + .probe = kb9202bl_probe,
10808 + .remove = kb9202bl_remove,
10809 + .suspend = kb9202bl_suspend,
10810 + .resume = kb9202bl_resume,
10811 + .driver = {
10812 + .name = "kb9202-bl",
10813 + .owner = THIS_MODULE,
10814 + },
10815 +};
10816 +
10817 +static struct platform_device *kb9202bl_device;
10818 +
10819 +static int __init kb9202bl_init(void)
10820 +{
10821 + int ret;
10822 +
10823 + ret = platform_driver_register(&kb9202bl_driver);
10824 + if (!ret) {
10825 + kb9202bl_device = platform_device_alloc("kb9202-bl", -1);
10826 + if (!kb9202bl_device)
10827 + return -ENOMEM;
10828 +
10829 + ret = platform_device_add(kb9202bl_device);
10830 + if (ret) {
10831 + platform_device_put(kb9202bl_device);
10832 + platform_driver_unregister(&kb9202bl_driver);
10833 + }
10834 + }
10835 + return ret;
10836 +}
10837 +
10838 +static void __exit kb9202bl_exit(void)
10839 +{
10840 + platform_device_unregister(kb9202bl_device);
10841 + platform_driver_unregister(&kb9202bl_driver);
10842 +}
10843 +
10844 +module_init(kb9202bl_init);
10845 +module_exit(kb9202bl_exit);
10846 +
10847 +MODULE_AUTHOR("KwikByte <kb9200_dev@kwikbyte.com>");
10848 +MODULE_DESCRIPTION("KB9202 Backlight Driver");
10849 +MODULE_LICENSE("GPL");
10850 --- /dev/null
10851 +++ b/drivers/video/s1d15605fb.c
10852 @@ -0,0 +1,655 @@
10853 +/*
10854 + * drivers/video/s1d15605.c
10855 + *
10856 + * Adapted from several sources including:
10857 + * 1) Driver for AT91 LCD Controller
10858 + * Copyright (C) 2006 Atmel
10859 + *
10860 + * 2) Copyright (C) 2005 S. Kevin Hester
10861 + *
10862 + * This file is subject to the terms and conditions of the GNU General Public
10863 + * License. See the file COPYING in the main directory of this archive for
10864 + * more details.
10865 + *
10866 + * This is a basic framebuffer driver for the Optrex F-51320 128x64 mono LCD
10867 + * display. This display uses a clone of the common Epson SED 1531 display
10868 + * controller.
10869 + *
10870 + * I've heavily borrowed code from the vfb.c driver.
10871 + *
10872 + * This program is free software; you can redistribute it and/or modify
10873 + * it under the terms of the GNU General Public License as published by
10874 + * the Free Software Foundation; either version 2 of the License, or
10875 + * (at your option) any later version.
10876 + *
10877 + * This program is distributed in the hope that it will be useful,
10878 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10879 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10880 + * GNU General Public License for more details.
10881 + *
10882 + * You should have received a copy of the GNU General Public License
10883 + * along with this program; if not, write to the Free Software
10884 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10885 + */
10886 +
10887 +#ifdef DEBUG
10888 +#define MSG(string, args...) printk("s1d15605fb:" string, ##args)
10889 +#else
10890 +#define MSG(string, args...)
10891 +#endif
10892 +
10893 +#include <linux/kernel.h>
10894 +#include <linux/platform_device.h>
10895 +#include <linux/dma-mapping.h>
10896 +#include <linux/interrupt.h>
10897 +#include <linux/clk.h>
10898 +#include <linux/fb.h>
10899 +#include <linux/init.h>
10900 +#include <linux/delay.h>
10901 +
10902 +#include <asm/uaccess.h>
10903 +
10904 +#include <asm/arch/board.h>
10905 +#include <asm/arch/gpio.h>
10906 +
10907 +#ifdef CONFIG_PMAC_BACKLIGHT
10908 +#include <asm/backlight.h>
10909 +#endif
10910 +
10911 +#define VIDEOWIDTH 128
10912 +#define VIDEOHEIGHT 64
10913 +#define VIDEODEPTH 1 /* bits/pixel */
10914 +#define VIDEOWIDTH_BYTES ((VIDEOWIDTH * VIDEODEPTH) / 8)
10915 +
10916 +/* The number of bytes that actually go to the device */
10917 +#define ACTUALVIDEOMEMSIZE (VIDEOWIDTH_BYTES * VIDEOHEIGHT)
10918 +#define VIDEOMEMSIZE PAGE_SIZE
10919 +
10920 +static struct fb_var_screeninfo s1d15605_default __initdata = {
10921 + .xres = VIDEOWIDTH,
10922 + .yres = VIDEOHEIGHT,
10923 + .xres_virtual = VIDEOWIDTH,
10924 + .yres_virtual = VIDEOHEIGHT,
10925 + .bits_per_pixel = VIDEODEPTH,
10926 + .red = { 0, 1, 0 },
10927 + .green = { 0, 1, 0 },
10928 + .blue = { 0, 1, 0 },
10929 + .activate = FB_ACTIVATE_NOW,
10930 + .pixclock = 20000,
10931 + .vmode = FB_VMODE_NONINTERLACED,
10932 +};
10933 +
10934 +static struct fb_fix_screeninfo s1d15605_fix __initdata = {
10935 + .id = "s1d15605",
10936 + .type = FB_TYPE_PACKED_PIXELS,
10937 + .visual = FB_VISUAL_MONO10,
10938 + .xpanstep = 0,
10939 + .ypanstep = 0,
10940 + .ywrapstep = 0,
10941 + .accel = FB_ACCEL_NONE,
10942 +};
10943 +
10944 +struct s1d15605fb_info {
10945 + struct fb_info *info;
10946 + char *mmio;
10947 + unsigned long reset_pin;
10948 + struct platform_device *pdev;
10949 +};
10950 +
10951 +/*
10952 + * LCD device interface
10953 + */
10954 +#define RESET_DISPLAY 0xE2
10955 +#define LCD_BIAS_1_9 0xA2
10956 +#define ADC_SELECT_REVERSE 0xA1
10957 +#define COMMON_OUTPUT_NORMAL 0xC0
10958 +#define V5_RESISTOR_RATIO 0x26
10959 +#define ELECTRONIC_VOLUME_SET 0x81
10960 +#define ELECTRONIC_VOLUME_INIT 0x20
10961 +#define POWER_CONTROL_SET 0x28
10962 +#define VOLTAGE_REGULATOR 0x02
10963 +#define VOLTAGE_FOLLOWER 0x01
10964 +#define BOOSTER_CIRCUIT 0x04
10965 +#define DISPLAY_ON 0xAF
10966 +#define START_LINE_SET 0x40
10967 +#define PAGE_ADDRESS_SET 0xB0
10968 +#define COLUMN_ADDRESS_HIGH 0x10
10969 +#define COLUMN_ADDRESS_LOW 0x00
10970 +#define RESISTOR_RATIO_START 0x20
10971 +
10972 +#define NUM_OF_PAGES 8
10973 +#define NUM_OF_COLUMNS 128
10974 +
10975 +#define WRITE_COMMAND(x) __raw_writeb((x), (sinfo)->mmio)
10976 +#define READ_COMMAND __raw_readb((sinfo)->mmio)
10977 +#define WRITE_DATA(x) __raw_writeb((x), (sinfo)->mmio + (0x10000))
10978 +#define READ_DATA __raw_readb((sinfo)->mmio + (0x10000))
10979 +
10980 +
10981 +/*
10982 + * s1d15605fb_resize_framebuffer
10983 + *
10984 + * Free allocated space if different. Allocate on new of changed.
10985 + * Returns -ENOMEM if the new framebuffer can not be allocated,
10986 + * zero on success.
10987 + */
10988 +static int s1d15605fb_resize_framebuffer(struct s1d15605fb_info *sinfo)
10989 +{
10990 + struct fb_info *info = sinfo->info;
10991 + struct fb_fix_screeninfo *fix = &info->fix;
10992 + struct fb_var_screeninfo *var = &info->var;
10993 + unsigned int new_size;
10994 + void *new_vaddr;
10995 +
10996 + new_size = ((var->xres_virtual * var->yres_virtual * var->bits_per_pixel) / 8);
10997 +
10998 + MSG("%s: x (%d) y (%d) bpp (%d): new size 0x%08x\n", __FUNCTION__,
10999 + var->xres_virtual, var->yres_virtual, var->bits_per_pixel, new_size);
11000 +
11001 + if (new_size == fix->smem_len)
11002 + return 0;
11003 +
11004 + if (fix->smem_len) {
11005 + kfree(info->screen_base);
11006 + }
11007 +
11008 + new_vaddr = kmalloc(new_size, GFP_KERNEL);
11009 +
11010 + if (!new_vaddr) {
11011 + fix->smem_len = 0;
11012 + return -ENOMEM;
11013 + }
11014 +
11015 + info->screen_base = new_vaddr;
11016 + fix->smem_start = (unsigned)new_vaddr;
11017 + fix->smem_len = new_size;
11018 + fix->line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
11019 +
11020 + dev_info(info->device,
11021 + "%luKiB frame buffer at %08lx (mapped at %p)\n",
11022 + (unsigned long)info->fix.smem_len / 1024,
11023 + (unsigned long)info->fix.smem_start,
11024 + info->screen_base);
11025 +
11026 + return 0;
11027 +}
11028 +
11029 +
11030 +/*
11031 + * The s1d15605 seems to be divided into eight 128 pixel wide pages (from top to
11032 + * bottom) each page seems to be eight pixels high, where these eight pixels are
11033 + * one byte
11034 + */
11035 +static void s1d15605_update(struct fb_info *info)
11036 +{
11037 + struct s1d15605fb_info *sinfo = info->par;
11038 + int page, i, row, colmask;
11039 + u8 retVal, *rowPtr;
11040 +
11041 + WRITE_COMMAND(START_LINE_SET);
11042 + for (page = 0; page < NUM_OF_PAGES; ++page) {
11043 + WRITE_COMMAND(PAGE_ADDRESS_SET + page);
11044 + WRITE_COMMAND(COLUMN_ADDRESS_HIGH);
11045 + WRITE_COMMAND(COLUMN_ADDRESS_LOW);
11046 +
11047 + for (i = 0; i < NUM_OF_COLUMNS; ++i)
11048 + {
11049 + /* point of opportunity: optimization */
11050 + colmask = (1 << (i & 0x7));
11051 + rowPtr = (u8*)(info->screen_base);
11052 + rowPtr += (VIDEOWIDTH_BYTES * 8 * page);
11053 + rowPtr += (i >> 3);
11054 + retVal = 0;
11055 + for (row = 0; row < 8; ++row)
11056 + {
11057 + retVal = (retVal >> 1) | (((*rowPtr) & colmask) ? 0x80 : 0);
11058 + rowPtr += VIDEOWIDTH_BYTES;
11059 + }
11060 + WRITE_DATA(retVal);
11061 + }
11062 + }
11063 +
11064 + WRITE_COMMAND(DISPLAY_ON);
11065 +}
11066 +
11067 +
11068 +/*
11069 + * Setting the video mode has been split into two parts.
11070 + * First part, xxxfb_check_var, must not write anything
11071 + * to hardware, it should only verify and adjust var.
11072 + * This means it doesn't alter par but it does use hardware
11073 + * data from it to check this var.
11074 + */
11075 +static int s1d15605_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
11076 +{
11077 + /*
11078 + * Some very basic checks
11079 + */
11080 + if (!var->xres)
11081 + var->xres = 1;
11082 + if (!var->yres)
11083 + var->yres = 1;
11084 + if (var->xres > var->xres_virtual)
11085 + var->xres_virtual = var->xres;
11086 + if (var->yres > var->yres_virtual)
11087 + var->yres_virtual = var->yres;
11088 +
11089 + if(var->bits_per_pixel > VIDEODEPTH)
11090 + return -EINVAL;
11091 +
11092 + /*
11093 + * Memory limit
11094 + */
11095 + if (((var->yres_virtual * var->bits_per_pixel * var->yres_virtual) >> 3) >
11096 + ACTUALVIDEOMEMSIZE)
11097 + return -ENOMEM;
11098 +
11099 + /*
11100 + * Now that we checked it we alter var. The reason being is that the video
11101 + * mode passed in might not work but slight changes to it might make it
11102 + * work. This way we let the user know what is acceptable.
11103 + */
11104 + switch (var->bits_per_pixel) {
11105 + case 1:
11106 + var->red.offset = var->green.offset = var->blue.offset = 0;
11107 + var->red.length = var->green.length = var->blue.length
11108 + = var->bits_per_pixel;
11109 + break;
11110 + default:
11111 + return -EINVAL;
11112 + }
11113 +
11114 + var->xoffset = var->yoffset = 0;
11115 + var->red.msb_right = var->green.msb_right = var->blue.msb_right =
11116 + var->transp.msb_right = 0;
11117 +
11118 + return 0;
11119 +}
11120 +
11121 +
11122 +/*
11123 + * This routine actually sets the video mode. It's in here where we
11124 + * the hardware state info->par and fix which can be affected by the
11125 + * change in par. For this driver it doesn't do much.
11126 + */
11127 +static int s1d15605_set_par(struct fb_info *info)
11128 +{
11129 + int ret;
11130 +
11131 + MSG("%s:\n", __func__);
11132 + MSG(" * resolution: %ux%u (%ux%u virtual)\n",
11133 + info->var.xres, info->var.yres,
11134 + info->var.xres_virtual, info->var.yres_virtual);
11135 +
11136 + ret = s1d15605fb_resize_framebuffer(info->par);
11137 +
11138 + info->fix.visual = FB_VISUAL_MONO10;
11139 + return ret;
11140 +}
11141 +
11142 +
11143 +/*
11144 + * Set a single color register. The values supplied are already
11145 + * rounded down to the hardware's capabilities (according to the
11146 + * entries in the var structure). Return != 0 for invalid regno.
11147 + */
11148 +static int s1d15605_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
11149 + u_int transp, struct fb_info *info)
11150 +{
11151 + if (regno > 1) /* no. of hw registers - we only do mono now */
11152 + return 1;
11153 +
11154 + return 0;
11155 +}
11156 +
11157 +
11158 +/*
11159 + * Currently, the routine will simply shut-off the backlight and prevent
11160 + * updates/refreshes. Modify according to application.
11161 + *
11162 + * 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off
11163 + */
11164 +static int s1d15605_blank(int blank, struct fb_info *info)
11165 +{
11166 +#ifdef CONFIG_PMAC_BACKLIGHT
11167 + if (blank)
11168 + pmac_backlight->props.power = FB_BLANK_POWERDOWN;
11169 + else
11170 + pmac_backlight->props.power = FB_BLANK_UNBLANK;
11171 + backlight_update_status(pmac_backlight);
11172 +#endif
11173 + return 1;
11174 +}
11175 +
11176 +
11177 +/*
11178 + * Pan or Wrap the Display
11179 + *
11180 + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
11181 + */
11182 +/*
11183 +static int s1d15605_pan_display(struct fb_var_screeninfo *var,
11184 + struct fb_info *info)
11185 +{
11186 + if (var->vmode & FB_VMODE_YWRAP) {
11187 + if (var->yoffset < 0
11188 + || var->yoffset >= info->var.yres_virtual
11189 + || var->xoffset)
11190 + return -EINVAL;
11191 + } else {
11192 + if (var->xoffset + var->xres > info->var.xres_virtual ||
11193 + var->yoffset + var->yres > info->var.yres_virtual)
11194 + return -EINVAL;
11195 + }
11196 + info->var.xoffset = var->xoffset;
11197 + info->var.yoffset = var->yoffset;
11198 + if (var->vmode & FB_VMODE_YWRAP)
11199 + info->var.vmode |= FB_VMODE_YWRAP;
11200 + else
11201 + info->var.vmode &= ~FB_VMODE_YWRAP;
11202 + return 0;
11203 +}
11204 +*/
11205 +
11206 +
11207 +static void s1d15605_copyarea(struct fb_info *info, const struct fb_copyarea *region)
11208 +{
11209 + cfb_copyarea(info, region);
11210 + s1d15605_update(info);
11211 +}
11212 +
11213 +
11214 +static void s1d15605_fillrect (struct fb_info *info, const struct fb_fillrect *rect)
11215 +{
11216 + cfb_fillrect(info, rect);
11217 + s1d15605_update(info);
11218 +}
11219 +
11220 +
11221 +static void s1d15605_imageblit(struct fb_info *p, const struct fb_image *image)
11222 +{
11223 + cfb_imageblit(p, image);
11224 + s1d15605_update(p);
11225 +}
11226 +
11227 +
11228 +/*
11229 + * Write the users data to our framebuffer, and then trigger a psuedo DMA
11230 + */
11231 +static ssize_t s1d15605_write(struct fb_info *info, const char *buf,
11232 + size_t count, loff_t *ppos)
11233 +{
11234 + unsigned long p = *ppos;
11235 + int err;
11236 +
11237 + if (p > info->fix.smem_len)
11238 + return -ENOSPC;
11239 + if (count >= info->fix.smem_len)
11240 + count = info->fix.smem_len;
11241 + err = 0;
11242 + if (count + p > info->fix.smem_len) {
11243 + count = info->fix.smem_len - p;
11244 + err = -ENOSPC;
11245 + }
11246 + if (count) {
11247 + char *base_addr;
11248 +
11249 + base_addr = info->screen_base;
11250 + count -= copy_from_user(base_addr+p, buf, count);
11251 + *ppos += count;
11252 + err = -EFAULT;
11253 + }
11254 +
11255 + s1d15605_update(info);
11256 +
11257 + if (count)
11258 + return count;
11259 +
11260 + return err;
11261 +}
11262 +
11263 +#ifdef USE_PRIVATE_VMA_FXS
11264 +static void s1d15605_vma_open(struct vm_area_struct *vma)
11265 +{
11266 + // FIXME - store stats in the device data via vm_private_data
11267 +}
11268 +
11269 +
11270 +static void s1d15605_vma_close(struct vm_area_struct *vma)
11271 +{
11272 + // FIXME - store stats in the device data via vm_private_data
11273 +}
11274 +
11275 +
11276 +static struct page *s1d15605_vma_nopage(struct vm_area_struct *vma,
11277 + unsigned long address, int *type)
11278 +{
11279 + struct page *page;
11280 + struct fb_info *info = vma->vm_private_data;
11281 +
11282 + page = virt_to_page(info->screen_base);
11283 + get_page(page);
11284 +
11285 + // FIXME - now someone has a link to our page, start periodically blitting
11286 + // latest updates to the actual device.
11287 +
11288 + return page;
11289 +}
11290 +
11291 +
11292 +static struct vm_operations_struct s1d15605_vm_ops = {
11293 + .open = s1d15605_vma_open,
11294 + .close = s1d15605_vma_close,
11295 + .nopage = s1d15605_vma_nopage
11296 +};
11297 +
11298 +
11299 +/* We don't do much here - because we have special vm_ops */
11300 +static int s1d15605_mmap(struct fb_info *info, struct vm_area_struct *vma)
11301 +{
11302 + vma->vm_ops = &s1d15605_vm_ops;
11303 + vma->vm_flags |= VM_RESERVED;
11304 + vma->vm_private_data = info;
11305 + s1d15605_vma_open(vma);
11306 +
11307 + return 0;
11308 +}
11309 +#endif /* USE_PRIVATE_VMA_FXS */
11310 +
11311 +
11312 +static struct fb_ops s1d15605fb_ops = {
11313 + .owner = THIS_MODULE,
11314 + .fb_check_var = s1d15605_check_var,
11315 + .fb_set_par = s1d15605_set_par,
11316 + .fb_setcolreg = s1d15605_setcolreg,
11317 + .fb_blank = s1d15605_blank,
11318 +// .fb_pan_display = s1d15605_pan_display,
11319 + .fb_fillrect = s1d15605_fillrect,
11320 + .fb_copyarea = s1d15605_copyarea,
11321 + .fb_imageblit = s1d15605_imageblit,
11322 + .fb_write = s1d15605_write,
11323 +#ifdef USE_PRIVATE_VMA_FXS
11324 + .fb_mmap = s1d15605_mmap,
11325 +#endif
11326 +};
11327 +
11328 +
11329 +static void s1d15605_device_init(struct s1d15605fb_info *sinfo) {
11330 +
11331 + char value;
11332 +
11333 + /* release the reset line by reading the device - proto hardware */
11334 + value = READ_COMMAND;
11335 + value = READ_COMMAND;
11336 +
11337 +#ifdef CONFIG_MACH_KB9200
11338 + /* new boards have dedicated reset line */
11339 + gpio_set_value(sinfo->reset_pin, 1);
11340 +#endif
11341 +
11342 + /* initialize the device within 5ms */
11343 + WRITE_COMMAND(RESET_DISPLAY);
11344 + WRITE_COMMAND(LCD_BIAS_1_9);
11345 + WRITE_COMMAND(ADC_SELECT_REVERSE);
11346 + WRITE_COMMAND(COMMON_OUTPUT_NORMAL);
11347 + WRITE_COMMAND(V5_RESISTOR_RATIO);
11348 + WRITE_COMMAND(ELECTRONIC_VOLUME_SET);
11349 + WRITE_COMMAND(ELECTRONIC_VOLUME_INIT);
11350 + WRITE_COMMAND(POWER_CONTROL_SET | VOLTAGE_REGULATOR | VOLTAGE_FOLLOWER | BOOSTER_CIRCUIT);
11351 + WRITE_COMMAND(DISPLAY_ON);
11352 +
11353 + WRITE_COMMAND(RESISTOR_RATIO_START + 4);
11354 + WRITE_COMMAND(ELECTRONIC_VOLUME_SET);
11355 + WRITE_COMMAND(0x33);
11356 +}
11357 +
11358 +
11359 +static int __init s1d15605fb_probe(struct platform_device *pdev)
11360 +{
11361 + struct device *dev = &pdev->dev;
11362 + struct fb_info *info;
11363 + struct s1d15605fb_info *sinfo;
11364 + int ret;
11365 +
11366 + MSG("%s\n", __func__);
11367 +
11368 + if (!(info = framebuffer_alloc(sizeof(struct s1d15605fb_info), dev))) {
11369 + dev_err(dev, "Cannot allocate framebuffer struct\n");
11370 + return -ENOMEM;
11371 + }
11372 +
11373 + sinfo = info->par;
11374 + sinfo->info = info;
11375 + sinfo->pdev = pdev;
11376 +
11377 + if (pdev->num_resources < 2) {
11378 + dev_err(dev, "Resources unusable\n");
11379 + ret = -ENODEV;
11380 + goto free_info;
11381 + }
11382 +
11383 + info->fbops = &s1d15605fb_ops;
11384 + strcpy(info->fix.id, pdev->name);
11385 +
11386 + info->fix.mmio_start = pdev->resource[0].start;
11387 + info->fix.mmio_len = pdev->resource[0].end - pdev->resource[0].start + 1;
11388 + sinfo->reset_pin = pdev->resource[1].start;
11389 +
11390 + ret = s1d15605fb_resize_framebuffer(sinfo);
11391 + if (ret < 0) {
11392 + dev_err(dev, "Cannot resize framebuffer: %d\n", ret);
11393 + goto free_fb;
11394 + }
11395 +
11396 + if (!request_mem_region(info->fix.mmio_start,
11397 + info->fix.mmio_len, pdev->name)) {
11398 + ret = -EBUSY;
11399 + goto free_fb;
11400 + }
11401 +
11402 + sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
11403 + if (!sinfo->mmio) {
11404 + dev_err(dev, "Cannot map LCD memory region\n");
11405 + goto release_mem;
11406 + }
11407 +
11408 + s1d15605_device_init(sinfo);
11409 +
11410 + ret = fb_find_mode(&info->var, info, NULL, NULL, 0, NULL, 1);
11411 +
11412 + if (!ret || (ret == 4))
11413 + info->var = s1d15605_default;
11414 +
11415 + info->fix = s1d15605_fix;
11416 + info->flags = FBINFO_FLAG_DEFAULT |
11417 +/* FBINFO_HWACCEL_YPAN | */
11418 + FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
11419 +
11420 + ret = register_framebuffer(info);
11421 + if (ret < 0) {
11422 + dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
11423 + goto unmap_mmio;
11424 + }
11425 +
11426 + dev_set_drvdata(dev, info);
11427 +
11428 + memset(info->screen_base, 0, info->fix.smem_len);
11429 + info->var.activate |= FB_ACTIVATE_NOW;
11430 + ret = fb_set_var(info, &info->var);
11431 + if (ret) {
11432 + dev_warn(dev, "Unable to set display parameters\n");
11433 + }
11434 +
11435 + info->var.activate &= ~(FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW);
11436 +
11437 + dev_dbg(dev, "%s SUCCESS\n", __func__);
11438 +
11439 + dev_info(dev, "Driver $Revision: 1.1 $\n");
11440 +
11441 + return 0;
11442 +
11443 +unmap_mmio:
11444 + iounmap(sinfo->mmio);
11445 +release_mem:
11446 + release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
11447 +free_fb:
11448 + kfree(info->screen_base);
11449 +
11450 +free_info:
11451 + framebuffer_release(info);
11452 +
11453 + dev_dbg(dev, "%s FAILED\n", __func__);
11454 + return ret;
11455 +}
11456 +
11457 +
11458 +static int __exit s1d15605fb_remove(struct platform_device *pdev)
11459 +{
11460 + struct device *dev = &pdev->dev;
11461 + struct fb_info *info = dev_get_drvdata(dev);
11462 + struct s1d15605fb_info *sinfo = info->par;
11463 +
11464 + if (!sinfo)
11465 + return 0;
11466 +
11467 + unregister_framebuffer(info);
11468 +
11469 + iounmap(sinfo->mmio);
11470 + release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
11471 +
11472 + kfree(info->screen_base);
11473 +
11474 + dev_set_drvdata(dev, NULL);
11475 + framebuffer_release(info);
11476 + return 0;
11477 +}
11478 +
11479 +
11480 +static struct platform_driver s1d15605fb_driver = {
11481 + .remove = __exit_p(s1d15605fb_remove),
11482 + .driver = {
11483 + .name = "s1d15605fb",
11484 + .owner = THIS_MODULE,
11485 + },
11486 +};
11487 +
11488 +
11489 +static int __init s1d15605fb_init(void)
11490 +{
11491 + return platform_driver_probe(&s1d15605fb_driver, s1d15605fb_probe);
11492 +}
11493 +
11494 +
11495 +static void __exit s1d15605fb_exit(void)
11496 +{
11497 + platform_driver_unregister(&s1d15605fb_driver);
11498 +}
11499 +
11500 +
11501 +module_init(s1d15605fb_init);
11502 +module_exit(s1d15605fb_exit);
11503 +
11504 +
11505 +MODULE_AUTHOR("KwikByte");
11506 +MODULE_DESCRIPTION("Epson S1D15605 LCD Controller framebuffer driver");
11507 +MODULE_LICENSE("GPL");
11508 --- a/drivers/watchdog/Kconfig
11509 +++ b/drivers/watchdog/Kconfig
11510 @@ -66,6 +66,14 @@
11511 Watchdog timer embedded into AT91RM9200 chips. This will reboot your
11512 system when the timeout is reached.
11513
11514 +config AT91SAM9_WATCHDOG
11515 + tristate "AT91SAM9 watchdog"
11516 + depends on ARCH_AT91 && !ARCH_AT91RM9200
11517 + select WATCHDOG_NOWAYOUT
11518 + help
11519 + Watchdog timer embedded into AT91SAM9 chips. This will reboot your
11520 + system when the timeout is reached.
11521 +
11522 config 21285_WATCHDOG
11523 tristate "DC21285 watchdog"
11524 depends on FOOTBRIDGE
11525 --- a/drivers/watchdog/Makefile
11526 +++ b/drivers/watchdog/Makefile
11527 @@ -26,6 +26,7 @@
11528
11529 # ARM Architecture
11530 obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
11531 +obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
11532 obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
11533 obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
11534 obj-$(CONFIG_977_WATCHDOG) += wdt977.o
11535 --- /dev/null
11536 +++ b/drivers/watchdog/at91sam9_wdt.c
11537 @@ -0,0 +1,259 @@
11538 +/*
11539 + * Watchdog driver for Atmel AT91SAM9x processors.
11540 + *
11541 + * Copyright (C) 2007 Renaud CERRATO r.cerrato@til-technologies.fr
11542 + *
11543 + * This program is free software; you can redistribute it and/or
11544 + * modify it under the terms of the GNU General Public License
11545 + * as published by the Free Software Foundation; either version
11546 + * 2 of the License, or (at your option) any later version.
11547 + */
11548 +
11549 +/*
11550 + * The Watchdog Timer Mode Register can be only written to once. If the
11551 + * timeout need to be set from Linux, be sure that the bootstrap or the
11552 + * bootloader doesn't write to this register.
11553 + */
11554 +
11555 +#include <linux/errno.h>
11556 +#include <linux/fs.h>
11557 +#include <linux/init.h>
11558 +#include <linux/kernel.h>
11559 +#include <linux/miscdevice.h>
11560 +#include <linux/module.h>
11561 +#include <linux/moduleparam.h>
11562 +#include <linux/platform_device.h>
11563 +#include <linux/types.h>
11564 +#include <linux/watchdog.h>
11565 +#include <linux/bitops.h>
11566 +#include <linux/uaccess.h>
11567 +
11568 +#include <asm/arch/at91_wdt.h>
11569 +
11570 +
11571 +#define WDT_MAX_TIME 16 /* seconds */
11572 +
11573 +static int wdt_timeout = -1; /* invalid */
11574 +
11575 +module_param(wdt_timeout, int, 0);
11576 +MODULE_PARM_DESC(wdt_timeout, "Watchdog time in seconds. (default = disabled)");
11577 +
11578 +
11579 +static unsigned long at91wdt_busy;
11580 +
11581 +/* ......................................................................... */
11582 +
11583 +/*
11584 + * Reload the watchdog timer. (ie, pat the watchdog)
11585 + */
11586 +static void inline at91_wdt_reload(void)
11587 +{
11588 + at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
11589 +}
11590 +
11591 +/* ......................................................................... */
11592 +
11593 +/*
11594 + * Watchdog device is opened, and watchdog starts running.
11595 + */
11596 +static int at91_wdt_open(struct inode *inode, struct file *file)
11597 +{
11598 + if (test_and_set_bit(0, &at91wdt_busy))
11599 + return -EBUSY;
11600 +
11601 + return nonseekable_open(inode, file);
11602 +}
11603 +
11604 +/*
11605 + * Close the watchdog device.
11606 + */
11607 +static int at91_wdt_close(struct inode *inode, struct file *file)
11608 +{
11609 + clear_bit(0, &at91wdt_busy);
11610 + return 0;
11611 +}
11612 +
11613 +/*
11614 + * Change the watchdog time interval.
11615 + */
11616 +static int at91_wdt_settimeout(int new_time)
11617 +{
11618 + unsigned int reg, mr;
11619 + /*
11620 + * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
11621 + *
11622 + * Since WDV is a 12-bit counter, the maximum period is
11623 + * 4096 / 256 = 16 seconds.
11624 + */
11625 + if ((new_time <= 0) || (new_time > WDT_MAX_TIME))
11626 + return -EINVAL;
11627 +
11628 + wdt_timeout = new_time;
11629 +
11630 + /* Program the Watchdog */
11631 + reg = AT91_WDT_WDRSTEN /* causes watchdog reset */
11632 + | AT91_WDT_WDRPROC /* causes processor reset */
11633 + | AT91_WDT_WDDBGHLT /* disabled in debug mode */
11634 + | AT91_WDT_WDD /* restart at any time */
11635 + | (((wdt_timeout * 256) - 1) & AT91_WDT_WDV); /* timer value */
11636 + at91_sys_write(AT91_WDT_MR, reg);
11637 +
11638 + /* Check if watchdog could be programmed */
11639 + mr = at91_sys_read(AT91_WDT_MR);
11640 + if (mr != reg) {
11641 + printk(KERN_ERR "at91sam9_wdt: Watchdog register already programmed.\n");
11642 + return -EIO;
11643 + }
11644 +
11645 + at91_wdt_reload();
11646 +
11647 + printk(KERN_INFO "AT91SAM9 Watchdog enabled (%d seconds, nowayout)\n", wdt_timeout);
11648 + return 0;
11649 +}
11650 +
11651 +static struct watchdog_info at91_wdt_info = {
11652 + .identity = "at91sam9 watchdog",
11653 + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
11654 +};
11655 +
11656 +/*
11657 + * Handle commands from user-space.
11658 + */
11659 +static int at91_wdt_ioctl(struct inode *inode, struct file *file,
11660 + unsigned int cmd, unsigned long arg)
11661 +{
11662 + void __user *argp = (void __user *)arg;
11663 + int __user *p = argp;
11664 + int new_value, err;
11665 +
11666 + switch (cmd) {
11667 + case WDIOC_KEEPALIVE:
11668 + at91_wdt_reload(); /* pat the watchdog */
11669 + return 0;
11670 +
11671 + case WDIOC_GETSUPPORT:
11672 + return copy_to_user(argp, &at91_wdt_info, sizeof(at91_wdt_info)) ? -EFAULT : 0;
11673 +
11674 + case WDIOC_SETTIMEOUT:
11675 + if (get_user(new_value, p))
11676 + return -EFAULT;
11677 +
11678 + err = at91_wdt_settimeout(new_value);
11679 + if (err)
11680 + return err;
11681 +
11682 + return put_user(wdt_timeout, p); /* return current value */
11683 +
11684 + case WDIOC_GETTIMEOUT:
11685 + return put_user(wdt_timeout, p);
11686 +
11687 + case WDIOC_GETSTATUS:
11688 + case WDIOC_GETBOOTSTATUS:
11689 + return put_user(0, p);
11690 + }
11691 + return -ENOTTY;
11692 +}
11693 +
11694 +/*
11695 + * Pat the watchdog whenever device is written to.
11696 + */
11697 +static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
11698 +{
11699 + at91_wdt_reload(); /* pat the watchdog */
11700 + return len;
11701 +}
11702 +
11703 +/* ......................................................................... */
11704 +
11705 +static const struct file_operations at91wdt_fops = {
11706 + .owner = THIS_MODULE,
11707 + .llseek = no_llseek,
11708 + .ioctl = at91_wdt_ioctl,
11709 + .open = at91_wdt_open,
11710 + .release = at91_wdt_close,
11711 + .write = at91_wdt_write,
11712 +};
11713 +
11714 +static struct miscdevice at91wdt_miscdev = {
11715 + .minor = WATCHDOG_MINOR,
11716 + .name = "watchdog",
11717 + .fops = &at91wdt_fops,
11718 +};
11719 +
11720 +static int __init at91wdt_probe(struct platform_device *pdev)
11721 +{
11722 + int res;
11723 +
11724 + if (at91wdt_miscdev.parent)
11725 + return -EBUSY;
11726 + at91wdt_miscdev.parent = &pdev->dev;
11727 +
11728 + res = misc_register(&at91wdt_miscdev);
11729 + if (res)
11730 + return res;
11731 +
11732 + /* Set watchdog */
11733 + if (at91_wdt_settimeout(wdt_timeout) == -EINVAL) {
11734 + pr_info("at91sam9_wdt: invalid timeout (must be between 1 and %d)\n", WDT_MAX_TIME);
11735 + return 0;
11736 + }
11737 +
11738 + return 0;
11739 +}
11740 +
11741 +static int __exit at91wdt_remove(struct platform_device *pdev)
11742 +{
11743 + int res;
11744 +
11745 + res = misc_deregister(&at91wdt_miscdev);
11746 + if (!res)
11747 + at91wdt_miscdev.parent = NULL;
11748 +
11749 + return res;
11750 +}
11751 +
11752 +#ifdef CONFIG_PM
11753 +
11754 +static int at91wdt_suspend(struct platform_device *pdev, pm_message_t message)
11755 +{
11756 + return 0;
11757 +}
11758 +
11759 +static int at91wdt_resume(struct platform_device *pdev)
11760 +{
11761 + return 0;
11762 +}
11763 +
11764 +#else
11765 +#define at91wdt_suspend NULL
11766 +#define at91wdt_resume NULL
11767 +#endif
11768 +
11769 +static struct platform_driver at91wdt_driver = {
11770 + .remove = __exit_p(at91wdt_remove),
11771 + .suspend = at91wdt_suspend,
11772 + .resume = at91wdt_resume,
11773 + .driver = {
11774 + .name = "at91_wdt",
11775 + .owner = THIS_MODULE,
11776 + },
11777 +};
11778 +
11779 +static int __init at91sam_wdt_init(void)
11780 +{
11781 + return platform_driver_probe(&at91wdt_driver, at91wdt_probe);
11782 +}
11783 +
11784 +static void __exit at91sam_wdt_exit(void)
11785 +{
11786 + platform_driver_unregister(&at91wdt_driver);
11787 +}
11788 +
11789 +module_init(at91sam_wdt_init);
11790 +module_exit(at91sam_wdt_exit);
11791 +
11792 +MODULE_AUTHOR("Renaud CERRATO");
11793 +MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
11794 +MODULE_LICENSE("GPL");
11795 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
11796 +MODULE_ALIAS("platform:at91_wdt");
11797 --- a/include/asm-arm/arch-at91/at91_ecc.h
11798 +++ b/include/asm-arm/arch-at91/at91_ecc.h
11799 @@ -1,6 +1,9 @@
11800 /*
11801 * include/asm-arm/arch-at91/at91_ecc.h
11802 *
11803 + * Copyright (C) 2007 Andrew Victor
11804 + * Copyright (C) 2007 Atmel Corporation.
11805 + *
11806 * Error Corrected Code Controller (ECC) - System peripherals regsters.
11807 * Based on AT91SAM9260 datasheet revision B.
11808 *
11809 @@ -13,26 +16,26 @@
11810 #ifndef AT91_ECC_H
11811 #define AT91_ECC_H
11812
11813 -#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
11814 +#define AT91_ECC_CR 0x00 /* Control register */
11815 #define AT91_ECC_RST (1 << 0) /* Reset parity */
11816
11817 -#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
11818 +#define AT91_ECC_MR 0x04 /* Mode register */
11819 #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
11820 #define AT91_ECC_PAGESIZE_528 (0)
11821 #define AT91_ECC_PAGESIZE_1056 (1)
11822 #define AT91_ECC_PAGESIZE_2112 (2)
11823 #define AT91_ECC_PAGESIZE_4224 (3)
11824
11825 -#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
11826 +#define AT91_ECC_SR 0x08 /* Status register */
11827 #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
11828 #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
11829 #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
11830
11831 -#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
11832 +#define AT91_ECC_PR 0x0c /* Parity register */
11833 #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
11834 #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
11835
11836 -#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
11837 +#define AT91_ECC_NPR 0x10 /* NParity register */
11838 #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
11839
11840 #endif
11841 --- a/include/asm-arm/arch-at91/at91_pit.h
11842 +++ b/include/asm-arm/arch-at91/at91_pit.h
11843 @@ -1,6 +1,9 @@
11844 /*
11845 * include/asm-arm/arch-at91/at91_pit.h
11846 *
11847 + * Copyright (C) 2007 Andrew Victor
11848 + * Copyright (C) 2007 Atmel Corporation.
11849 + *
11850 * Periodic Interval Timer (PIT) - System peripherals regsters.
11851 * Based on AT91SAM9261 datasheet revision D.
11852 *
11853 --- a/include/asm-arm/arch-at91/at91_pmc.h
11854 +++ b/include/asm-arm/arch-at91/at91_pmc.h
11855 @@ -23,6 +23,7 @@
11856 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
11857 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
11858 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
11859 +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
11860 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
11861 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
11862 #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
11863 @@ -39,10 +40,14 @@
11864 #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
11865
11866 #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
11867 +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
11868 +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
11869 +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
11870 +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
11871
11872 #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
11873 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
11874 -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
11875 +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
11876 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
11877
11878 #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
11879 @@ -56,6 +61,7 @@
11880 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
11881 #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
11882 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
11883 +#define AT91CAP9_PMC_USBDIV (0xf << 28) /* USB Divisor (PLLB only) [AT91CAP9 revC only] */
11884 #define AT91_PMC_USBDIV_1 (0 << 28)
11885 #define AT91_PMC_USBDIV_2 (1 << 28)
11886 #define AT91_PMC_USBDIV_4 (2 << 28)
11887 @@ -76,10 +82,13 @@
11888 #define AT91_PMC_PRES_32 (5 << 2)
11889 #define AT91_PMC_PRES_64 (6 << 2)
11890 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
11891 -#define AT91_PMC_MDIV_1 (0 << 8)
11892 -#define AT91_PMC_MDIV_2 (1 << 8)
11893 -#define AT91_PMC_MDIV_3 (2 << 8)
11894 -#define AT91_PMC_MDIV_4 (3 << 8)
11895 +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
11896 +#define AT91RM9200_PMC_MDIV_2 (1 << 8)
11897 +#define AT91RM9200_PMC_MDIV_3 (2 << 8)
11898 +#define AT91RM9200_PMC_MDIV_4 (3 << 8)
11899 +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
11900 +#define AT91SAM9_PMC_MDIV_2 (1 << 8)
11901 +#define AT91SAM9_PMC_MDIV_4 (2 << 8)
11902
11903 #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
11904
11905 @@ -90,10 +99,17 @@
11906 #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
11907 #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
11908 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
11909 +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
11910 +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
11911 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
11912 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
11913 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
11914 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
11915 #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
11916
11917 +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
11918 +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
11919 +
11920 +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
11921 +
11922 #endif
11923 --- a/include/asm-arm/arch-at91/at91_rstc.h
11924 +++ b/include/asm-arm/arch-at91/at91_rstc.h
11925 @@ -1,6 +1,9 @@
11926 /*
11927 * include/asm-arm/arch-at91/at91_rstc.h
11928 *
11929 + * Copyright (C) 2007 Andrew Victor
11930 + * Copyright (C) 2007 Atmel Corporation.
11931 + *
11932 * Reset Controller (RSTC) - System peripherals regsters.
11933 * Based on AT91SAM9261 datasheet revision D.
11934 *
11935 --- a/include/asm-arm/arch-at91/at91_rtt.h
11936 +++ b/include/asm-arm/arch-at91/at91_rtt.h
11937 @@ -1,6 +1,9 @@
11938 /*
11939 * include/asm-arm/arch-at91/at91_rtt.h
11940 *
11941 + * Copyright (C) 2007 Andrew Victor
11942 + * Copyright (C) 2007 Atmel Corporation.
11943 + *
11944 * Real-time Timer (RTT) - System peripherals regsters.
11945 * Based on AT91SAM9261 datasheet revision D.
11946 *
11947 --- a/include/asm-arm/arch-at91/at91_shdwc.h
11948 +++ b/include/asm-arm/arch-at91/at91_shdwc.h
11949 @@ -1,6 +1,9 @@
11950 /*
11951 * include/asm-arm/arch-at91/at91_shdwc.h
11952 *
11953 + * Copyright (C) 2007 Andrew Victor
11954 + * Copyright (C) 2007 Atmel Corporation.
11955 + *
11956 * Shutdown Controller (SHDWC) - System peripherals regsters.
11957 * Based on AT91SAM9261 datasheet revision D.
11958 *
11959 @@ -24,10 +27,12 @@
11960 #define AT91_SHDW_WKMODE0_LOW 2
11961 #define AT91_SHDW_WKMODE0_ANYLEVEL 3
11962 #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
11963 +#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
11964 #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
11965
11966 #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
11967 #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
11968 #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
11969 +#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
11970
11971 #endif
11972 --- /dev/null
11973 +++ b/include/asm-arm/arch-at91/at91_tsc.h
11974 @@ -0,0 +1,76 @@
11975 +/*
11976 + * include/asm-arm/arch-at91/at91_tsc.h
11977 + *
11978 + * Copyright (C) 2008 Andrew Victor
11979 + *
11980 + * Touch Screen ADC Controller (TSC)
11981 + * Based on AT91SAM9RL64 preliminary draft datasheet.
11982 + *
11983 + * This program is free software; you can redistribute it and/or modify it
11984 + * under the terms of the GNU General Public License as published by the
11985 + * Free Software Foundation; either version 2 of the License, or (at your
11986 + * option) any later version.
11987 + */
11988 +
11989 +#ifndef AT91_TSC_H
11990 +#define AT91_TSC_H
11991 +
11992 +#define AT91_TSADCC_CR 0x00 /* Control register */
11993 +#define AT91_TSADCC_SWRST (1 << 0) /* Software Reset*/
11994 +#define AT91_TSADCC_START (1 << 1) /* Start conversion */
11995 +
11996 +#define AT91_TSADCC_MR 0x04 /* Mode register */
11997 +#define AT91_TSADCC_TSAMOD (3 << 0) /* ADC mode */
11998 +#define AT91_TSADCC_LOWRES (1 << 4) /* Resolution selection */
11999 +#define AT91_TSADCC_SLEEP (1 << 5) /* Sleep mode */
12000 +#define AT91_TSADCC_PENDET (1 << 6) /* Pen Detect selection */
12001 +#define AT91_TSADCC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */
12002 +#define AT91_TSADCC_STARTUP (0x7f << 16) /* Start Up time */
12003 +#define AT91_TSADCC_SHTIM (0xf << 24) /* Sample & Hold time */
12004 +#define AT91_TSADCC_PENDBC (0xf << 28) /* Pen Detect debouncing time */
12005 +
12006 +#define AT91_TSADCC_TRGR 0x08 /* Trigger register */
12007 +#define AT91_TSADCC_TRGMOD (7 << 0) /* Trigger mode */
12008 +#define AT91_TSADCC_TRGMOD_NONE (0 << 0)
12009 +#define AT91_TSADCC_TRGMOD_EXT_RISING (1 << 0)
12010 +#define AT91_TSADCC_TRGMOD_EXT_FALLING (2 << 0)
12011 +#define AT91_TSADCC_TRGMOD_EXT_ANY (3 << 0)
12012 +#define AT91_TSADCC_TRGMOD_PENDET (4 << 0)
12013 +#define AT91_TSADCC_TRGMOD_PERIOD (5 << 0)
12014 +#define AT91_TSADCC_TRGMOD_CONTINUOUS (6 << 0)
12015 +#define AT91_TSADCC_TRGPER (0xffff << 16) /* Trigger period */
12016 +
12017 +#define AT91_TSADCC_TSR 0x0C /* Touch Screen register */
12018 +#define AT91_TSADCC_TSFREQ (0xf << 0) /* TS Frequency in Interleaved mode */
12019 +#define AT91_TSADCC_TSSHTIM (0xf << 24) /* Sample & Hold time */
12020 +
12021 +#define AT91_TSADCC_CHER 0x10 /* Channel Enable register */
12022 +#define AT91_TSADCC_CHDR 0x14 /* Channel Disable register */
12023 +#define AT91_TSADCC_CHSR 0x18 /* Channel Status register */
12024 +#define AT91_TSADCC_CH(n) (1 << (n)) /* Channel number */
12025 +
12026 +#define AT91_TSADCC_SR 0x1C /* Status register */
12027 +#define AT91_TSADCC_EOC(n) (1 << ((n)+0)) /* End of conversion for channel N */
12028 +#define AT91_TSADCC_OVRE(n) (1 << ((n)+8)) /* Overrun error for channel N */
12029 +#define AT91_TSADCC_DRDY (1 << 16) /* Data Ready */
12030 +#define AT91_TSADCC_GOVRE (1 << 17) /* General Overrun Error */
12031 +#define AT91_TSADCC_ENDRX (1 << 18) /* End of RX Buffer */
12032 +#define AT91_TSADCC_RXBUFF (1 << 19) /* TX Buffer full */
12033 +#define AT91_TSADCC_PENCNT (1 << 20) /* Pen contact */
12034 +#define AT91_TSADCC_NOCNT (1 << 21) /* No contact */
12035 +
12036 +#define AT91_TSADCC_LCDR 0x20 /* Last Converted Data register */
12037 +#define AT91_TSADCC_DATA (0x3ff << 0) /* Channel data */
12038 +
12039 +#define AT91_TSADCC_IER 0x24 /* Interrupt Enable register */
12040 +#define AT91_TSADCC_IDR 0x28 /* Interrupt Disable register */
12041 +#define AT91_TSADCC_IMR 0x2C /* Interrupt Mask register */
12042 +#define AT91_TSADCC_CDR0 0x30 /* Channel Data 0 */
12043 +#define AT91_TSADCC_CDR1 0x34 /* Channel Data 1 */
12044 +#define AT91_TSADCC_CDR2 0x38 /* Channel Data 2 */
12045 +#define AT91_TSADCC_CDR3 0x3C /* Channel Data 3 */
12046 +#define AT91_TSADCC_CDR4 0x40 /* Channel Data 4 */
12047 +#define AT91_TSADCC_CDR5 0x44 /* Channel Data 5 */
12048 +
12049 +#endif
12050 +
12051 --- a/include/asm-arm/arch-at91/at91_wdt.h
12052 +++ b/include/asm-arm/arch-at91/at91_wdt.h
12053 @@ -1,6 +1,9 @@
12054 /*
12055 * include/asm-arm/arch-at91/at91_wdt.h
12056 *
12057 + * Copyright (C) 2007 Andrew Victor
12058 + * Copyright (C) 2007 Atmel Corporation.
12059 + *
12060 * Watchdog Timer (WDT) - System peripherals regsters.
12061 * Based on AT91SAM9261 datasheet revision D.
12062 *
12063 --- a/include/asm-arm/arch-at91/at91cap9.h
12064 +++ b/include/asm-arm/arch-at91/at91cap9.h
12065 @@ -101,7 +101,10 @@
12066 #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
12067 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
12068 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
12069 -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
12070 +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
12071 +#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
12072 + (0xfffffd50 - AT91_BASE_SYS) : \
12073 + (0xfffffd60 - AT91_BASE_SYS))
12074
12075 #define AT91_USART0 AT91CAP9_BASE_US0
12076 #define AT91_USART1 AT91CAP9_BASE_US1
12077 @@ -118,7 +121,7 @@
12078 #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
12079
12080 #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
12081 -#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
12082 +#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
12083 #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
12084
12085 #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
12086 --- /dev/null
12087 +++ b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
12088 @@ -0,0 +1,102 @@
12089 +/*
12090 + * include/asm-arm/arch-at91/at91cap9_ddrsdr.h
12091 + *
12092 + * (C) 2008 Andrew Victor
12093 + *
12094 + * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
12095 + * Based on AT91CAP9 datasheet revision B.
12096 + *
12097 + * This program is free software; you can redistribute it and/or modify
12098 + * it under the terms of the GNU General Public License as published by
12099 + * the Free Software Foundation; either version 2 of the License, or
12100 + * (at your option) any later version.
12101 + */
12102 +
12103 +#ifndef AT91CAP9_DDRSDR_H
12104 +#define AT91CAP9_DDRSDR_H
12105 +
12106 +#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */
12107 +#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
12108 +#define AT91_DDRSDRC_MODE_NORMAL 0
12109 +#define AT91_DDRSDRC_MODE_NOP 1
12110 +#define AT91_DDRSDRC_MODE_PRECHARGE 2
12111 +#define AT91_DDRSDRC_MODE_LMR 3
12112 +#define AT91_DDRSDRC_MODE_REFRESH 4
12113 +#define AT91_DDRSDRC_MODE_EXT_LMR 5
12114 +#define AT91_DDRSDRC_MODE_DEEP 6
12115 +
12116 +#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */
12117 +#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
12118 +
12119 +#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */
12120 +#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
12121 +#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
12122 +#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
12123 +#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
12124 +#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
12125 +#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
12126 +#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
12127 +#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
12128 +#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
12129 +#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
12130 +#define AT91_DDRSDRC_NR_11 (0 << 2)
12131 +#define AT91_DDRSDRC_NR_12 (1 << 2)
12132 +#define AT91_DDRSDRC_NR_13 (2 << 2)
12133 +#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
12134 +#define AT91_DDRSDRC_CAS_2 (2 << 4)
12135 +#define AT91_DDRSDRC_CAS_3 (3 << 4)
12136 +#define AT91_DDRSDRC_CAS_25 (6 << 4)
12137 +#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
12138 +#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
12139 +
12140 +#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */
12141 +#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
12142 +#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
12143 +#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
12144 +#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
12145 +#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
12146 +#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
12147 +#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
12148 +#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
12149 +
12150 +#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */
12151 +#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
12152 +#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
12153 +#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
12154 +#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
12155 +
12156 +#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */
12157 +#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
12158 +#define AT91_DDRSDRC_LPCB_DISABLE 0
12159 +#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
12160 +#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
12161 +#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
12162 +#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
12163 +#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
12164 +#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
12165 +#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
12166 +#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
12167 +#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
12168 +#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
12169 +#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
12170 +
12171 +#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */
12172 +#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
12173 +#define AT91_DDRSDRC_MD_SDR 0
12174 +#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
12175 +#define AT91_DDRSDRC_MD_DDR 2
12176 +#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
12177 +
12178 +#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */
12179 +#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
12180 +#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
12181 +#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
12182 +#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
12183 +#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
12184 +#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
12185 +#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
12186 +#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
12187 +#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
12188 +
12189 +
12190 +#endif
12191 --- a/include/asm-arm/arch-at91/at91cap9_matrix.h
12192 +++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
12193 @@ -106,6 +106,11 @@
12194 #define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
12195 #define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
12196
12197 +#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
12198 +#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
12199 +#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
12200 +#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
12201 +
12202 #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
12203 #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
12204 #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
12205 --- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
12206 +++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
12207 @@ -1,6 +1,8 @@
12208 /*
12209 * include/asm-arm/arch-at91/at91sam9260_matrix.h
12210 *
12211 + * Copyright (C) 2007 Atmel Corporation.
12212 + *
12213 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
12214 * Based on AT91SAM9260 datasheet revision B.
12215 *
12216 --- a/include/asm-arm/arch-at91/at91sam9261_matrix.h
12217 +++ b/include/asm-arm/arch-at91/at91sam9261_matrix.h
12218 @@ -1,6 +1,8 @@
12219 /*
12220 * include/asm-arm/arch-at91/at91sam9261_matrix.h
12221 *
12222 + * Copyright (C) 2007 Atmel Corporation.
12223 + *
12224 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
12225 * Based on AT91SAM9261 datasheet revision D.
12226 *
12227 --- a/include/asm-arm/arch-at91/at91sam926x_mc.h
12228 +++ /dev/null
12229 @@ -1,141 +0,0 @@
12230 -/*
12231 - * include/asm-arm/arch-at91/at91sam926x_mc.h
12232 - *
12233 - * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
12234 - * Based on AT91SAM9261 datasheet revision D.
12235 - *
12236 - * This program is free software; you can redistribute it and/or modify
12237 - * it under the terms of the GNU General Public License as published by
12238 - * the Free Software Foundation; either version 2 of the License, or
12239 - * (at your option) any later version.
12240 - */
12241 -
12242 -#ifndef AT91SAM926x_MC_H
12243 -#define AT91SAM926x_MC_H
12244 -
12245 -/* SDRAM Controller (SDRAMC) registers */
12246 -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
12247 -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
12248 -#define AT91_SDRAMC_MODE_NORMAL 0
12249 -#define AT91_SDRAMC_MODE_NOP 1
12250 -#define AT91_SDRAMC_MODE_PRECHARGE 2
12251 -#define AT91_SDRAMC_MODE_LMR 3
12252 -#define AT91_SDRAMC_MODE_REFRESH 4
12253 -#define AT91_SDRAMC_MODE_EXT_LMR 5
12254 -#define AT91_SDRAMC_MODE_DEEP 6
12255 -
12256 -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
12257 -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
12258 -
12259 -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
12260 -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
12261 -#define AT91_SDRAMC_NC_8 (0 << 0)
12262 -#define AT91_SDRAMC_NC_9 (1 << 0)
12263 -#define AT91_SDRAMC_NC_10 (2 << 0)
12264 -#define AT91_SDRAMC_NC_11 (3 << 0)
12265 -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
12266 -#define AT91_SDRAMC_NR_11 (0 << 2)
12267 -#define AT91_SDRAMC_NR_12 (1 << 2)
12268 -#define AT91_SDRAMC_NR_13 (2 << 2)
12269 -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
12270 -#define AT91_SDRAMC_NB_2 (0 << 4)
12271 -#define AT91_SDRAMC_NB_4 (1 << 4)
12272 -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
12273 -#define AT91_SDRAMC_CAS_1 (1 << 5)
12274 -#define AT91_SDRAMC_CAS_2 (2 << 5)
12275 -#define AT91_SDRAMC_CAS_3 (3 << 5)
12276 -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
12277 -#define AT91_SDRAMC_DBW_32 (0 << 7)
12278 -#define AT91_SDRAMC_DBW_16 (1 << 7)
12279 -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
12280 -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
12281 -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
12282 -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
12283 -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
12284 -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
12285 -
12286 -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
12287 -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
12288 -#define AT91_SDRAMC_LPCB_DISABLE 0
12289 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
12290 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2
12291 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
12292 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
12293 -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
12294 -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
12295 -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
12296 -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
12297 -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
12298 -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
12299 -
12300 -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
12301 -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
12302 -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
12303 -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
12304 -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
12305 -
12306 -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
12307 -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
12308 -#define AT91_SDRAMC_MD_SDRAM 0
12309 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
12310 -
12311 -
12312 -/* Static Memory Controller (SMC) registers */
12313 -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
12314 -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
12315 -#define AT91_SMC_NWESETUP_(x) ((x) << 0)
12316 -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
12317 -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
12318 -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
12319 -#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
12320 -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
12321 -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
12322 -
12323 -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
12324 -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
12325 -#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
12326 -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
12327 -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
12328 -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
12329 -#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
12330 -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
12331 -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
12332 -
12333 -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
12334 -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
12335 -#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
12336 -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
12337 -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
12338 -
12339 -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
12340 -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
12341 -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
12342 -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
12343 -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
12344 -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
12345 -#define AT91_SMC_EXNWMODE_READY (3 << 4)
12346 -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
12347 -#define AT91_SMC_BAT_SELECT (0 << 8)
12348 -#define AT91_SMC_BAT_WRITE (1 << 8)
12349 -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
12350 -#define AT91_SMC_DBW_8 (0 << 12)
12351 -#define AT91_SMC_DBW_16 (1 << 12)
12352 -#define AT91_SMC_DBW_32 (2 << 12)
12353 -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
12354 -#define AT91_SMC_TDF_(x) ((x) << 16)
12355 -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
12356 -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
12357 -#define AT91_SMC_PS (3 << 28) /* Page Size */
12358 -#define AT91_SMC_PS_4 (0 << 28)
12359 -#define AT91_SMC_PS_8 (1 << 28)
12360 -#define AT91_SMC_PS_16 (2 << 28)
12361 -#define AT91_SMC_PS_32 (3 << 28)
12362 -
12363 -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
12364 -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
12365 -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
12366 -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
12367 -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
12368 -#endif
12369 -
12370 -#endif
12371 --- /dev/null
12372 +++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
12373 @@ -0,0 +1,86 @@
12374 +/*
12375 + * include/asm-arm/arch-at91/at91sam9_sdramc.h
12376 + *
12377 + * Copyright (C) 2007 Andrew Victor
12378 + * Copyright (C) 2007 Atmel Corporation.
12379 + *
12380 + * SDRAM Controllers (SDRAMC) - System peripherals registers.
12381 + * Based on AT91SAM9261 datasheet revision D.
12382 + *
12383 + * This program is free software; you can redistribute it and/or modify
12384 + * it under the terms of the GNU General Public License as published by
12385 + * the Free Software Foundation; either version 2 of the License, or
12386 + * (at your option) any later version.
12387 + */
12388 +
12389 +#ifndef AT91SAM9_SDRAMC_H
12390 +#define AT91SAM9_SDRAMC_H
12391 +
12392 +/* SDRAM Controller (SDRAMC) registers */
12393 +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
12394 +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
12395 +#define AT91_SDRAMC_MODE_NORMAL 0
12396 +#define AT91_SDRAMC_MODE_NOP 1
12397 +#define AT91_SDRAMC_MODE_PRECHARGE 2
12398 +#define AT91_SDRAMC_MODE_LMR 3
12399 +#define AT91_SDRAMC_MODE_REFRESH 4
12400 +#define AT91_SDRAMC_MODE_EXT_LMR 5
12401 +#define AT91_SDRAMC_MODE_DEEP 6
12402 +
12403 +#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
12404 +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
12405 +
12406 +#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
12407 +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
12408 +#define AT91_SDRAMC_NC_8 (0 << 0)
12409 +#define AT91_SDRAMC_NC_9 (1 << 0)
12410 +#define AT91_SDRAMC_NC_10 (2 << 0)
12411 +#define AT91_SDRAMC_NC_11 (3 << 0)
12412 +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
12413 +#define AT91_SDRAMC_NR_11 (0 << 2)
12414 +#define AT91_SDRAMC_NR_12 (1 << 2)
12415 +#define AT91_SDRAMC_NR_13 (2 << 2)
12416 +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
12417 +#define AT91_SDRAMC_NB_2 (0 << 4)
12418 +#define AT91_SDRAMC_NB_4 (1 << 4)
12419 +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
12420 +#define AT91_SDRAMC_CAS_1 (1 << 5)
12421 +#define AT91_SDRAMC_CAS_2 (2 << 5)
12422 +#define AT91_SDRAMC_CAS_3 (3 << 5)
12423 +#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
12424 +#define AT91_SDRAMC_DBW_32 (0 << 7)
12425 +#define AT91_SDRAMC_DBW_16 (1 << 7)
12426 +#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
12427 +#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
12428 +#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
12429 +#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
12430 +#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
12431 +#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
12432 +
12433 +#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
12434 +#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
12435 +#define AT91_SDRAMC_LPCB_DISABLE 0
12436 +#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
12437 +#define AT91_SDRAMC_LPCB_POWER_DOWN 2
12438 +#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
12439 +#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
12440 +#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
12441 +#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
12442 +#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
12443 +#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
12444 +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
12445 +#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
12446 +
12447 +#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
12448 +#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
12449 +#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
12450 +#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
12451 +#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
12452 +
12453 +#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
12454 +#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
12455 +#define AT91_SDRAMC_MD_SDRAM 0
12456 +#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
12457 +
12458 +
12459 +#endif
12460 --- /dev/null
12461 +++ b/include/asm-arm/arch-at91/at91sam9_smc.h
12462 @@ -0,0 +1,76 @@
12463 +/*
12464 + * include/asm-arm/arch-at91/at91sam9_smc.h
12465 + *
12466 + * Copyright (C) 2007 Andrew Victor
12467 + * Copyright (C) 2007 Atmel Corporation.
12468 + *
12469 + * Static Memory Controllers (SMC) - System peripherals registers.
12470 + * Based on AT91SAM9261 datasheet revision D.
12471 + *
12472 + * This program is free software; you can redistribute it and/or modify
12473 + * it under the terms of the GNU General Public License as published by
12474 + * the Free Software Foundation; either version 2 of the License, or
12475 + * (at your option) any later version.
12476 + */
12477 +
12478 +#ifndef AT91SAM9_SMC_H
12479 +#define AT91SAM9_SMC_H
12480 +
12481 +#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
12482 +#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
12483 +#define AT91_SMC_NWESETUP_(x) ((x) << 0)
12484 +#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
12485 +#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
12486 +#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
12487 +#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
12488 +#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
12489 +#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
12490 +
12491 +#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
12492 +#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
12493 +#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
12494 +#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
12495 +#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
12496 +#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
12497 +#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
12498 +#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
12499 +#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
12500 +
12501 +#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
12502 +#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
12503 +#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
12504 +#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
12505 +#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
12506 +
12507 +#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
12508 +#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
12509 +#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
12510 +#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
12511 +#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
12512 +#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
12513 +#define AT91_SMC_EXNWMODE_READY (3 << 4)
12514 +#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
12515 +#define AT91_SMC_BAT_SELECT (0 << 8)
12516 +#define AT91_SMC_BAT_WRITE (1 << 8)
12517 +#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
12518 +#define AT91_SMC_DBW_8 (0 << 12)
12519 +#define AT91_SMC_DBW_16 (1 << 12)
12520 +#define AT91_SMC_DBW_32 (2 << 12)
12521 +#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
12522 +#define AT91_SMC_TDF_(x) ((x) << 16)
12523 +#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
12524 +#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
12525 +#define AT91_SMC_PS (3 << 28) /* Page Size */
12526 +#define AT91_SMC_PS_4 (0 << 28)
12527 +#define AT91_SMC_PS_8 (1 << 28)
12528 +#define AT91_SMC_PS_16 (2 << 28)
12529 +#define AT91_SMC_PS_32 (3 << 28)
12530 +
12531 +#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
12532 +#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
12533 +#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
12534 +#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
12535 +#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
12536 +#endif
12537 +
12538 +#endif
12539 --- a/include/asm-arm/arch-at91/at91sam9rl.h
12540 +++ b/include/asm-arm/arch-at91/at91sam9rl.h
12541 @@ -110,6 +110,6 @@
12542 #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
12543
12544 #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
12545 -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
12546 +#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
12547
12548 #endif
12549 --- a/include/asm-arm/arch-at91/board.h
12550 +++ b/include/asm-arm/arch-at91/board.h
12551 @@ -36,6 +36,7 @@
12552 #include <linux/i2c.h>
12553 #include <linux/leds.h>
12554 #include <linux/spi/spi.h>
12555 +#include <linux/usb/atmel_usba_udc.h>
12556
12557 /* USB Device */
12558 struct at91_udc_data {
12559 @@ -45,6 +46,9 @@
12560 };
12561 extern void __init at91_add_device_udc(struct at91_udc_data *data);
12562
12563 + /* USB High Speed Device */
12564 +extern void __init at91_add_device_usba(struct usba_platform_data *data);
12565 +
12566 /* Compact Flash */
12567 struct at91_cf_data {
12568 u8 irq_pin; /* I/O IRQ */
12569 @@ -158,6 +162,9 @@
12570 /* ISI */
12571 extern void __init at91_add_device_isi(void);
12572
12573 + /* Touchscreen Controller */
12574 +extern void __init at91_add_device_tsadcc(void);
12575 +
12576 /* LEDs */
12577 extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
12578 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
12579 --- a/include/asm-arm/arch-at91/cpu.h
12580 +++ b/include/asm-arm/arch-at91/cpu.h
12581 @@ -48,6 +48,17 @@
12582 return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
12583 }
12584
12585 +#ifdef CONFIG_ARCH_AT91CAP9
12586 +#include <asm/arch/at91_pmc.h>
12587 +
12588 +#define ARCH_REVISION_CAP9_B 0x399
12589 +#define ARCH_REVISION_CAP9_C 0x601
12590 +
12591 +static inline unsigned long at91cap9_rev_identify(void)
12592 +{
12593 + return (at91_sys_read(AT91_PMC_VER));
12594 +}
12595 +#endif
12596
12597 #ifdef CONFIG_ARCH_AT91RM9200
12598 #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
12599 @@ -83,8 +94,12 @@
12600
12601 #ifdef CONFIG_ARCH_AT91CAP9
12602 #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
12603 +#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
12604 +#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C)
12605 #else
12606 #define cpu_is_at91cap9() (0)
12607 +#define cpu_is_at91cap9_revB() (0)
12608 +#define cpu_is_at91cap9_revC() (0)
12609 #endif
12610
12611 /*
12612 --- /dev/null
12613 +++ b/include/asm-arm/arch-at91/ics1523.h
12614 @@ -0,0 +1,154 @@
12615 +//*----------------------------------------------------------------------------
12616 +//* ATMEL Microcontroller Software Support - ROUSSET -
12617 +//*----------------------------------------------------------------------------
12618 +//* The software is delivered "AS IS" without warranty or condition of any
12619 +//* kind, either express, implied or statutory. This includes without
12620 +//* limitation any warranty or condition with respect to merchantability or
12621 +//* fitness for any particular purpose, or against the infringements of
12622 +//* intellectual property rights of others.
12623 +//*----------------------------------------------------------------------------
12624 +//* File Name : ics1523.h
12625 +//* Object : Clock Generator Prototyping File.
12626 +//*
12627 +//* 1.0 08/28/02 ED : Creation
12628 +//* 1.2 13/01/03 FB : Update on lib V3
12629 +//*----------------------------------------------------------------------------
12630 +
12631 +#ifndef ics1523_h
12632 +#define ics1523_h
12633 +
12634 +/*-------------------------------------------*/
12635 +/* ICS1523 TWI Serial Clock Definition */
12636 +/*-------------------------------------------*/
12637 +
12638 +#define ICS_MIN_CLOCK 100 /* Min Frequency Access Clock KHz */
12639 +#define ICS_MAX_CLOCK 400 /* Max Frequency Access Clock KHz */
12640 +#define ICS_TRANSFER_RATE ICS_MAX_CLOCK /* Transfer speed to apply */
12641 +
12642 +#define ICS_WRITE_CLK_PNB 30 /* TWCK Clock Periods required to write */
12643 +#define ICS_READ_CLK_PNB 40 /* TWCK Clock Periods required to read */
12644 +
12645 +/*-------------------------------------------*/
12646 +/* ICS1523 Write Operation Definition */
12647 +/*-------------------------------------------*/
12648 +
12649 +#define ICS1523_ACCESS_OK 0 /* OK */
12650 +#define ICS1523_ACCESS_ERROR -1 /* NOK */
12651 +
12652 +/*-------------------------------------------*/
12653 +/* ICS1523 Device Addresses Definition */
12654 +/*-------------------------------------------*/
12655 +
12656 +#define ICS_ADDR 0x26 /* Device Address */
12657 +
12658 +/*--------------------------------------------------*/
12659 +/* ICS1523 Registers Internal Addresses Definition */
12660 +/*--------------------------------------------------*/
12661 +
12662 +#define ICS_ICR 0x0 /* Input Control Register */
12663 +#define ICS_LCR 0x1 /* Loop Control Register */
12664 +#define ICS_FD0 0x2 /* PLL FeedBack Divider LSBs */
12665 +#define ICS_FD1 0x3 /* PLL FeedBack Divider MSBs */
12666 +#define ICS_DPAO 0x4 /* Dynamic Phase Aligner Offset */
12667 +#define ICS_DPAC 0x5 /* Dynamic Phase Aligner Resolution */
12668 +#define ICS_OE 0x6 /* Output Enables Register */
12669 +#define ICS_OD 0x7 /* Osc Divider Register */
12670 +#define ICS_SWRST 0x8 /* DPA & PLL Reset Register */
12671 +#define ICS_VID 0x10 /* Chip Version Register */
12672 +#define ICS_RID 0x11 /* Chip Revision Register */
12673 +#define ICS_SR 0x12 /* Status Register */
12674 +
12675 +/*------------------------------------------------------*/
12676 +/* ICS1523 Input Control Register Bits Definition */
12677 +/*------------------------------------------------------*/
12678 +
12679 +#define ICS_PDEN 0x1 /* Phase Detector Enable */
12680 +#define ICS_PDPOL 0x2 /* Phase Detector Enable Polarity */
12681 +#define ICS_REFPOL 0x4 /* External Reference Polarity */
12682 +#define ICS_FBKPOL 0x8 /* External Feedback Polarity */
12683 +#define ICS_FBKSEL 0x10 /* External Feedback Select */
12684 +#define ICS_FUNCSEL 0x20 /* Function Out Select */
12685 +#define ICS_ENPLS 0x40 /* Enable PLL Lock/Ref Status Output */
12686 +#define ICS_ENDLS 0x80 /* Enable DPA Lock/Ref Status Output */
12687 +
12688 +/*-----------------------------------------------------*/
12689 +/* ICS1523 Loop Control Register Bits Definition */
12690 +/*-----------------------------------------------------*/
12691 +
12692 +#define ICS_PFD 0x7 /* Phase Detector Gain */
12693 +#define ICS_PSD 0x30 /* Post-Scaler Divider */
12694 +
12695 +/*----------------------------------------------------*/
12696 +/* ICS1523 PLL FeedBack Divider LSBs Definition */
12697 +/*----------------------------------------------------*/
12698 +
12699 +#define ICS_FBDL 0xFF /* PLL FeedBack Divider LSBs */
12700 +
12701 +/*----------------------------------------------------*/
12702 +/* ICS1523 PLL FeedBack Divider MSBs Definition */
12703 +/*----------------------------------------------------*/
12704 +
12705 +#define ICS_FBDM 0xF /* PLL FeedBack Divider MSBs */
12706 +
12707 +/*------------------------------------------------------------*/
12708 +/* ICS1523 Dynamic Phase Aligner Offset Bits Definition */
12709 +/*------------------------------------------------------------*/
12710 +
12711 +#define ICS_DPAOS 0x2F /* Dynamic Phase Aligner Offset */
12712 +#define ICS_FILSEL 0x80 /* Loop Filter Select */
12713 +
12714 +/*----------------------------------------------------------------*/
12715 +/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition */
12716 +/*----------------------------------------------------------------*/
12717 +
12718 +#define ICS_DPARES 0x3 /* Dynamic Phase Aligner Resolution */
12719 +#define ICS_MMREV 0xFC /* Metal Mask Revision Number */
12720 +
12721 +/*-------------------------------------------------------*/
12722 +/* ICS1523 Output Enables Register Bits Definition */
12723 +/*-------------------------------------------------------*/
12724 +
12725 +#define ICS_OEPCK 0x1 /* Output Enable for PECL PCLK Outputs */
12726 +#define ICS_OETCK 0x2 /* Output Enable for STTL CLK Output */
12727 +#define ICS_OEP2 0x4 /* Output Enable for PECL CLK/2 Outputs */
12728 +#define ICS_OET2 0x8 /* Output Enable for STTL CLK/2 Output */
12729 +#define ICS_OEF 0x10 /* Output Enable for STTL FUNC Output */
12730 +#define ICS_CLK2INV 0x20 /* CLK/2 Invert */
12731 +#define ICS_OSCL 0xC0 /* SSTL Clock Scaler */
12732 +
12733 +/*----------------------------------------------------*/
12734 +/* ICS1523 Osc Divider Register Bits Definition */
12735 +/*----------------------------------------------------*/
12736 +
12737 +#define ICS_OSCDIV 0x7F /* Oscillator Divider Modulus */
12738 +#define ICS_INSEL 0x80 /* Input Select */
12739 +
12740 +/*---------------------------------------------------*/
12741 +/* ICS1523 DPA & PLL Reset Register Definition */
12742 +/*---------------------------------------------------*/
12743 +
12744 +#define ICS_DPAR 0x0A /* DPA Reset Command */
12745 +#define ICS_PLLR 0x50 /* PLL Reset Command */
12746 +
12747 +/*------------------------------------------------*/
12748 +/* ICS1523 Chip Version Register Definition */
12749 +/*------------------------------------------------*/
12750 +
12751 +#define ICS_CHIPV 0xFF /* Chip Version */
12752 +
12753 +/*-------------------------------------------------*/
12754 +/* ICS1523 Chip Revision Register Definition */
12755 +/*-------------------------------------------------*/
12756 +
12757 +#define ICS_CHIPR 0xFF /* Chip Revision */
12758 +
12759 +/*------------------------------------------*/
12760 +/* ICS1523 Status Register Definition */
12761 +/*------------------------------------------*/
12762 +
12763 +#define ICS_DPALOCK 0x1 /* DPA Lock Status */
12764 +#define ICS_PLLLOCK 0x2 /* PLL Lock Status */
12765 +
12766 +int at91_ics1523_init(void);
12767 +
12768 +#endif /* ics1523_h */
12769 --- /dev/null
12770 +++ b/include/asm-arm/arch-at91/spi.h
12771 @@ -0,0 +1,54 @@
12772 +/*
12773 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200
12774 + *
12775 + * (c) SAN People (Pty) Ltd
12776 + *
12777 + * This program is free software; you can redistribute it and/or
12778 + * modify it under the terms of the GNU General Public License
12779 + * as published by the Free Software Foundation; either version
12780 + * 2 of the License, or (at your option) any later version.
12781 + */
12782 +
12783 +#ifndef AT91_LEGACY_SPI_H
12784 +#define AT91_LEGACY_SPI_H
12785 +
12786 +#define SPI_MAJOR 153 /* registered device number */
12787 +
12788 +#define DEFAULT_SPI_CLK 6000000
12789 +
12790 +
12791 +/* Maximum number of buffers in a single SPI transfer.
12792 + * DataFlash uses maximum of 2
12793 + * spidev interface supports up to 8.
12794 + */
12795 +#define MAX_SPI_TRANSFERS 8
12796 +#define NR_SPI_DEVICES 4 /* number of devices on SPI bus */
12797 +
12798 +/*
12799 + * Describes the buffers for a SPI transfer.
12800 + * A transmit & receive buffer must be specified for each transfer
12801 + */
12802 +struct spi_transfer_list {
12803 + void* tx[MAX_SPI_TRANSFERS]; /* transmit */
12804 + int txlen[MAX_SPI_TRANSFERS];
12805 + void* rx[MAX_SPI_TRANSFERS]; /* receive */
12806 + int rxlen[MAX_SPI_TRANSFERS];
12807 + int nr_transfers; /* number of transfers */
12808 + int curr; /* current transfer */
12809 +};
12810 +
12811 +struct spi_local {
12812 + unsigned int pcs; /* Peripheral Chip Select value */
12813 +
12814 + struct spi_transfer_list *xfers; /* current transfer list */
12815 + dma_addr_t tx, rx; /* DMA address for current transfer */
12816 + dma_addr_t txnext, rxnext; /* DMA address for next transfer */
12817 +};
12818 +
12819 +
12820 +/* Exported functions */
12821 +extern void spi_access_bus(short device);
12822 +extern void spi_release_bus(short device);
12823 +extern int spi_transfer(struct spi_transfer_list* list);
12824 +
12825 +#endif
12826 --- a/include/asm-arm/arch-at91/timex.h
12827 +++ b/include/asm-arm/arch-at91/timex.h
12828 @@ -27,14 +27,29 @@
12829
12830 #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
12831
12832 -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
12833 +#elif defined(CONFIG_ARCH_AT91SAM9260)
12834 +
12835 +#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
12836 +#define AT91SAM9_MASTER_CLOCK 90000000
12837 +#else
12838 +#define AT91SAM9_MASTER_CLOCK 99300000
12839 +#endif
12840 +
12841 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
12842 +
12843 +#elif defined(CONFIG_ARCH_AT91SAM9261)
12844
12845 #define AT91SAM9_MASTER_CLOCK 99300000
12846 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
12847
12848 #elif defined(CONFIG_ARCH_AT91SAM9263)
12849
12850 +#if defined(CONFIG_MACH_USB_A9263)
12851 +#define AT91SAM9_MASTER_CLOCK 90000000
12852 +#else
12853 #define AT91SAM9_MASTER_CLOCK 99959500
12854 +#endif
12855 +
12856 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
12857
12858 #elif defined(CONFIG_ARCH_AT91SAM9RL)
12859 --- a/include/asm-arm/arch-ks8695/devices.h
12860 +++ b/include/asm-arm/arch-ks8695/devices.h
12861 @@ -18,6 +18,11 @@
12862 extern void __init ks8695_add_device_lan(void);
12863 extern void __init ks8695_add_device_hpna(void);
12864
12865 + /* LEDs */
12866 +extern short ks8695_leds_cpu;
12867 +extern short ks8695_leds_timer;
12868 +extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
12869 +
12870 /* PCI */
12871 #define KS8695_MODE_PCI 0
12872 #define KS8695_MODE_MINIPCI 1
12873 --- a/include/linux/clk.h
12874 +++ b/include/linux/clk.h
12875 @@ -121,4 +121,24 @@
12876 */
12877 struct clk *clk_get_parent(struct clk *clk);
12878
12879 +/**
12880 + * clk_must_disable - report whether a clock's users must disable it
12881 + * @clk: one node in the clock tree
12882 + *
12883 + * This routine returns true only if the upcoming system state requires
12884 + * disabling the specified clock.
12885 + *
12886 + * It's common for platform power states to constrain certain clocks (and
12887 + * their descendants) to be unavailable, while other states allow that
12888 + * clock to be active. A platform's power states often include an "all on"
12889 + * mode; system wide sleep states like "standby" or "suspend-to-RAM"; and
12890 + * operating states which sacrifice functionality for lower power usage.
12891 + *
12892 + * The constraint value is commonly tested in device driver suspend(), to
12893 + * leave clocks active if they are needed for features like wakeup events.
12894 + * On platforms that support reduced functionality operating states, the
12895 + * constraint may also need to be tested during resume() and probe() calls.
12896 + */
12897 +int clk_must_disable(struct clk *clk);
12898 +
12899 #endif
12900 --- a/include/linux/i2c-id.h
12901 +++ b/include/linux/i2c-id.h
12902 @@ -131,6 +131,7 @@
12903
12904 /* --- PCA 9564 based algorithms */
12905 #define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */
12906 +#define I2C_HW_A_PLAT 0x1a0001 /* generic platform_bus interface */
12907
12908 /* --- PowerPC on-chip adapters */
12909 #define I2C_HW_OCP 0x120000 /* IBM on-chip I2C adapter */
12910 --- /dev/null
12911 +++ b/include/linux/usb/atmel_usba_udc.h
12912 @@ -0,0 +1,23 @@
12913 +/*
12914 +* Platform data definitions for Atmel USBA gadget driver.
12915 +*/
12916 +#ifndef __LINUX_USB_USBA_H
12917 +#define __LINUX_USB_USBA_H
12918 +
12919 +struct usba_ep_data {
12920 + char* name;
12921 + int index;
12922 + int fifo_size;
12923 + int nr_banks;
12924 + int can_dma;
12925 + int can_isoc;
12926 +};
12927 +
12928 +struct usba_platform_data {
12929 + int vbus_pin;
12930 + int num_ep;
12931 + struct usba_ep_data ep[0];
12932 +};
12933 +
12934 +#endif /* __LINUX_USB_USBA_H */
12935 +
12936 --- a/include/video/atmel_lcdc.h
12937 +++ b/include/video/atmel_lcdc.h
12938 @@ -39,6 +39,7 @@
12939 u8 bl_power;
12940 #endif
12941 bool lcdcon_is_backlight;
12942 + u8 saved_lcdcon;
12943
12944 u8 default_bpp;
12945 unsigned int default_lcdcon2;
12946 --- a/sound/soc/at91/eti_b1_wm8731.c
12947 +++ b/sound/soc/at91/eti_b1_wm8731.c
12948 @@ -33,8 +33,7 @@
12949 #include <sound/soc.h>
12950 #include <sound/soc-dapm.h>
12951
12952 -#include <asm/arch/hardware.h>
12953 -#include <asm/arch/at91_pio.h>
12954 +#include <asm/hardware.h>
12955 #include <asm/arch/gpio.h>
12956
12957 #include "../codecs/wm8731.h"
12958 @@ -47,13 +46,6 @@
12959 #define DBG(x...)
12960 #endif
12961
12962 -#define AT91_PIO_TF1 (1 << (AT91_PIN_PB6 - PIN_BASE) % 32)
12963 -#define AT91_PIO_TK1 (1 << (AT91_PIN_PB7 - PIN_BASE) % 32)
12964 -#define AT91_PIO_TD1 (1 << (AT91_PIN_PB8 - PIN_BASE) % 32)
12965 -#define AT91_PIO_RD1 (1 << (AT91_PIN_PB9 - PIN_BASE) % 32)
12966 -#define AT91_PIO_RK1 (1 << (AT91_PIN_PB10 - PIN_BASE) % 32)
12967 -#define AT91_PIO_RF1 (1 << (AT91_PIN_PB11 - PIN_BASE) % 32)
12968 -
12969 static struct clk *pck1_clk;
12970 static struct clk *pllb_clk;
12971
12972 @@ -276,7 +268,6 @@
12973 static int __init eti_b1_init(void)
12974 {
12975 int ret;
12976 - u32 ssc_pio_lines;
12977 struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
12978
12979 if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) {
12980 @@ -310,19 +301,12 @@
12981 goto fail_io_unmap;
12982 }
12983
12984 - ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1
12985 - | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1;
12986 -
12987 - /* Reset all PIO registers and assign lines to peripheral A */
12988 - at91_sys_write(AT91_PIOB + PIO_PDR, ssc_pio_lines);
12989 - at91_sys_write(AT91_PIOB + PIO_ODR, ssc_pio_lines);
12990 - at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines);
12991 - at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines);
12992 - at91_sys_write(AT91_PIOB + PIO_IDR, ssc_pio_lines);
12993 - at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines);
12994 - at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines);
12995 - at91_sys_write(AT91_PIOB + PIO_ASR, ssc_pio_lines);
12996 - at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines);
12997 + at91_set_A_periph(AT91_PIN_PB6, 0); /* TF1 */
12998 + at91_set_A_periph(AT91_PIN_PB7, 0); /* TK1 */
12999 + at91_set_A_periph(AT91_PIN_PB8, 0); /* TD1 */
13000 + at91_set_A_periph(AT91_PIN_PB9, 0); /* RD1 */
13001 +/* at91_set_A_periph(AT91_PIN_PB10, 0);*/ /* RK1 */
13002 + at91_set_A_periph(AT91_PIN_PB11, 0); /* RF1 */
13003
13004 /*
13005 * Set PCK1 parent to PLLB and its rate to 12 Mhz.
13006 --- a/sound/spi/at73c213.c
13007 +++ b/sound/spi/at73c213.c
13008 @@ -114,7 +114,11 @@
13009 static struct snd_pcm_hardware snd_at73c213_playback_hw = {
13010 .info = SNDRV_PCM_INFO_INTERLEAVED |
13011 SNDRV_PCM_INFO_BLOCK_TRANSFER,
13012 +#ifdef __BIG_ENDIAN
13013 .formats = SNDRV_PCM_FMTBIT_S16_BE,
13014 +#else
13015 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
13016 +#endif
13017 .rates = SNDRV_PCM_RATE_CONTINUOUS,
13018 .rate_min = 8000, /* Replaced by chip->bitrate later. */
13019 .rate_max = 50000, /* Replaced by chip->bitrate later. */
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