2 * HND SiliconBackplane MIPS core software interface.
4 * Copyright 2006, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
18 extern void sb_mips_init(sb_t
*sbh
, uint shirq_map_base
);
19 extern bool sb_mips_setclock(sb_t
*sbh
, uint32 mipsclock
, uint32 sbclock
, uint32 pciclock
);
20 extern void enable_pfc(uint32 mode
);
21 extern uint32
sb_memc_get_ncdl(sb_t
*sbh
);
23 #if defined(BCMPERFSTATS)
24 /* enable counting - exclusive version. Only one set of counters allowed at a time */
25 extern void hndmips_perf_instrcount_enable(void);
26 extern void hndmips_perf_icachecount_enable(void);
27 extern void hndmips_perf_dcachecount_enable(void);
28 /* start and stop counting */
29 #define hndmips_perf_start01() \
30 MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
31 #define hndmips_perf_stop01() \
32 MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
33 /* retrieve coutners - counters *decrement* */
34 #define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
35 #define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
36 #define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
37 /* enable counting - modular version. Each counters can be enabled separately. */
38 extern void hndmips_perf_icache_hit_enable(void);
39 extern void hndmips_perf_icache_miss_enable(void);
40 extern uint32
hndmips_perf_read_instrcount(void);
41 extern uint32
hndmips_perf_read_cache_miss(void);
42 extern uint32
hndmips_perf_read_cache_hit(void);
43 #endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
45 #endif /* _hndmips_h_ */
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