fix pci init for brcm-2.4 with atheros wifi cards
[openwrt.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / include / osl.h
1 #ifndef __osl_h
2 #define __osl_h
3
4 #include <linux/delay.h>
5 #include <typedefs.h>
6 #include <linuxver.h>
7 #include <bcmutils.h>
8 #include <pcicfg.h>
9
10 #define ASSERT(n)
11
12 /* Pkttag flag should be part of public information */
13 typedef struct {
14 bool pkttag;
15 uint pktalloced; /* Number of allocated packet buffers */
16 void *tx_fn;
17 void *tx_ctx;
18 } osl_pubinfo_t;
19
20 struct osl_info {
21 osl_pubinfo_t pub;
22 uint magic;
23 void *pdev;
24 uint malloced;
25 uint failed;
26 void *dbgmem_list;
27 };
28
29 typedef struct osl_info osl_t;
30
31 #define PCI_CFG_RETRY 10
32
33 /* map/unmap direction */
34 #define DMA_TX 1 /* TX direction for DMA */
35 #define DMA_RX 2 /* RX direction for DMA */
36
37 #define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
38 #define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
39 #define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
40
41 /* bcopy, bcmp, and bzero */
42 #define bcopy(src, dst, len) memcpy((dst), (src), (len))
43 #define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
44 #define bzero(b, len) memset((b), '\0', (len))
45
46 /* uncached virtual address */
47 #ifdef mips
48 #define OSL_UNCACHED(va) KSEG1ADDR((va))
49 #include <asm/addrspace.h>
50 #else
51 #define OSL_UNCACHED(va) (va)
52 #endif /* mips */
53
54
55 #ifndef IL_BIGENDIAN
56 #define R_REG(osh, r) (\
57 sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
58 sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
59 readl((volatile uint32*)(r)) \
60 )
61 #define W_REG(osh, r, v) do { \
62 switch (sizeof(*(r))) { \
63 case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
64 case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
65 case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
66 } \
67 } while (0)
68 #else /* IL_BIGENDIAN */
69 #define R_REG(osh, r) ({ \
70 __typeof(*(r)) __osl_v; \
71 switch (sizeof(*(r))) { \
72 case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
73 case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
74 case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
75 } \
76 __osl_v; \
77 })
78 #define W_REG(osh, r, v) do { \
79 switch (sizeof(*(r))) { \
80 case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
81 case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
82 case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
83 } \
84 } while (0)
85 #endif /* IL_BIGENDIAN */
86
87 /* dereference an address that may cause a bus exception */
88 #define BUSPROBE(val, addr) get_dbe((val), (addr))
89 #include <asm/paccess.h>
90
91 /* map/unmap physical to virtual I/O */
92 #define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
93 #define REG_UNMAP(va) iounmap((void *)(va))
94
95 /* shared (dma-able) memory access macros */
96 #define R_SM(r) *(r)
97 #define W_SM(r, v) (*(r) = (v))
98 #define BZERO_SM(r, len) memset((r), '\0', (len))
99
100 #define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
101 #define MFREE(osh, addr, size) kfree((addr))
102 #define MALLOCED(osh) (0)
103
104 #define osl_delay OSL_DELAY
105 static inline void OSL_DELAY(uint usec)
106 {
107 uint d;
108
109 while (usec > 0) {
110 d = MIN(usec, 1000);
111 udelay(d);
112 usec -= d;
113 }
114 }
115
116 static inline void
117 bcm_mdelay(uint ms)
118 {
119 uint i;
120
121 for (i = 0; i < ms; i++) {
122 OSL_DELAY(1000);
123 }
124 }
125
126
127 #define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
128 #define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
129
130 #define OSL_PCI_READ_CONFIG(osh, offset, size) \
131 osl_pci_read_config((osh), (offset), (size))
132
133 static inline uint32
134 osl_pci_read_config(osl_t *osh, uint offset, uint size)
135 {
136 uint val;
137 uint retry = PCI_CFG_RETRY;
138
139 do {
140 pci_read_config_dword(osh->pdev, offset, &val);
141 if (val != 0xffffffff)
142 break;
143 } while (retry--);
144
145 return (val);
146 }
147
148 #define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
149 osl_pci_write_config((osh), (offset), (size), (val))
150 static inline void
151 osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
152 {
153 uint retry = PCI_CFG_RETRY;
154
155 do {
156 pci_write_config_dword(osh->pdev, offset, val);
157 if (offset != PCI_BAR0_WIN)
158 break;
159 if (osl_pci_read_config(osh, offset, size) == val)
160 break;
161 } while (retry--);
162 }
163
164
165 /* return bus # for the pci device pointed by osh->pdev */
166 #define OSL_PCI_BUS(osh) osl_pci_bus(osh)
167 static inline uint
168 osl_pci_bus(osl_t *osh)
169 {
170 return ((struct pci_dev *)osh->pdev)->bus->number;
171 }
172
173 /* return slot # for the pci device pointed by osh->pdev */
174 #define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
175 static inline uint
176 osl_pci_slot(osl_t *osh)
177 {
178 return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
179 }
180
181 #endif
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