target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h

   1 /*
   2  * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
   3  *
   4  * Copyright 2006, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
  13  */
  14
  15 #ifndef _SBPCMCIA_H
  16 #define _SBPCMCIA_H
  17
  18
  19 /* All the addresses that are offsets in attribute space are divided
  20  * by two to account for the fact that odd bytes are invalid in
  21  * attribute space and our read/write routines make the space appear
  22  * as if they didn't exist. Still we want to show the original numbers
  23  * as documented in the hnd_pcmcia core manual.
  24  */
  25
  26 /* PCMCIA Function Configuration Registers */
  27 #define PCMCIA_FCR              (0x700 / 2)
  28
  29 #define FCR0_OFF                0
  30 #define FCR1_OFF                (0x40 / 2)
  31 #define FCR2_OFF                (0x80 / 2)
  32 #define FCR3_OFF                (0xc0 / 2)
  33
  34 #define PCMCIA_FCR0             (0x700 / 2)
  35 #define PCMCIA_FCR1             (0x740 / 2)
  36 #define PCMCIA_FCR2             (0x780 / 2)
  37 #define PCMCIA_FCR3             (0x7c0 / 2)
  38
  39 /* Standard PCMCIA FCR registers */
  40
  41 #define PCMCIA_COR              0
  42
  43 #define COR_RST                 0x80
  44 #define COR_LEV                 0x40
  45 #define COR_IRQEN               0x04
  46 #define COR_BLREN               0x01
  47 #define COR_FUNEN               0x01
  48
  49
  50 #define PCICIA_FCSR             (2 / 2)
  51 #define PCICIA_PRR              (4 / 2)
  52 #define PCICIA_SCR              (6 / 2)
  53 #define PCICIA_ESR              (8 / 2)
  54
  55
  56 #define PCM_MEMOFF              0x0000
  57 #define F0_MEMOFF               0x1000
  58 #define F1_MEMOFF               0x2000
  59 #define F2_MEMOFF               0x3000
  60 #define F3_MEMOFF               0x4000
  61
  62 /* Memory base in the function fcr's */
  63 #define MEM_ADDR0               (0x728 / 2)
  64 #define MEM_ADDR1               (0x72a / 2)
  65 #define MEM_ADDR2               (0x72c / 2)
  66
  67 /* PCMCIA base plus Srom access in fcr0: */
  68 #define PCMCIA_ADDR0            (0x072e / 2)
  69 #define PCMCIA_ADDR1            (0x0730 / 2)
  70 #define PCMCIA_ADDR2            (0x0732 / 2)
  71
  72 #define MEM_SEG                 (0x0734 / 2)
  73 #define SROM_CS                 (0x0736 / 2)
  74 #define SROM_DATAL              (0x0738 / 2)
  75 #define SROM_DATAH              (0x073a / 2)
  76 #define SROM_ADDRL              (0x073c / 2)
  77 #define SROM_ADDRH              (0x073e / 2)
  78
  79 /*  Values for srom_cs: */
  80 #define SROM_IDLE               0
  81 #define SROM_WRITE              1
  82 #define SROM_READ               2
  83 #define SROM_WEN                4
  84 #define SROM_WDS                7
  85 #define SROM_DONE               8
  86
  87 /* CIS stuff */
  88
  89 /* The CIS stops where the FCRs start */
  90 #define CIS_SIZE                PCMCIA_FCR
  91
  92 /* Standard tuples we know about */
  93
  94 #define CISTPL_MANFID           0x20            /* Manufacturer and device id */
  95 #define CISTPL_FUNCE            0x22            /* Function extensions */
  96 #define CISTPL_CFTABLE          0x1b            /* Config table entry */
  97
  98 /* Function extensions for LANs */
  99
 100 #define LAN_TECH                1               /* Technology type */
 101 #define LAN_SPEED               2               /* Raw bit rate */
 102 #define LAN_MEDIA               3               /* Transmission media */
 103 #define LAN_NID                 4               /* Node identification (aka MAC addr) */
 104 #define LAN_CONN                5               /* Connector standard */
 105
 106
 107 /* CFTable */
 108 #define CFTABLE_REGWIN_2K       0x08            /* 2k reg windows size */
 109 #define CFTABLE_REGWIN_4K       0x10            /* 4k reg windows size */
 110 #define CFTABLE_REGWIN_8K       0x20            /* 8k reg windows size */
 111
 112 /* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
 113  * take one for HNBU, and use "extensions" (a la FUNCE) within it.
 114  */
 115
 116 #define CISTPL_BRCM_HNBU        0x80
 117
 118 /* Subtypes of BRCM_HNBU: */
 119
 120 #define HNBU_SROMREV            0x00            /* A byte with sromrev, 1 if not present */
 121 #define HNBU_CHIPID             0x01            /* Two 16bit values: PCI vendor & device id */
 122 #define HNBU_BOARDREV           0x02            /* One byte board revision */
 123 #define HNBU_PAPARMS            0x03            /* PA parameters: 8 (sromrev == 1)
 124                                                  * or 9 (sromrev > 1) bytes
 125                                                  */
 126 #define HNBU_OEM                0x04            /* Eight bytes OEM data (sromrev == 1) */
 127 #define HNBU_CC                 0x05            /* Default country code (sromrev == 1) */
 128 #define HNBU_AA                 0x06            /* Antennas available */
 129 #define HNBU_AG                 0x07            /* Antenna gain */
 130 #define HNBU_BOARDFLAGS         0x08            /* board flags (2 or 4 bytes) */
 131 #define HNBU_LEDS               0x09            /* LED set */
 132 #define HNBU_CCODE              0x0a            /* Country code (2 bytes ascii + 1 byte cctl)
 133                                                  * in rev 2
 134                                                  */
 135 #define HNBU_CCKPO              0x0b            /* 2 byte cck power offsets in rev 3 */
 136 #define HNBU_OFDMPO             0x0c            /* 4 byte 11g ofdm power offsets in rev 3 */
 137 #define HNBU_GPIOTIMER          0x0d            /* 2 bytes with on/off values in rev 3 */
 138
 139
 140 /* sbtmstatelow */
 141 #define SBTML_INT_ACK           0x40000         /* ack the sb interrupt */
 142 #define SBTML_INT_EN            0x20000         /* enable sb interrupt */
 143
 144 /* sbtmstatehigh */
 145 #define SBTMH_INT_STATUS        0x40000         /* sb interrupt status */
 146
 147 #endif  /* _SBPCMCIA_H */