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[openwrt.git] / target / linux / brcm47xx / patches-3.2 / 030-bcm47xx-bcma-nandflash.patch
1 --- a/arch/mips/bcm47xx/Kconfig
2 +++ b/arch/mips/bcm47xx/Kconfig
3 @@ -24,6 +24,7 @@ config BCM47XX_BCMA
4 select BCMA_DRIVER_MIPS
5 select BCMA_DRIVER_PCI_HOSTMODE if PCI
6 select BCMA_SFLASH
7 + select BCMA_NFLASH
8 default y
9 help
10 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
11 --- a/arch/mips/bcm47xx/bus.c
12 +++ b/arch/mips/bcm47xx/bus.c
13 @@ -2,6 +2,7 @@
14 * BCM947xx nvram variable access
15 *
16 * Copyright (C) 2011 Hauke Mehrtens <hauke@hauke-m.de>
17 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 @@ -80,3 +81,9 @@ void bcm47xx_sflash_struct_ssb_init(stru
22 sflash->numblocks = scc->sflash.numblocks;
23 sflash->size = scc->sflash.size;
24 }
25 +
26 +void bcm47xx_nflash_struct_bcma_init(struct bcm47xx_nflash *nflash, struct bcma_drv_cc *bcc)
27 +{
28 + nflash->nflash_type = BCM47XX_BUS_TYPE_BCMA;
29 + nflash->bcc = bcc;
30 +}
31 --- a/arch/mips/bcm47xx/nvram.c
32 +++ b/arch/mips/bcm47xx/nvram.c
33 @@ -4,6 +4,7 @@
34 * Copyright (C) 2005 Broadcom Corporation
35 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
36 * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
37 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
38 *
39 * This program is free software; you can redistribute it and/or modify it
40 * under the terms of the GNU General Public License as published by the
41 @@ -21,6 +22,7 @@
42 #include <asm/mach-bcm47xx/nvram.h>
43 #include <asm/mach-bcm47xx/bcm47xx.h>
44 #include <asm/mach-bcm47xx/bus.h>
45 +#include <linux/mtd/bcm47xx_nand.h>
46
47 static char nvram_buf[NVRAM_SPACE];
48
49 @@ -134,6 +136,51 @@ found:
50 return 0;
51 }
52
53 +static int early_nvram_init_nflash(void)
54 +{
55 + struct nvram_header *header;
56 + u32 off;
57 + int ret;
58 + int len;
59 + u32 flash_size = bcm47xx_nflash.size;
60 + u8 tmpbuf[NFL_SECTOR_SIZE];
61 + int i;
62 + u32 *src, *dst;
63 +
64 + /* check if the struct is already initilized */
65 + if (!flash_size)
66 + return -1;
67 +
68 + cfe_env = 0;
69 +
70 + off = FLASH_MIN;
71 + while (off <= flash_size) {
72 + ret = bcma_nflash_read(bcm47xx_nflash.bcc, off, NFL_SECTOR_SIZE, tmpbuf);
73 + if (ret != NFL_SECTOR_SIZE)
74 + goto done;
75 + header = (struct nvram_header *)tmpbuf;
76 + if (header->magic == NVRAM_HEADER)
77 + goto found;
78 + off <<= 1;
79 + }
80 +
81 + ret = -1;
82 + goto done;
83 +
84 +found:
85 + len = header->len;
86 + header = (struct nvram_header *) KSEG1ADDR(NAND_FLASH1 + off);
87 + src = (u32 *) header;
88 + dst = (u32 *) nvram_buf;
89 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
90 + *dst++ = *src++;
91 + for (; i < len && i < NVRAM_SPACE; i += 4)
92 + *dst++ = *src++;
93 + ret = 0;
94 +done:
95 + return ret;
96 +}
97 +
98 #ifdef CONFIG_BCM47XX_SSB
99 static void early_nvram_init_ssb(void)
100 {
101 @@ -164,6 +211,10 @@ static void early_nvram_init_bcma(void)
102 err = early_nvram_init_sflash();
103 if (err < 0)
104 printk(KERN_WARNING "can not read from flash: %i\n", err);
105 + case BCMA_NFLASH:
106 + err = early_nvram_init_nflash();
107 + if (err < 0)
108 + printk(KERN_WARNING "can not read from nflash: %i\n", err);
109 default:
110 printk(KERN_WARNING "unknow flash type\n");
111 }
112 --- a/arch/mips/bcm47xx/setup.c
113 +++ b/arch/mips/bcm47xx/setup.c
114 @@ -4,6 +4,7 @@
115 * Copyright (C) 2006 Michael Buesch <m@bues.ch>
116 * Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
117 * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
118 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
119 *
120 * This program is free software; you can redistribute it and/or modify it
121 * under the terms of the GNU General Public License as published by the
122 @@ -46,6 +47,7 @@ enum bcm47xx_bus_type bcm47xx_bus_type;
123 EXPORT_SYMBOL(bcm47xx_bus_type);
124
125 struct bcm47xx_sflash bcm47xx_sflash;
126 +struct bcm47xx_nflash bcm47xx_nflash;
127
128 static struct resource bcm47xx_pflash_resource = {
129 .name = "bcm47xx_pflash",
130 @@ -73,6 +75,19 @@ static struct platform_device bcm47xx_sf
131 .num_resources = 1,
132 };
133
134 +static struct resource bcm47xx_nflash_resource = {
135 + .name = "bcm47xx_nflash",
136 + .start = 0,
137 + .end = 0,
138 + .flags = 0,
139 +};
140 +
141 +static struct platform_device bcm47xx_nflash_dev = {
142 + .name = "bcm47xx_nflash",
143 + .resource = &bcm47xx_nflash_resource,
144 + .num_resources = 1,
145 +};
146 +
147 static void bcm47xx_machine_restart(char *command)
148 {
149 printk(KERN_ALERT "Please stand by while rebooting the system...\n");
150 @@ -369,6 +384,9 @@ static void __init bcm47xx_register_bcma
151
152 if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_SFLASH)
153 bcm47xx_sflash_struct_bcma_init(&bcm47xx_sflash, &bcm47xx_bus.bcma.bus.drv_cc);
154 +
155 + if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_NFLASH)
156 + bcm47xx_nflash_struct_bcma_init(&bcm47xx_nflash, &bcm47xx_bus.bcma.bus.drv_cc);
157 }
158
159 static int __init bcm47xx_register_flash_bcma(void)
160 @@ -383,6 +401,9 @@ static int __init bcm47xx_register_flash
161 case BCMA_SFLASH:
162 bcm47xx_sflash_dev.dev.platform_data = &bcm47xx_sflash;
163 return platform_device_register(&bcm47xx_sflash_dev);
164 + case BCMA_NFLASH:
165 + bcm47xx_nflash_dev.dev.platform_data = &bcm47xx_nflash;
166 + return platform_device_register(&bcm47xx_nflash_dev);
167 default:
168 printk(KERN_ERR "No flash device found\n");
169 return -1;
170 --- a/arch/mips/include/asm/mach-bcm47xx/bus.h
171 +++ b/arch/mips/include/asm/mach-bcm47xx/bus.h
172 @@ -2,6 +2,7 @@
173 * BCM947xx nvram variable access
174 *
175 * Copyright (C) 2011 Hauke Mehrtens <hauke@hauke-m.de>
176 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
177 *
178 * This program is free software; you can redistribute it and/or modify it
179 * under the terms of the GNU General Public License as published by the
180 @@ -13,6 +14,7 @@
181 #include <linux/bcma/bcma.h>
182 #include <linux/mtd/mtd.h>
183 #include <bcm47xx.h>
184 +#include <linux/mtd/nand.h>
185
186 struct bcm47xx_sflash {
187 enum bcm47xx_bus_type sflash_type;
188 @@ -29,11 +31,24 @@ struct bcm47xx_sflash {
189 u32 blocksize; /* Block size */
190 u32 numblocks; /* Number of blocks */
191 u32 size; /* Total size in bytes */
192 -
193 - struct mtd_info *mtd;
194 };
195
196 void bcm47xx_sflash_struct_bcma_init(struct bcm47xx_sflash *sflash, struct bcma_drv_cc *bcc);
197 void bcm47xx_sflash_struct_ssb_init(struct bcm47xx_sflash *sflash, struct ssb_chipcommon *scc);
198
199 extern struct bcm47xx_sflash bcm47xx_sflash;
200 +
201 +struct bcm47xx_nflash {
202 + enum bcm47xx_bus_type nflash_type;
203 + struct bcma_drv_cc *bcc;
204 +
205 + u32 size; /* Total size in bytes */
206 + u32 next_opcode; /* Next expected command from upper NAND layer */
207 +
208 + struct mtd_info mtd;
209 + struct nand_chip nand;
210 +};
211 +
212 +void bcm47xx_nflash_struct_bcma_init(struct bcm47xx_nflash *nflash, struct bcma_drv_cc *bcc);
213 +
214 +extern struct bcm47xx_nflash bcm47xx_nflash;
215 --- a/drivers/bcma/Kconfig
216 +++ b/drivers/bcma/Kconfig
217 @@ -43,6 +43,11 @@ config BCMA_SFLASH
218 depends on BCMA_DRIVER_MIPS
219 default y
220
221 +config BCMA_NFLASH
222 + bool
223 + depends on BCMA_DRIVER_MIPS
224 + default y
225 +
226 config BCMA_DRIVER_MIPS
227 bool "BCMA Broadcom MIPS core driver"
228 depends on BCMA && MIPS
229 --- a/drivers/bcma/Makefile
230 +++ b/drivers/bcma/Makefile
231 @@ -1,6 +1,7 @@
232 bcma-y += main.o scan.o core.o sprom.o
233 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
234 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
235 +bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
236 bcma-y += driver_pci.o
237 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
238 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
239 --- a/drivers/bcma/bcma_private.h
240 +++ b/drivers/bcma/bcma_private.h
241 @@ -46,6 +46,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
242 int bcma_sflash_init(struct bcma_drv_cc *cc);
243 #endif /* CONFIG_BCMA_SFLASH */
244
245 +#ifdef CONFIG_BCMA_NFLASH
246 +/* driver_chipcommon_nflash.c */
247 +int bcma_nflash_init(struct bcma_drv_cc *cc);
248 +#endif /* CONFIG_BCMA_NFLASH */
249 +
250 #ifdef CONFIG_BCMA_HOST_PCI
251 /* host_pci.c */
252 extern int __init bcma_host_pci_init(void);
253 --- /dev/null
254 +++ b/drivers/bcma/driver_chipcommon_nflash.c
255 @@ -0,0 +1,154 @@
256 +/*
257 + * BCMA nand flash interface
258 + *
259 + * Copyright 2011, Tathagata Das <tathagata@alumnux.com>
260 + * Copyright 2010, Broadcom Corporation
261 + *
262 + * Licensed under the GNU/GPL. See COPYING for details.
263 + */
264 +
265 +#include <linux/bcma/bcma.h>
266 +#include <linux/bcma/bcma_driver_chipcommon.h>
267 +#include <linux/delay.h>
268 +#include <linux/mtd/bcm47xx_nand.h>
269 +#include <linux/mtd/nand.h>
270 +
271 +#include "bcma_private.h"
272 +
273 +/* Issue a nand flash command */
274 +static inline void bcma_nflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
275 +{
276 + bcma_cc_write32(cc, NAND_CMD_START, opcode);
277 + bcma_cc_read32(cc, NAND_CMD_START);
278 +}
279 +
280 +/* Check offset and length */
281 +static int bcma_nflash_offset_is_valid(struct bcma_drv_cc *cc, u32 offset, u32 len, u32 mask)
282 +{
283 + if ((offset & mask) != 0 || (len & mask) != 0) {
284 + pr_err("%s(): Address is not aligned. offset: %x, len: %x, mask: %x\n", __func__, offset, len, mask);
285 + return 1;
286 + }
287 +
288 + if ((((offset + len) >> 20) >= cc->nflash.size) &&
289 + (((offset + len) & ((1 << 20) - 1)) != 0)) {
290 + pr_err("%s(): Address is outside Flash memory region. offset: %x, len: %x, mask: %x\n", __func__, offset, len, mask);
291 + return 1;
292 + }
293 +
294 + return 0;
295 +}
296 +
297 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
298 +int bcma_nflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf)
299 +{
300 + u32 mask;
301 + int i;
302 + u32 *to, val, res;
303 +
304 + mask = NFL_SECTOR_SIZE - 1;
305 + if (bcma_nflash_offset_is_valid(cc, offset, len, mask))
306 + return 0;
307 +
308 + to = (u32 *)buf;
309 + res = len;
310 + while (res > 0) {
311 + bcma_cc_write32(cc, NAND_CMD_ADDR, offset);
312 + bcma_nflash_cmd(cc, NCMD_PAGE_RD);
313 + if (bcma_nflash_poll(cc) < 0)
314 + break;
315 + val = bcma_cc_read32(cc, NAND_INTFC_STATUS);
316 + if ((val & NIST_CACHE_VALID) == 0)
317 + break;
318 + bcma_cc_write32(cc, NAND_CACHE_ADDR, 0);
319 + for (i = 0; i < NFL_SECTOR_SIZE; i += 4, to++) {
320 + *to = bcma_cc_read32(cc, NAND_CACHE_DATA);
321 + }
322 + res -= NFL_SECTOR_SIZE;
323 + offset += NFL_SECTOR_SIZE;
324 + }
325 + return (len - res);
326 +}
327 +
328 +#define NF_RETRIES 1000000
329 +
330 +/* Poll for command completion. Returns zero when complete. */
331 +int bcma_nflash_poll(struct bcma_drv_cc *cc)
332 +{
333 + u32 retries = NF_RETRIES;
334 + u32 pollmask = NIST_CTRL_READY|NIST_FLASH_READY;
335 + u32 mask;
336 +
337 + while (retries--) {
338 + mask = bcma_cc_read32(cc, NAND_INTFC_STATUS) & pollmask;
339 + if (mask == pollmask)
340 + return 0;
341 + cpu_relax();
342 + }
343 +
344 + if (!retries) {
345 + pr_err("bcma_nflash_poll: not ready\n");
346 + return -1;
347 + }
348 +
349 + return 0;
350 +}
351 +
352 +/* Write len bytes starting at offset into buf. Returns success (0) or failure (!0).
353 + * Should poll for completion.
354 + */
355 +int bcma_nflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
356 + const u8 *buf)
357 +{
358 + u32 mask;
359 + int i;
360 + u32 *from, res, reg;
361 +
362 + mask = cc->nflash.pagesize - 1;
363 + if (bcma_nflash_offset_is_valid(cc, offset, len, mask))
364 + return 1;
365 +
366 + /* disable partial page enable */
367 + reg = bcma_cc_read32(cc, NAND_ACC_CONTROL);
368 + reg &= ~NAC_PARTIAL_PAGE_EN;
369 + bcma_cc_write32(cc, NAND_ACC_CONTROL, reg);
370 +
371 + from = (u32 *)buf;
372 + res = len;
373 + while (res > 0) {
374 + bcma_cc_write32(cc, NAND_CACHE_ADDR, 0);
375 + for (i = 0; i < cc->nflash.pagesize; i += 4, from++) {
376 + if (i % 512 == 0)
377 + bcma_cc_write32(cc, NAND_CMD_ADDR, i);
378 + bcma_cc_write32(cc, NAND_CACHE_DATA, *from);
379 + }
380 + bcma_cc_write32(cc, NAND_CMD_ADDR, offset + cc->nflash.pagesize - 512);
381 + bcma_nflash_cmd(cc, NCMD_PAGE_PROG);
382 + if (bcma_nflash_poll(cc) < 0)
383 + break;
384 + res -= cc->nflash.pagesize;
385 + offset += cc->nflash.pagesize;
386 + }
387 +
388 + if (res <= 0)
389 + return 0;
390 + else
391 + return (len - res);
392 +}
393 +
394 +/* Erase a region. Returns success (0) or failure (-1).
395 + * Poll for completion.
396 + */
397 +int bcma_nflash_erase(struct bcma_drv_cc *cc, u32 offset)
398 +{
399 + if ((offset >> 20) >= cc->nflash.size)
400 + return -1;
401 + if ((offset & (cc->nflash.blocksize - 1)) != 0)
402 + return -1;
403 +
404 + bcma_cc_write32(cc, NAND_CMD_ADDR, offset);
405 + bcma_nflash_cmd(cc, NCMD_BLOCK_ERASE);
406 + if (bcma_nflash_poll(cc) < 0)
407 + return -1;
408 + return 0;
409 +}
410 --- a/drivers/bcma/driver_mips.c
411 +++ b/drivers/bcma/driver_mips.c
412 @@ -6,6 +6,7 @@
413 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
414 * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
415 * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
416 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
417 *
418 * Licensed under the GNU/GPL. See COPYING for details.
419 */
420 @@ -182,6 +183,17 @@ static void bcma_core_mips_flash_detect(
421 {
422 struct bcma_bus *bus = mcore->core->bus;
423
424 + if (bus->drv_cc.core->id.rev == 38
425 + && (bus->drv_cc.status & (1 << 4)) != 0) {
426 +#ifdef CONFIG_BCMA_NFLASH
427 + pr_info("found nand flash.\n");
428 + bus->drv_cc.flash_type = BCMA_NFLASH;
429 +#else
430 + pr_info("NAND flash not supported.\n");
431 +#endif
432 + return;
433 + }
434 +
435 switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
436 case BCMA_CC_FLASHT_STSER:
437 case BCMA_CC_FLASHT_ATSER:
438 --- a/drivers/mtd/nand/Kconfig
439 +++ b/drivers/mtd/nand/Kconfig
440 @@ -537,4 +537,12 @@ config MTD_NAND_FSMC
441 Enables support for NAND Flash chips on the ST Microelectronics
442 Flexible Static Memory Controller (FSMC)
443
444 +config MTD_NAND_BCM47XX
445 + tristate "bcm47xx nand flash support"
446 + default y
447 + depends on BCM47XX
448 + select MTD_PARTITIONS
449 + help
450 + Support for bcm47xx nand flash
451 +
452 endif # MTD_NAND
453 --- a/drivers/mtd/nand/Makefile
454 +++ b/drivers/mtd/nand/Makefile
455 @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mp
456 obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
457 obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
458 obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
459 +obj-$(CONFIG_MTD_NAND_BCM47XX) += bcm47xx_nand.o
460
461 nand-objs := nand_base.o nand_bbt.o
462 --- /dev/null
463 +++ b/drivers/mtd/nand/bcm47xx_nand.c
464 @@ -0,0 +1,506 @@
465 +/*
466 + * BCMA nand flash interface
467 + *
468 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
469 + * Copyright 2010, Broadcom Corporation
470 + *
471 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
472 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
473 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
474 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
475 + *
476 + */
477 +
478 +#define pr_fmt(fmt) "bcm47xx_nflash: " fmt
479 +#include <linux/module.h>
480 +#include <linux/slab.h>
481 +#include <linux/ioport.h>
482 +#include <linux/sched.h>
483 +#include <linux/mtd/mtd.h>
484 +#include <linux/mtd/map.h>
485 +#include <linux/mtd/partitions.h>
486 +#include <linux/errno.h>
487 +#include <linux/delay.h>
488 +#include <linux/platform_device.h>
489 +#include <bcm47xx.h>
490 +#include <bus.h>
491 +#include <linux/cramfs_fs.h>
492 +#include <linux/romfs_fs.h>
493 +#include <linux/magic.h>
494 +#include <linux/byteorder/generic.h>
495 +#include <linux/mtd/bcm47xx_nand.h>
496 +#include <linux/mtd/nand.h>
497 +
498 +static int bcm47xx_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip);
499 +static int bcm47xx_erase(struct mtd_info *mtd, unsigned int addr, unsigned int len);
500 +
501 +/* Private Global variable */
502 +static u32 read_offset = 0;
503 +static u32 write_offset;
504 +
505 +static int
506 +nflash_mtd_poll(struct bcm47xx_nflash *nflash, unsigned int offset, int timeout)
507 +{
508 + unsigned long now = jiffies;
509 + int ret = 0;
510 +
511 + for (;;) {
512 + if (!bcma_nflash_poll(nflash->bcc)) {
513 + ret = 0;
514 + break;
515 + }
516 + if (time_after(jiffies, now + timeout)) {
517 + pr_err("timeout while polling\n");
518 + ret = -ETIMEDOUT;
519 + break;
520 + }
521 + udelay(1);
522 + }
523 +
524 + return ret;
525 +}
526 +
527 +static int
528 +bcm47xx_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
529 +{
530 + struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
531 + struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
532 + int bytes, ret = 0;
533 + u32 extra = 0;
534 + u8 *tmpbuf = NULL;
535 + int size;
536 + u32 offset, blocksize, mask, off;
537 + u32 skip_bytes = 0;
538 + int need_copy = 0;
539 + u8 *ptr = NULL;
540 +
541 + /* Check address range */
542 + if (!len)
543 + return 0;
544 + if ((from + len) > mtd->size)
545 + return -EINVAL;
546 + offset = from;
547 + if ((offset & (NFL_SECTOR_SIZE - 1)) != 0) {
548 + extra = offset & (NFL_SECTOR_SIZE - 1);
549 + offset -= extra;
550 + len += extra;
551 + need_copy = 1;
552 + }
553 + size = (len + (NFL_SECTOR_SIZE - 1)) & ~(NFL_SECTOR_SIZE - 1);
554 + if (size != len) {
555 + need_copy = 1;
556 + }
557 + if (!need_copy) {
558 + ptr = buf;
559 + } else {
560 + tmpbuf = (u8 *)kmalloc(size, GFP_KERNEL);
561 + ptr = tmpbuf;
562 + }
563 +
564 + blocksize = mtd->erasesize;
565 + mask = blocksize - 1;
566 + *retlen = 0;
567 + while (len > 0) {
568 + off = offset + skip_bytes;
569 + if ((bytes = bcma_nflash_read(nflash->bcc, off, NFL_SECTOR_SIZE, ptr)) < 0) {
570 + ret = bytes;
571 + goto done;
572 + }
573 + if (bytes > len)
574 + bytes = len;
575 + offset += bytes;
576 + len -= bytes;
577 + ptr += bytes;
578 + *retlen += bytes;
579 + }
580 +
581 +done:
582 + if (tmpbuf) {
583 + *retlen -= extra;
584 + memcpy(buf, tmpbuf+extra, *retlen);
585 + kfree(tmpbuf);
586 + }
587 +
588 + return ret;
589 +}
590 +
591 +static void bcm47xx_write(struct mtd_info *mtd, u32 to, const u_char *buf, u32 len)
592 +{
593 + struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
594 + struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
595 + u32 offset, blocksize, mask, off;
596 + int read_len;
597 + u32 copy_len, write_len, from;
598 + u_char *write_ptr, *block;
599 + const u_char *ptr;
600 + int ret, bytes;
601 +
602 + /* Check address range */
603 + if (!len) {
604 + pr_err("Error: Attempted to write too small data\n");
605 + return;
606 + }
607 +
608 + if (!to)
609 + return;
610 +
611 + if ((to + len) > mtd->size) {
612 + pr_err("Error: Attempted to write too large data\n");
613 + return;
614 + }
615 +
616 + ptr = buf;
617 + block = NULL;
618 + offset = to;
619 + blocksize = mtd->erasesize;
620 + if (!(block = kmalloc(blocksize, GFP_KERNEL)))
621 + return;
622 + mask = blocksize - 1;
623 + while (len) {
624 + /* Align offset */
625 + from = offset & ~mask;
626 + /* Copy existing data into holding block if necessary */
627 + if (((offset & (blocksize-1)) != 0) || (len < blocksize)) {
628 + if ((ret = bcm47xx_read(mtd, from, blocksize, &read_len, block)))
629 + goto done;
630 + if (read_len != blocksize) {
631 + ret = -EINVAL;
632 + goto done;
633 + }
634 + }
635 +
636 + /* Copy input data into holding block */
637 + copy_len = min(len, blocksize - (offset & mask));
638 + memcpy(block + (offset & mask), ptr, copy_len);
639 + off = (uint) from;
640 + /* Erase block */
641 + if ((ret = bcm47xx_erase(mtd, off, blocksize)) < 0)
642 + goto done;
643 + /* Write holding block */
644 + write_ptr = block;
645 + write_len = blocksize;
646 + if ((bytes = bcma_nflash_write(nflash->bcc, (uint)from, (uint)write_len, (u8 *) write_ptr)) != 0) {
647 + ret = bytes;
648 + goto done;
649 + }
650 + offset += copy_len;
651 + if (len < copy_len)
652 + len = 0;
653 + else
654 + len -= copy_len;
655 + ptr += copy_len;
656 + }
657 +
658 +done:
659 + if (block)
660 + kfree(block);
661 + return;
662 +}
663 +
664 +static int bcm47xx_erase(struct mtd_info *mtd, unsigned int addr, unsigned int len)
665 +{
666 + struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
667 + struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
668 +
669 + /* Check address range */
670 + if (!len)
671 + return 1;
672 + if ((addr + len) > mtd->size)
673 + return 1;
674 +
675 + if (bcma_nflash_erase(nflash->bcc, addr)) {
676 + pr_err("ERASE: nflash erase error\n");
677 + return 1;
678 + }
679 +
680 + if (nflash_mtd_poll(nflash, addr, 10 * HZ)) {
681 + pr_err("ERASE: nflash_mtd_poll error\n");
682 + return 1;
683 + }
684 +
685 + return 0;
686 +}
687 +
688 +/* This functions is used by upper layer to checks if device is ready */
689 +static int bcm47xx_dev_ready(struct mtd_info *mtd)
690 +{
691 + return 1;
692 +}
693 +
694 +/* Issue a nand flash command */
695 +static inline void bcm47xx_nflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
696 +{
697 + bcma_cc_write32(cc, NAND_CMD_START, opcode);
698 + bcma_cc_read32(cc, NAND_CMD_START);
699 +}
700 +
701 +static void bcm47xx_command(struct mtd_info *mtd, unsigned command,
702 + int column, int page_addr)
703 +{
704 + struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
705 + struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
706 + u32 pagesize = 1 << nchip->page_shift;
707 +
708 + /* Command pre-processing step */
709 + switch (command) {
710 + case NAND_CMD_RESET:
711 + bcm47xx_nflash_cmd(nflash->bcc, NCMD_FLASH_RESET);
712 + break;
713 +
714 + case NAND_CMD_STATUS:
715 + nflash->next_opcode = NAND_CMD_STATUS;
716 + read_offset = 0;
717 + write_offset = 0;
718 + break;
719 +
720 + case NAND_CMD_READ0:
721 + read_offset = page_addr * pagesize;
722 + nflash->next_opcode = 0;
723 + break;
724 +
725 + case NAND_CMD_READOOB:
726 + read_offset = page_addr * pagesize;
727 + nflash->next_opcode = 0;
728 + break;
729 +
730 + case NAND_CMD_SEQIN:
731 + write_offset = page_addr * pagesize;
732 + nflash->next_opcode = 0;
733 + break;
734 +
735 + case NAND_CMD_PAGEPROG:
736 + nflash->next_opcode = 0;
737 + break;
738 +
739 + case NAND_CMD_READID:
740 + read_offset = column;
741 + bcm47xx_nflash_cmd(nflash->bcc, NCMD_ID_RD);
742 + nflash->next_opcode = NAND_DEVID;
743 + break;
744 +
745 + case NAND_CMD_ERASE1:
746 + nflash->next_opcode = 0;
747 + bcm47xx_erase(mtd, page_addr*pagesize, pagesize);
748 + break;
749 +
750 + case NAND_CMD_ERASE2:
751 + break;
752 +
753 + case NAND_CMD_RNDOUT:
754 + if (column > mtd->writesize)
755 + read_offset += (column - mtd->writesize);
756 + else
757 + read_offset += column;
758 + break;
759 +
760 + default:
761 + pr_err("COMMAND not supported %x\n", command);
762 + nflash->next_opcode = 0;
763 + break;
764 + }
765 +}
766 +
767 +/* This function is used by upper layer for select and
768 + * deselect of the NAND chip.
769 + * It is dummy function. */
770 +static void bcm47xx_select_chip(struct mtd_info *mtd, int chip)
771 +{
772 +}
773 +
774 +static u_char bcm47xx_read_byte(struct mtd_info *mtd)
775 +{
776 + struct nand_chip *nchip = mtd->priv;
777 + struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
778 + uint8_t ret = 0;
779 + static u32 id;
780 +
781 + if (nflash->next_opcode == 0)
782 + return ret;
783 +
784 + if (nflash->next_opcode == NAND_CMD_STATUS)
785 + return NAND_STATUS_WP;
786 +
787 + id = bcma_cc_read32(nflash->bcc, nflash->next_opcode);
788 +
789 + if (nflash->next_opcode == NAND_DEVID) {
790 + ret = (id >> (8*read_offset)) & 0xff;
791 + read_offset++;
792 + }
793 +
794 + return ret;
795 +}
796 +
797 +static uint16_t bcm47xx_read_word(struct mtd_info *mtd)
798 +{
799 + loff_t from = read_offset;
800 + uint16_t buf = 0;
801 + int bytes;
802 +
803 + bcm47xx_read(mtd, from, sizeof(buf), &bytes, (u_char *)&buf);
804 + return buf;
805 +}
806 +
807 +/* Write data of length len to buffer buf. The data to be
808 + * written on NAND Flash is first copied to RAMbuffer. After the Data Input
809 + * Operation by the NFC, the data is written to NAND Flash */
810 +static void bcm47xx_write_buf(struct mtd_info *mtd,
811 + const u_char *buf, int len)
812 +{
813 + bcm47xx_write(mtd, write_offset, buf, len);
814 +}
815 +
816 +/* Read the data buffer from the NAND Flash. To read the data from NAND
817 + * Flash first the data output cycle is initiated by the NFC, which copies
818 + * the data to RAMbuffer. This data of length len is then copied to buffer buf.
819 + */
820 +static void bcm47xx_read_buf(struct mtd_info *mtd, u_char *buf, int len)
821 +{
822 + loff_t from = read_offset;
823 + int bytes;
824 +
825 + bcm47xx_read(mtd, from, len, &bytes, buf);
826 +}
827 +
828 +/* Used by the upper layer to verify the data in NAND Flash
829 + * with the data in the buf. */
830 +static int bcm47xx_verify_buf(struct mtd_info *mtd,
831 + const u_char *buf, int len)
832 +{
833 + return -EFAULT;
834 +}
835 +
836 +static int bcm47xx_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
837 +{
838 + struct nand_chip *nchip = mtd->priv;
839 + struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
840 + int i;
841 + uint off;
842 + u32 pagesize = 1 << nchip->page_shift;
843 + u32 blocksize = mtd->erasesize;
844 +
845 + if ((ofs >> 20) >= nflash->size)
846 + return 1;
847 + if ((ofs & (blocksize - 1)) != 0)
848 + return 1;
849 +
850 + for (i = 0; i < 2; i++) {
851 + off = ofs + pagesize;
852 + bcma_cc_write32(nflash->bcc, NAND_CMD_ADDR, off);
853 + bcm47xx_nflash_cmd(nflash->bcc, NCMD_SPARE_RD);
854 + if (bcma_nflash_poll(nflash->bcc) < 0)
855 + break;
856 + if ((bcma_cc_read32(nflash->bcc, NAND_INTFC_STATUS) & NIST_SPARE_VALID) != NIST_SPARE_VALID)
857 + return 1;
858 + if ((bcma_cc_read32(nflash->bcc, NAND_SPARE_RD0) & 0xff) != 0xff)
859 + return 1;
860 + }
861 + return 0;
862 +}
863 +
864 +const char *part_probes[] = { "cmdlinepart", NULL };
865 +static int bcm47xx_probe(struct platform_device *pdev)
866 +{
867 + struct nand_chip *nchip;
868 + struct mtd_info *mtd;
869 + struct bcm47xx_nflash *nflash = dev_get_platdata(&pdev->dev);
870 + int ret = 0;
871 +
872 + mtd = &nflash->mtd;
873 + nchip = &nflash->nand;
874 +
875 + /* Register with MTD */
876 + mtd->priv = nchip;
877 + mtd->owner = THIS_MODULE;
878 + mtd->dev.parent = &pdev->dev;
879 +
880 + /* 50 us command delay time */
881 + nchip->chip_delay = 50;
882 +
883 + nchip->priv = nflash;
884 + nchip->dev_ready = bcm47xx_dev_ready;
885 + nchip->cmdfunc = bcm47xx_command;
886 + nchip->select_chip = bcm47xx_select_chip;
887 + nchip->read_byte = bcm47xx_read_byte;
888 + nchip->read_word = bcm47xx_read_word;
889 + nchip->write_buf = bcm47xx_write_buf;
890 + nchip->read_buf = bcm47xx_read_buf;
891 + nchip->verify_buf = bcm47xx_verify_buf;
892 + nchip->block_bad = bcm47xx_block_bad;
893 + nchip->options = NAND_SKIP_BBTSCAN;
894 +
895 + /* Not known */
896 + nchip->ecc.mode = NAND_ECC_NONE;
897 +
898 + /* first scan to find the device and get the page size */
899 + if (nand_scan_ident(mtd, 1, NULL)) {
900 + pr_err("nand_scan_ident failed\n");
901 + ret = -ENXIO;
902 + goto done;
903 + }
904 + nflash->bcc->nflash.size = mtd->size;
905 + nflash->bcc->nflash.pagesize = 1 << nchip->page_shift;
906 + nflash->bcc->nflash.blocksize = mtd->erasesize;
907 + bcm47xx_nflash.size = mtd->size;
908 +
909 + /* second phase scan */
910 + if (nand_scan_tail(mtd)) {
911 + pr_err("nand_scan_tail failed\n");
912 + ret = -ENXIO;
913 + goto done;
914 + }
915 +
916 + mtd->name = "bcm47xx-nflash";
917 + mtd->flags |= MTD_WRITEABLE;
918 + ret = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
919 +
920 + if (ret) {
921 + pr_err("mtd_device_register failed\n");
922 + return ret;
923 + }
924 +
925 + return 0;
926 +
927 +done:
928 + return ret;
929 +}
930 +
931 +static int __devexit bcm47xx_remove(struct platform_device *pdev)
932 +{
933 + struct bcm47xx_nflash *nflash = dev_get_platdata(&pdev->dev);
934 + struct mtd_info *mtd = &nflash->mtd;
935 +
936 + if (nflash) {
937 + /* Release resources, unregister device */
938 + nand_release(mtd);
939 + }
940 +
941 + return 0;
942 +}
943 +
944 +static struct platform_driver bcm47xx_driver = {
945 + .remove = __devexit_p(bcm47xx_remove),
946 + .driver = {
947 + .name = "bcm47xx_nflash",
948 + .owner = THIS_MODULE,
949 + },
950 +};
951 +
952 +static int __init init_bcm47xx_nflash(void)
953 +{
954 + int ret = platform_driver_probe(&bcm47xx_driver, bcm47xx_probe);
955 +
956 + if (ret)
957 + pr_err("error registering platform driver: %i\n", ret);
958 + return ret;
959 +}
960 +
961 +static void __exit exit_bcm47xx_nflash(void)
962 +{
963 + platform_driver_unregister(&bcm47xx_driver);
964 +}
965 +
966 +module_init(init_bcm47xx_nflash);
967 +module_exit(exit_bcm47xx_nflash);
968 +
969 +MODULE_LICENSE("GPL");
970 +MODULE_DESCRIPTION("BCM47XX NAND flash driver");
971 --- a/include/linux/bcma/bcma_driver_chipcommon.h
972 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
973 @@ -376,6 +376,7 @@ struct bcma_chipcommon_pmu {
974 enum bcma_flash_type {
975 BCMA_PFLASH,
976 BCMA_SFLASH,
977 + BCMA_NFLASH,
978 };
979
980 struct bcma_pflash {
981 @@ -392,6 +393,14 @@ struct bcma_sflash {
982 };
983 #endif /* CONFIG_BCMA_SFLASH */
984
985 +#ifdef CONFIG_BCMA_NFLASH
986 +struct bcma_nflash {
987 + u32 blocksize; /* Block size */
988 + u32 pagesize; /* Page size */
989 + u32 size; /* Total size in bytes */
990 +};
991 +#endif
992 +
993 struct bcma_serial_port {
994 void *regs;
995 unsigned long clockspeed;
996 @@ -417,6 +426,9 @@ struct bcma_drv_cc {
997 #ifdef CONFIG_BCMA_SFLASH
998 struct bcma_sflash sflash;
999 #endif /* CONFIG_BCMA_SFLASH */
1000 +#ifdef CONFIG_BCMA_NFLASH
1001 + struct bcma_nflash nflash;
1002 +#endif
1003 };
1004
1005 int nr_serial_ports;
1006 @@ -481,4 +493,13 @@ int bcma_sflash_write(struct bcma_drv_cc
1007 int bcma_sflash_erase(struct bcma_drv_cc *cc, u32 offset);
1008 #endif /* CONFIG_BCMA_SFLASH */
1009
1010 +#ifdef CONFIG_BCMA_NFLASH
1011 +/* Chipcommon nflash support. */
1012 +int bcma_nflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf);
1013 +int bcma_nflash_poll(struct bcma_drv_cc *cc);
1014 +int bcma_nflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf);
1015 +int bcma_nflash_erase(struct bcma_drv_cc *cc, u32 offset);
1016 +int bcma_nflash_commit(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf);
1017 +#endif
1018 +
1019 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1020 --- /dev/null
1021 +++ b/include/linux/mtd/bcm47xx_nand.h
1022 @@ -0,0 +1,134 @@
1023 +/*
1024 + * Broadcom chipcommon NAND flash interface
1025 + *
1026 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
1027 + * Copyright (C) 2009, Broadcom Corporation
1028 + * All Rights Reserved.
1029 + *
1030 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1031 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1032 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1033 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1034 + *
1035 + */
1036 +
1037 +#ifndef _nflash_h_
1038 +#define _nflash_h_
1039 +
1040 +#define NAND_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1041 +
1042 +/* nand_cmd_start commands */
1043 +#define NCMD_NULL 0
1044 +#define NCMD_PAGE_RD 1
1045 +#define NCMD_SPARE_RD 2
1046 +#define NCMD_STATUS_RD 3
1047 +#define NCMD_PAGE_PROG 4
1048 +#define NCMD_SPARE_PROG 5
1049 +#define NCMD_COPY_BACK 6
1050 +#define NCMD_ID_RD 7
1051 +#define NCMD_BLOCK_ERASE 8
1052 +#define NCMD_FLASH_RESET 9
1053 +#define NCMD_LOCK 0xa
1054 +#define NCMD_LOCK_DOWN 0xb
1055 +#define NCMD_UNLOCK 0xc
1056 +#define NCMD_LOCK_STATUS 0xd
1057 +
1058 +/* nand_acc_control */
1059 +#define NAC_RD_ECC_EN 0x80000000
1060 +#define NAC_WR_ECC_EN 0x40000000
1061 +#define NAC_RD_ECC_BLK0_EN 0x20000000
1062 +#define NAC_FAST_PGM_RDIN 0x10000000
1063 +#define NAC_RD_ERASED_ECC_EN 0x08000000
1064 +#define NAC_PARTIAL_PAGE_EN 0x04000000
1065 +#define NAC_PAGE_HIT_EN 0x01000000
1066 +#define NAC_ECC_LEVEL0 0x00f00000
1067 +#define NAC_ECC_LEVEL 0x000f0000
1068 +#define NAC_SPARE_SIZE0 0x00003f00
1069 +#define NAC_SPARE_SIZE 0x0000003f
1070 +
1071 +/* nand_config */
1072 +#define NCF_CONFIG_LOCK 0x80000000
1073 +#define NCF_BLOCK_SIZE_MASK 0x70000000
1074 +#define NCF_BLOCK_SIZE_SHIFT 28
1075 +#define NCF_DEVICE_SIZE_MASK 0x0f000000
1076 +#define NCF_DEVICE_SIZE_SHIFT 24
1077 +#define NCF_DEVICE_WIDTH 0x00800000
1078 +#define NCF_PAGE_SIZE_MASK 0x00300000
1079 +#define NCF_PAGE_SIZE_SHIFT 20
1080 +#define NCF_FULL_ADDR_BYTES_MASK 0x00070000
1081 +#define NCF_FULL_ADDR_BYTES_SHIFT 16
1082 +#define NCF_COL_ADDR_BYTES_MASK 0x00007000
1083 +#define NCF_COL_ADDR_BYTES_SHIFT 12
1084 +#define NCF_BLK_ADDR_BYTES_MASK 0x00000700
1085 +#define NCF_BLK_ADDR_BYTES_SHIFT 8
1086 +
1087 +/* nand_intfc_status */
1088 +#define NIST_CTRL_READY 0x80000000
1089 +#define NIST_FLASH_READY 0x40000000
1090 +#define NIST_CACHE_VALID 0x20000000
1091 +#define NIST_SPARE_VALID 0x10000000
1092 +#define NIST_ERASED 0x08000000
1093 +#define NIST_STATUS 0x000000ff
1094 +
1095 +#define NFL_SECTOR_SIZE 512
1096 +
1097 +#define NFL_TABLE_END 0xffffffff
1098 +#define NFL_BOOT_SIZE 0x200000
1099 +#define NFL_BOOT_OS_SIZE 0x2000000
1100 +
1101 +/* Nand flash MLC controller registers (corerev >= 38) */
1102 +#define NAND_REVISION 0xC00
1103 +#define NAND_CMD_START 0xC04
1104 +#define NAND_CMD_ADDR_X 0xC08
1105 +#define NAND_CMD_ADDR 0xC0C
1106 +#define NAND_CMD_END_ADDR 0xC10
1107 +#define NAND_CS_NAND_SELECT 0xC14
1108 +#define NAND_CS_NAND_XOR 0xC18
1109 +#define NAND_SPARE_RD0 0xC20
1110 +#define NAND_SPARE_RD4 0xC24
1111 +#define NAND_SPARE_RD8 0xC28
1112 +#define NAND_SPARE_RD12 0xC2C
1113 +#define NAND_SPARE_WR0 0xC30
1114 +#define NAND_SPARE_WR4 0xC34
1115 +#define NAND_SPARE_WR8 0xC38
1116 +#define NAND_SPARE_WR12 0xC3C
1117 +#define NAND_ACC_CONTROL 0xC40
1118 +#define NAND_CONFIG 0xC48
1119 +#define NAND_TIMING_1 0xC50
1120 +#define NAND_TIMING_2 0xC54
1121 +#define NAND_SEMAPHORE 0xC58
1122 +#define NAND_DEVID 0xC60
1123 +#define NAND_DEVID_X 0xC64
1124 +#define NAND_BLOCK_LOCK_STATUS 0xC68
1125 +#define NAND_INTFC_STATUS 0xC6C
1126 +#define NAND_ECC_CORR_ADDR_X 0xC70
1127 +#define NAND_ECC_CORR_ADDR 0xC74
1128 +#define NAND_ECC_UNC_ADDR_X 0xC78
1129 +#define NAND_ECC_UNC_ADDR 0xC7C
1130 +#define NAND_READ_ERROR_COUNT 0xC80
1131 +#define NAND_CORR_STAT_THRESHOLD 0xC84
1132 +#define NAND_READ_ADDR_X 0xC90
1133 +#define NAND_READ_ADDR 0xC94
1134 +#define NAND_PAGE_PROGRAM_ADDR_X 0xC98
1135 +#define NAND_PAGE_PROGRAM_ADDR 0xC9C
1136 +#define NAND_COPY_BACK_ADDR_X 0xCA0
1137 +#define NAND_COPY_BACK_ADDR 0xCA4
1138 +#define NAND_BLOCK_ERASE_ADDR_X 0xCA8
1139 +#define NAND_BLOCK_ERASE_ADDR 0xCAC
1140 +#define NAND_INV_READ_ADDR_X 0xCB0
1141 +#define NAND_INV_READ_ADDR 0xCB4
1142 +#define NAND_BLK_WR_PROTECT 0xCC0
1143 +#define NAND_ACC_CONTROL_CS1 0xCD0
1144 +#define NAND_CONFIG_CS1 0xCD4
1145 +#define NAND_TIMING_1_CS1 0xCD8
1146 +#define NAND_TIMING_2_CS1 0xCDC
1147 +#define NAND_SPARE_RD16 0xD30
1148 +#define NAND_SPARE_RD20 0xD34
1149 +#define NAND_SPARE_RD24 0xD38
1150 +#define NAND_SPARE_RD28 0xD3C
1151 +#define NAND_CACHE_ADDR 0xD40
1152 +#define NAND_CACHE_DATA 0xD44
1153 +#define NAND_CTRL_CONFIG 0xD48
1154 +#define NAND_CTRL_STATUS 0xD4C
1155 +
1156 +#endif /* _nflash_h_ */
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