[malta] update to 2.6.39.1
[openwrt.git] / target / linux / octeon / patches / 001-wndap330_hacks.patch
1 --- a/drivers/staging/octeon/cvmx-helper-board.c
2 +++ b/drivers/staging/octeon/cvmx-helper-board.c
3 @@ -90,7 +90,7 @@ int cvmx_helper_board_get_mii_address(in
4 case CVMX_BOARD_TYPE_KODAMA:
5 case CVMX_BOARD_TYPE_EBH3100:
6 case CVMX_BOARD_TYPE_HIKARI:
7 - case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
8 + //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
9 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
10 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
11 /*
12 @@ -103,6 +103,12 @@ int cvmx_helper_board_get_mii_address(in
13 return 9;
14 else
15 return -1;
16 + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
17 + /* We have only one port, using GMII */
18 + if (ipd_port == 0)
19 + return 9;
20 + else
21 + return -1;
22 case CVMX_BOARD_TYPE_NAC38:
23 /* Board has 8 RGMII ports PHYs are 0-7 */
24 if ((ipd_port >= 0) && (ipd_port < 4))
25 @@ -213,7 +219,7 @@ cvmx_helper_link_info_t __cvmx_helper_bo
26 result.s.speed = 1000;
27 return result;
28 case CVMX_BOARD_TYPE_EBH3100:
29 - case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
30 + //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
31 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
32 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
33 /* Port 1 on these boards is always Gigabit */
34 @@ -225,6 +231,9 @@ cvmx_helper_link_info_t __cvmx_helper_bo
35 }
36 /* Fall through to the generic code below */
37 break;
38 + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
39 + is_broadcom_phy = 1;
40 + break;
41 case CVMX_BOARD_TYPE_CUST_NB5:
42 /* Port 1 on these boards is always Gigabit */
43 if (ipd_port == 1) {
44 --- a/drivers/staging/octeon/cvmx-helper-rgmii.c
45 +++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
46 @@ -66,13 +66,15 @@ int __cvmx_helper_rgmii_probe(int interf
47 cvmx_dprintf("ERROR: RGMII initialize called in "
48 "SPI interface\n");
49 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
50 - || OCTEON_IS_MODEL(OCTEON_CN30XX)
51 + //|| OCTEON_IS_MODEL(OCTEON_CN30XX)
52 || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
53 /*
54 * On these chips "type" says we're in
55 * GMII/MII mode. This limits us to 2 ports
56 */
57 num_ports = 2;
58 + } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
59 + num_ports = 1;
60 } else {
61 cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
62 __func__);
63 --- a/arch/mips/pci/pci-octeon.c
64 +++ b/arch/mips/pci/pci-octeon.c
65 @@ -217,9 +217,11 @@ const char *octeon_get_pci_interrupts(vo
66 /* This is really the NAC38 */
67 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
68 case CVMX_BOARD_TYPE_EBH3100:
69 - case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
70 + //case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
71 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
72 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
73 + case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
74 + return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
75 case CVMX_BOARD_TYPE_BBGW_REF:
76 return "AABCD";
77 case CVMX_BOARD_TYPE_THUNDER:
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