1 #include <linux/ioport.h>
3 #include <rt305x_regs.h>
4 #include <rt305x_esw_platform.h>
6 #define RT305X_ESW_REG_FCT0 0x08
7 #define RT305X_ESW_REG_PFC1 0x14
8 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
9 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
10 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
11 #define RT305X_ESW_REG_FPA 0x84
12 #define RT305X_ESW_REG_SOCPC 0x8c
13 #define RT305X_ESW_REG_POC1 0x90
14 #define RT305X_ESW_REG_POC2 0x94
15 #define RT305X_ESW_REG_POC3 0x98
16 #define RT305X_ESW_REG_SGC 0x9c
17 #define RT305X_ESW_REG_PCR0 0xc0
18 #define RT305X_ESW_REG_PCR1 0xc4
19 #define RT305X_ESW_REG_FPA2 0xc8
20 #define RT305X_ESW_REG_FCT2 0xcc
21 #define RT305X_ESW_REG_SGC2 0xe4
23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
24 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
27 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
29 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
31 #define RT305X_ESW_PVIDC_PVID_M 0xfff
32 #define RT305X_ESW_PVIDC_PVID_S 12
34 #define RT305X_ESW_VLANI_VID_M 0xfff
35 #define RT305X_ESW_VLANI_VID_S 12
37 #define RT305X_ESW_VMSC_MSC_M 0xff
38 #define RT305X_ESW_VMSC_MSC_S 8
40 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
41 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
42 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
43 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
45 #define RT305X_ESW_POC1_EN_BP_S 0
46 #define RT305X_ESW_POC1_EN_FC_S 8
47 #define RT305X_ESW_POC1_DIS_RMC2CPU_S 16
48 #define RT305X_ESW_POC1_DIS_PORT_S 23
50 #define RT305X_ESW_POC3_UNTAG_EN_S 0
51 #define RT305X_ESW_POC3_ENAGING_S 8
52 #define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
54 #define RT305X_ESW_PORT0 0
55 #define RT305X_ESW_PORT1 1
56 #define RT305X_ESW_PORT2 2
57 #define RT305X_ESW_PORT3 3
58 #define RT305X_ESW_PORT4 4
59 #define RT305X_ESW_PORT5 5
60 #define RT305X_ESW_PORT6 6
62 #define RT305X_ESW_PORTS_INTERNAL \
63 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
64 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
65 BIT(RT305X_ESW_PORT4))
67 #define RT305X_ESW_PORTS_NOCPU \
68 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
70 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
72 #define RT305X_ESW_PORTS_ALL \
73 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
75 #define RT305X_ESW_NUM_VLANS 16
76 #define RT305X_ESW_NUM_PORTS 7
80 struct rt305x_esw_platform_data
*pdata
;
81 spinlock_t reg_rw_lock
;
85 rt305x_esw_wr(struct rt305x_esw
*esw
, u32 val
, unsigned reg
)
87 __raw_writel(val
, esw
->base
+ reg
);
91 rt305x_esw_rr(struct rt305x_esw
*esw
, unsigned reg
)
93 return __raw_readl(esw
->base
+ reg
);
97 rt305x_esw_rmw_raw(struct rt305x_esw
*esw
, unsigned reg
, unsigned long mask
,
102 t
= __raw_readl(esw
->base
+ reg
) & ~mask
;
103 __raw_writel(t
| val
, esw
->base
+ reg
);
107 rt305x_esw_rmw(struct rt305x_esw
*esw
, unsigned reg
, unsigned long mask
,
112 spin_lock_irqsave(&esw
->reg_rw_lock
, flags
);
113 rt305x_esw_rmw_raw(esw
, reg
, mask
, val
);
114 spin_unlock_irqrestore(&esw
->reg_rw_lock
, flags
);
118 rt305x_mii_write(struct rt305x_esw
*esw
, u32 phy_addr
, u32 phy_register
,
121 unsigned long t_start
= jiffies
;
125 if (!(rt305x_esw_rr(esw
, RT305X_ESW_REG_PCR1
) &
126 RT305X_ESW_PCR1_WT_DONE
))
128 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
134 write_data
&= 0xffff;
136 (write_data
<< RT305X_ESW_PCR0_WT_NWAY_DATA_S
) |
137 (phy_register
<< RT305X_ESW_PCR0_CPU_PHY_REG_S
) |
138 (phy_addr
) | RT305X_ESW_PCR0_WT_PHY_CMD
,
139 RT305X_ESW_REG_PCR0
);
143 if (rt305x_esw_rr(esw
, RT305X_ESW_REG_PCR1
) &
144 RT305X_ESW_PCR1_WT_DONE
)
147 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
154 printk(KERN_ERR
"ramips_eth: MDIO timeout\n");
159 rt305x_esw_set_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
, unsigned vid
)
163 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
165 RT305X_ESW_REG_VLANI(vlan
/ 2),
166 RT305X_ESW_VLANI_VID_M
<< s
,
167 (vid
& RT305X_ESW_VLANI_VID_M
) << s
);
171 rt305x_esw_set_pvid(struct rt305x_esw
*esw
, unsigned port
, unsigned pvid
)
175 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
177 RT305X_ESW_REG_PVIDC(port
/ 2),
178 RT305X_ESW_PVIDC_PVID_M
<< s
,
179 (pvid
& RT305X_ESW_PVIDC_PVID_M
) << s
);
183 rt305x_esw_set_vmsc(struct rt305x_esw
*esw
, unsigned vlan
, unsigned msc
)
187 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
189 RT305X_ESW_REG_VMSC(vlan
/ 4),
190 RT305X_ESW_VMSC_MSC_M
<< s
,
191 (msc
& RT305X_ESW_VMSC_MSC_M
) << s
);
195 rt305x_esw_hw_init(struct rt305x_esw
*esw
)
199 /* vodoo from original driver */
200 rt305x_esw_wr(esw
, 0xC8A07850, RT305X_ESW_REG_FCT0
);
201 rt305x_esw_wr(esw
, 0x00000000, RT305X_ESW_REG_SGC2
);
202 rt305x_esw_wr(esw
, 0x00405555, RT305X_ESW_REG_PFC1
);
204 /* Enable Back Pressure, and Flow Control */
206 ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC1_EN_BP_S
) |
207 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC1_EN_FC_S
)),
208 RT305X_ESW_REG_POC1
);
210 /* Enable Aging, and VLAN TAG removal */
212 ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC3_ENAGING_S
) |
213 (RT305X_ESW_PORTS_NOCPU
<< RT305X_ESW_POC3_UNTAG_EN_S
)),
214 RT305X_ESW_REG_POC3
);
216 rt305x_esw_wr(esw
, 0x00d6500c, RT305X_ESW_REG_FCT2
);
217 rt305x_esw_wr(esw
, 0x0008a301, RT305X_ESW_REG_SGC
);
219 /* Setup SoC Port control register */
221 (RT305X_ESW_SOCPC_CRC_PADDING
|
222 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISUN2CPU_S
) |
223 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISMC2CPU_S
) |
224 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISBC2CPU_S
)),
225 RT305X_ESW_REG_SOCPC
);
227 rt305x_esw_wr(esw
, 0x3f502b28, RT305X_ESW_REG_FPA2
);
228 rt305x_esw_wr(esw
, 0x00000000, RT305X_ESW_REG_FPA
);
230 rt305x_mii_write(esw
, 0, 31, 0x8000);
231 for (i
= 0; i
< 5; i
++) {
232 /* TX10 waveform coefficient */
233 rt305x_mii_write(esw
, i
, 0, 0x3100);
234 /* TX10 waveform coefficient */
235 rt305x_mii_write(esw
, i
, 26, 0x1601);
236 /* TX100/TX10 AD/DA current bias */
237 rt305x_mii_write(esw
, i
, 29, 0x7058);
238 /* TX100 slew rate control */
239 rt305x_mii_write(esw
, i
, 30, 0x0018);
243 /* select global register */
244 rt305x_mii_write(esw
, 0, 31, 0x0);
245 /* tune TP_IDL tail and head waveform */
246 rt305x_mii_write(esw
, 0, 22, 0x052f);
247 /* set TX10 signal amplitude threshold to minimum */
248 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
249 /* set squelch amplitude to higher threshold */
250 rt305x_mii_write(esw
, 0, 18, 0x40ba);
251 /* longer TP_IDL tail length */
252 rt305x_mii_write(esw
, 0, 14, 0x65);
253 /* select local register */
254 rt305x_mii_write(esw
, 0, 31, 0x8000);
256 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
257 rt305x_esw_set_vlan_id(esw
, i
, 0);
258 rt305x_esw_set_vmsc(esw
, i
, 0);
261 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++)
262 rt305x_esw_set_pvid(esw
, i
, 1);
264 switch (esw
->pdata
->vlan_config
) {
265 case RT305X_ESW_VLAN_CONFIG_NONE
:
268 case RT305X_ESW_VLAN_CONFIG_LLLLW
:
269 rt305x_esw_set_vlan_id(esw
, 0, 1);
270 rt305x_esw_set_vlan_id(esw
, 1, 2);
271 rt305x_esw_set_pvid(esw
, RT305X_ESW_PORT4
, 2);
273 rt305x_esw_set_vmsc(esw
, 0,
274 BIT(RT305X_ESW_PORT0
) | BIT(RT305X_ESW_PORT1
) |
275 BIT(RT305X_ESW_PORT2
) | BIT(RT305X_ESW_PORT3
) |
276 BIT(RT305X_ESW_PORT6
));
277 rt305x_esw_set_vmsc(esw
, 1,
278 BIT(RT305X_ESW_PORT4
) | BIT(RT305X_ESW_PORT6
));
281 case RT305X_ESW_VLAN_CONFIG_WLLLL
:
282 rt305x_esw_set_vlan_id(esw
, 0, 1);
283 rt305x_esw_set_vlan_id(esw
, 1, 2);
284 rt305x_esw_set_pvid(esw
, RT305X_ESW_PORT0
, 2);
286 rt305x_esw_set_vmsc(esw
, 0,
287 BIT(RT305X_ESW_PORT1
) | BIT(RT305X_ESW_PORT2
) |
288 BIT(RT305X_ESW_PORT3
) | BIT(RT305X_ESW_PORT4
) |
289 BIT(RT305X_ESW_PORT6
));
290 rt305x_esw_set_vmsc(esw
, 1,
291 BIT(RT305X_ESW_PORT0
) | BIT(RT305X_ESW_PORT6
));
300 rt305x_esw_probe(struct platform_device
*pdev
)
302 struct rt305x_esw_platform_data
*pdata
;
303 struct rt305x_esw
*esw
;
304 struct resource
*res
;
307 pdata
= pdev
->dev
.platform_data
;
311 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
313 dev_err(&pdev
->dev
, "no memory resource found\n");
317 esw
= kzalloc(sizeof(struct rt305x_esw
), GFP_KERNEL
);
319 dev_err(&pdev
->dev
, "no memory for private data\n");
323 esw
->base
= ioremap(res
->start
, resource_size(res
));
325 dev_err(&pdev
->dev
, "ioremap failed\n");
330 platform_set_drvdata(pdev
, esw
);
333 spin_lock_init(&esw
->reg_rw_lock
);
334 rt305x_esw_hw_init(esw
);
344 rt305x_esw_remove(struct platform_device
*pdev
)
346 struct rt305x_esw
*esw
;
348 esw
= platform_get_drvdata(pdev
);
350 platform_set_drvdata(pdev
, NULL
);
358 static struct platform_driver rt305x_esw_driver
= {
359 .probe
= rt305x_esw_probe
,
360 .remove
= rt305x_esw_remove
,
362 .name
= "rt305x-esw",
363 .owner
= THIS_MODULE
,
368 rt305x_esw_init(void)
370 return platform_driver_register(&rt305x_esw_driver
);
374 rt305x_esw_exit(void)
376 platform_driver_unregister(&rt305x_esw_driver
);