target/linux/lantiq/patches-3.2/0036-MIPS-lantiq-add-vr9-support.patch

   1 From 27c4128ab1835a2aff1a0ce6413bb21cfa614d93 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 21 Feb 2012 09:48:11 +0100
   4 Subject: [PATCH 36/70] MIPS: lantiq: add vr9 support
   5
   6 VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9.
   7 This patch adds the clkdev init code and SoC detection for the VR9.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  11 ---
  12  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    3 +
  13  arch/mips/lantiq/xway/clk.c                        |   83 ++++++++++++++++++++
  14  arch/mips/lantiq/xway/prom.c                       |    6 ++
  15  arch/mips/lantiq/xway/sysctrl.c                    |   12 +++-
  16  4 files changed, 103 insertions(+), 1 deletions(-)
  17
  18 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  19 index e9d2dd4..5d11eb7 100644
  20 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  21 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  22 @@ -21,6 +21,9 @@
  23  #define SOC_ID_ARX188          0x16C
  24  #define SOC_ID_ARX168          0x16D
  25  #define SOC_ID_ARX182          0x16F
  26 +#define SOC_ID_VRX288          0x1C0 /* VRX288 v1.1 */
  27 +#define SOC_ID_VRX268          0x1C2 /* VRX268 v1.1 */
  28 +#define SOC_ID_GRX288          0x1C9 /* GRX288 v1.1 */
  29
  30  /* SoC Types */
  31  #define SOC_TYPE_DANUBE                0x01
  32 diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
  33 index f3b50fc..3635c9f 100644
  34 --- a/arch/mips/lantiq/xway/clk.c
  35 +++ b/arch/mips/lantiq/xway/clk.c
  36 @@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void)
  37                 return ddr_clock >> 1;
  38         return ddr_clock;
  39  }
  40 +
  41 +unsigned long ltq_vr9_cpu_hz(void)
  42 +{
  43 +       unsigned int cpu_sel;
  44 +       unsigned long clk;
  45 +
  46 +       cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
  47 +
  48 +       switch (cpu_sel) {
  49 +       case 0:
  50 +               clk = CLOCK_600M;
  51 +               break;
  52 +       case 1:
  53 +               clk = CLOCK_500M;
  54 +               break;
  55 +       case 2:
  56 +               clk = CLOCK_393M;
  57 +               break;
  58 +       case 3:
  59 +               clk = CLOCK_333M;
  60 +               break;
  61 +       case 5:
  62 +       case 6:
  63 +               clk = CLOCK_196_608M;
  64 +               break;
  65 +       case 7:
  66 +               clk = CLOCK_167M;
  67 +               break;
  68 +       case 4:
  69 +       case 8:
  70 +       case 9:
  71 +               clk = CLOCK_125M;
  72 +               break;
  73 +       default:
  74 +               clk = 0;
  75 +               break;
  76 +       }
  77 +
  78 +       return clk;
  79 +}
  80 +
  81 +unsigned long ltq_vr9_fpi_hz(void)
  82 +{
  83 +       unsigned int ocp_sel, cpu_clk;
  84 +       unsigned long clk;
  85 +
  86 +       cpu_clk = ltq_vr9_cpu_hz();
  87 +       ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
  88 +
  89 +       switch (ocp_sel) {
  90 +       case 0:
  91 +               /* OCP ratio 1 */
  92 +               clk = cpu_clk;
  93 +               break;
  94 +       case 2:
  95 +               /* OCP ratio 2 */
  96 +               clk = cpu_clk / 2;
  97 +               break;
  98 +       case 3:
  99 +               /* OCP ratio 2.5 */
 100 +               clk = (cpu_clk * 2) / 5;
 101 +               break;
 102 +       case 4:
 103 +               /* OCP ratio 3 */
 104 +               clk = cpu_clk / 3;
 105 +               break;
 106 +       default:
 107 +               clk = 0;
 108 +               break;
 109 +       }
 110 +
 111 +       return clk;
 112 +}
 113 +
 114 +unsigned long ltq_vr9_io_region_clock(void)
 115 +{
 116 +       return ltq_vr9_fpi_hz();
 117 +}
 118 +
 119 +unsigned long ltq_vr9_fpi_bus_clock(int fpi)
 120 +{
 121 +       return ltq_vr9_fpi_hz();
 122 +}
 123 diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
 124 index 0929acb..b6f56b7 100644
 125 --- a/arch/mips/lantiq/xway/prom.c
 126 +++ b/arch/mips/lantiq/xway/prom.c
 127 @@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 128  #endif
 129                 break;
 130
 131 +       case SOC_ID_VRX268:
 132 +       case SOC_ID_VRX288:
 133 +               i->name = SOC_VR9;
 134 +               i->type = SOC_TYPE_VR9;
 135 +               break;
 136 +
 137         default:
 138                 unreachable();
 139                 break;
 140 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
 141 index c5782b5..38f02f9 100644
 142 --- a/arch/mips/lantiq/xway/sysctrl.c
 143 +++ b/arch/mips/lantiq/xway/sysctrl.c
 144 @@ -147,7 +147,8 @@ void __init ltq_soc_init(void)
 145         clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 146         clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 147         clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
 148 -       clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 149 +       if (!ltq_is_vr9())
 150 +               clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 151         if (ltq_is_ase()) {
 152                 if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
 153                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 154 @@ -155,6 +156,15 @@ void __init ltq_soc_init(void)
 155                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 156                 clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
 157                 clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
 158 +       } else if (ltq_is_vr9()) {
 159 +               clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 160 +                                       ltq_vr9_io_region_clock());
 161 +               clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
 162 +               clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
 163 +               clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
 164 +               clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
 165 +               clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
 166 +               clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 167         } else {
 168                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 169                                         ltq_danube_io_region_clock());
 170 --
 171 1.7.7.1
 172