target/linux/adm5120/files/drivers/net/adm5120sw.h

   1 /*
   2  *      Defines for ADM5120 built in ethernet switch driver
   3  *
   4  *      Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
   5  *
   6  *      Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
   7  *      Copyright ADMtek Inc.
   8  */
   9
  10 #ifndef _INCLUDE_ADM5120SW_H_
  11 #define _INCLUDE_ADM5120SW_H_
  12
  13 #define SW_BASE KSEG1ADDR(0x12000000)
  14 #define SW_DEVS 6
  15
  16 #define ETH_TX_TIMEOUT          HZ*400
  17 #define ETH_FCS 4;
  18
  19 #define ADM5120_CODE            0x00            /* CPU description */
  20 #define ADM5120_CODE_PQFP       0x20000000      /* package type */
  21 #define ADM5120_SW_CONF         0x20            /* Switch configuration register */
  22 #define ADM5120_SW_CONF_BPM     0x00300000      /* Mask for backpressure mode */
  23 #define ADM5120_CPUP_CONF       0x24            /* CPU port config */
  24 #define ADM5120_DISCCPUPORT     0x00000001      /* disable cpu port */
  25 #define ADM5120_CRC_PADDING     0x00000002      /* software crc */
  26 #define ADM5120_BTM             0x00000004      /* bridge test mode */
  27 #define ADM5120_DISUNSHIFT      9
  28 #define ADM5120_DISUNALL        0x00007e00      /* disable unknown from all */
  29 #define ADM5120_DISMCSHIFT      16
  30 #define ADM5120_DISMCALL        0x003f0000      /* disable multicast from all */
  31 #define ADM5120_PORT_CONF0      0x28
  32 #define ADM5120_ENMC            0x00003f00      /* Enable MC routing (ex cpu) */
  33 #define ADM5120_ENBP            0x003f0000      /* Enable Back Pressure */
  34 #define ADM5120_PORTDISALL      0x0000003F
  35 #define ADM5120_VLAN_GI         0x40            /* VLAN settings */
  36 #define ADM5120_VLAN_GII        0x44
  37 #define ADM5120_SEND_TRIG       0x48
  38 #define ADM5120_SEND_TRIG_L     0x00000001
  39 #define ADM5120_SEND_TRIG_H     0x00000002
  40 #define ADM5120_MAC_WT0         0x58
  41 #define ADM5120_MAC_WRITE       0x00000001
  42 #define ADM5120_MAC_WRITE_DONE  0x00000002
  43 #define ADM5120_VLAN_EN         0x00000040
  44 #define ADM5120_MAC_WT1         0x5c
  45 #define ADM5120_BW_CTL0         0x60            /* Bandwidth control 0 */
  46 #define ADM5120_BW_CTL1         0x64            /* Bandwidth control 1 */
  47 #define ADM5120_PHY_CNTL2       0x7c
  48 #define ADM5120_AUTONEG         0x0000001f      /* Auto negotiate */
  49 #define ADM5120_NORMAL          0x01f00000      /* PHY normal mode */
  50 #define ADM5120_AUTOMDIX        0x3e000000      /* Auto MDIX */
  51 #define ADM5120_PHY_CNTL3       0x80
  52 #define ADM5120_PHY_NTH         0x00000400
  53 #define ADM5120_PRI_CNTL        0x84
  54 #define ADM5120_INT_ST          0xb0
  55 #define ADM5120_INT_RXH         0x0000004
  56 #define ADM5120_INT_RXL         0x0000008
  57 #define ADM5120_INT_HFULL       0x0000010
  58 #define ADM5120_INT_LFULL       0x0000020
  59 #define ADM5120_INT_TXH         0x0000001
  60 #define ADM5120_INT_TXL         0x0000002
  61 #define ADM5120_INT_MASK        0xb4
  62 #define ADM5120_INTMASKALL      0x1FDEFFF       /* All interrupts */
  63 #define ADM5120_INTHANDLE       (ADM5120_INT_RXH | ADM5120_INT_RXL | \
  64                                  ADM5120_INT_HFULL | ADM5120_INT_LFULL | \
  65                                  ADM5120_INT_TXH | ADM5120_INT_TXL)
  66 #define ADM5120_SEND_HBADDR     0xd0
  67 #define ADM5120_SEND_LBADDR     0xd4
  68 #define ADM5120_RECEIVE_HBADDR  0xd8
  69 #define ADM5120_RECEIVE_LBADDR  0xdc
  70
  71 struct adm5120_dma {
  72         u32 data;
  73         u32 cntl;
  74         u32 len;
  75         u32 status;
  76 } __attribute__ ((packed));
  77
  78 #define ADM5120_DMA_MASK        0x01ffffff
  79 #define ADM5120_DMA_OWN         0x80000000      /* buffer owner */
  80 #define ADM5120_DMA_RINGEND     0x10000000      /* Last in DMA ring */
  81
  82 #define ADM5120_DMA_ADDR(ptr)   ((u32)(ptr) & ADM5120_DMA_MASK)
  83 #define ADM5120_DMA_PORTID      0x00007000
  84 #define ADM5120_DMA_PORTSHIFT   12
  85 #define ADM5120_DMA_LEN         0x07ff0000
  86 #define ADM5120_DMA_LENSHIFT    16
  87 #define ADM5120_DMA_FCSERR      0x00000008
  88
  89 #define ADM5120_DMA_TXH         2
  90 #define ADM5120_DMA_TXL         64
  91 #define ADM5120_DMA_RXH         2
  92 #define ADM5120_DMA_RXL         64
  93
  94 #define ADM5120_DMA_RXSIZE      1550
  95 #define ADM5120_DMA_EXTRA       20
  96
  97 struct adm5120_sw {
  98         int                     port;
  99         struct net_device_stats stats;
 100 };
 101
 102 #define SIOCSMATRIX     SIOCDEVPRIVATE
 103 #define SIOCGMATRIX     SIOCDEVPRIVATE+1
 104 #define SIOCGADMINFO    SIOCDEVPRIVATE+2
 105 #define SIOCGETBW       SIOCDEVPRIVATE+3
 106 #define SIOCSETBW       SIOCDEVPRIVATE+4
 107
 108 struct adm5120_sw_info {
 109         u16     magic;
 110         u16     ports;
 111         u16     vlan;
 112 };
 113
 114 #endif /* _INCLUDE_ADM5120SW_H_ */