target/linux/ar7-2.6/files/arch/mips/ar7/vlynq-pci.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/pci.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <asm/ar7/vlynq.h>
  27
  28 #define VLYNQ_PCI_SLOTS 2
  29
  30 struct vlynq_reg_config {
  31         u32 offset;
  32         u32 value;
  33 };
  34
  35 struct vlynq_pci_config {
  36         u32 chip_id;
  37         char name[32];
  38         struct vlynq_mapping rx_mapping[4];
  39         int irq;
  40         int irq_type;
  41         u32 chip;
  42         u32 class;
  43         int num_regs;
  44         struct vlynq_reg_config regs[10];
  45 };
  46
  47 struct vlynq_pci_private {
  48         u32 latency;
  49         u32 cache_line;
  50         u32 command;
  51         u32 sz_mask;
  52         struct vlynq_pci_config *config;
  53 };
  54
  55 static struct vlynq_pci_config known_devices[] = {
  56         {
  57                 .chip_id = 0x00000009, .name = "TI ACX111",
  58                 .rx_mapping = {
  59                         { .size = 0x22000, .offset = 0xf0000000 },
  60                         { .size = 0x40000, .offset = 0xc0000000 },
  61                         { .size = 0x0, .offset = 0x0 },
  62                         { .size = 0x0, .offset = 0x0 },
  63                 },
  64                 .irq = 0, .chip = 0x9066104c,
  65                 .irq_type = IRQ_TYPE_EDGE_RISING,
  66                 .class = PCI_CLASS_NETWORK_OTHER,
  67                 .num_regs = 5,
  68                 .regs = {
  69                         { .offset = 0x790, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
  70                         { .offset = 0x794, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
  71                         { .offset = 0x740, .value = 0 },
  72                         { .offset = 0x744, .value = 0x00010000 },
  73                         { .offset = 0x764, .value = 0x00010000 },
  74                 },
  75         },
  76 };
  77
  78 static struct vlynq_device *slots[VLYNQ_PCI_SLOTS] = { NULL, };
  79
  80 static struct resource vlynq_io_resource = {
  81         .start  = 0x00000000,
  82         .end    = 0x00000000,
  83         .name   = "pci IO space",
  84         .flags  = IORESOURCE_IO
  85 };
  86
  87 static struct resource vlynq_mem_resource = {
  88         .start  = 0x00000000,
  89         .end    = 0x00000000,
  90         .name   = "pci memory space",
  91         .flags  = IORESOURCE_MEM
  92 };
  93
  94 static inline u32 vlynq_get_mapped(struct vlynq_device *dev, int res)
  95 {
  96         int i;
  97         struct vlynq_pci_private *priv = dev->priv;
  98         u32 ret = dev->mem_start;
  99         if (!priv->config->rx_mapping[res].size) return 0;
 100         for (i = 0; i < res; i++)
 101                 ret += priv->config->rx_mapping[i].size;
 102
 103         return ret;
 104 }
 105
 106 static inline u32 vlynq_read(u32 val, int size) {
 107         switch (size) {
 108         case 1:
 109                 return *(u8 *)&val;
 110         case 2:
 111                 return *(u16 *)&val;
 112         }
 113         return val;
 114 }
 115
 116 static int vlynq_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
 117 {
 118         struct vlynq_device *dev;
 119         struct vlynq_pci_private *priv;
 120         int resno, slot = PCI_SLOT(devfn);
 121
 122         if ((size == 2) && (where & 1))
 123                 return PCIBIOS_BAD_REGISTER_NUMBER;
 124         else if ((size == 4) && (where & 3))
 125                 return PCIBIOS_BAD_REGISTER_NUMBER;
 126
 127         if (slot >= VLYNQ_PCI_SLOTS)
 128                 return PCIBIOS_DEVICE_NOT_FOUND;
 129
 130         dev = slots[slot];
 131
 132         if (!dev || (PCI_FUNC(devfn) > 0))
 133                 return PCIBIOS_DEVICE_NOT_FOUND;
 134
 135         priv = dev->priv;
 136
 137         switch (where) {
 138         case PCI_VENDOR_ID:
 139                 *val = vlynq_read(priv->config->chip, size);
 140                 break;
 141         case PCI_DEVICE_ID:
 142                 *val = priv->config->chip & 0xffff;
 143         case PCI_COMMAND:
 144                 *val = priv->command;
 145         case PCI_STATUS:
 146 /*              *val = PCI_STATUS_CAP_LIST;*/
 147                 *val = 0;
 148                 break;
 149         case PCI_CLASS_REVISION:
 150                 *val = priv->config->class;
 151                 break;
 152         case PCI_LATENCY_TIMER:
 153                 *val = priv->latency;
 154                 break;
 155         case PCI_HEADER_TYPE:
 156                 *val = PCI_HEADER_TYPE_NORMAL;
 157                 break;
 158         case PCI_CACHE_LINE_SIZE:
 159                 *val = priv->cache_line;
 160                 break;
 161         case PCI_BASE_ADDRESS_0:
 162         case PCI_BASE_ADDRESS_1:
 163         case PCI_BASE_ADDRESS_2:
 164         case PCI_BASE_ADDRESS_3:
 165                 resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 166                 if (priv->sz_mask & (1 << resno)) {
 167                         priv->sz_mask &= ~(1 << resno);
 168                         *val = priv->config->rx_mapping[resno].size;
 169                 } else {
 170                         *val = vlynq_get_mapped(dev, resno);
 171                 }
 172                 break;
 173         case PCI_BASE_ADDRESS_4:
 174         case PCI_BASE_ADDRESS_5:
 175         case PCI_SUBSYSTEM_VENDOR_ID:
 176         case PCI_SUBSYSTEM_ID:
 177         case PCI_ROM_ADDRESS:
 178         case PCI_INTERRUPT_LINE:
 179         case PCI_CARDBUS_CIS:
 180         case PCI_CAPABILITY_LIST:
 181                 *val = 0;
 182                 break;
 183         case PCI_INTERRUPT_PIN:
 184                 *val = 1;
 185                 break;
 186         default:
 187                 printk("%s: Read of unknown register 0x%x (size %d)\n",
 188                        dev->dev.bus_id, where, size);
 189                 return PCIBIOS_BAD_REGISTER_NUMBER;
 190         }
 191         return PCIBIOS_SUCCESSFUL;
 192 }
 193
 194 static int vlynq_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 195 {
 196         struct vlynq_device *dev;
 197         struct vlynq_pci_private *priv;
 198         int resno, slot = PCI_SLOT(devfn);
 199
 200         if ((size == 2) && (where & 1))
 201                 return PCIBIOS_BAD_REGISTER_NUMBER;
 202         else if ((size == 4) && (where & 3))
 203                 return PCIBIOS_BAD_REGISTER_NUMBER;
 204
 205         if (slot >= VLYNQ_PCI_SLOTS)
 206                 return PCIBIOS_DEVICE_NOT_FOUND;
 207
 208         dev = slots[slot];
 209
 210         if (!dev || (PCI_FUNC(devfn) > 0))
 211                 return PCIBIOS_DEVICE_NOT_FOUND;
 212
 213         priv = dev->priv;
 214
 215         switch (where) {
 216         case PCI_VENDOR_ID:
 217         case PCI_DEVICE_ID:
 218         case PCI_STATUS:
 219         case PCI_CLASS_REVISION:
 220         case PCI_HEADER_TYPE:
 221         case PCI_CACHE_LINE_SIZE:
 222         case PCI_SUBSYSTEM_VENDOR_ID:
 223         case PCI_SUBSYSTEM_ID:
 224         case PCI_INTERRUPT_LINE:
 225         case PCI_INTERRUPT_PIN:
 226         case PCI_CARDBUS_CIS:
 227         case PCI_CAPABILITY_LIST:
 228                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 229         case PCI_COMMAND:
 230                 priv->command = val;
 231         case PCI_LATENCY_TIMER:
 232                 priv->latency = val;
 233                 break;
 234         case PCI_BASE_ADDRESS_0:
 235         case PCI_BASE_ADDRESS_1:
 236         case PCI_BASE_ADDRESS_2:
 237         case PCI_BASE_ADDRESS_3:
 238                 if (val == 0xffffffff) {
 239                         resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 240                         priv->sz_mask |= (1 << resno);
 241                         break;
 242                 }
 243         case PCI_BASE_ADDRESS_4:
 244         case PCI_BASE_ADDRESS_5:
 245         case PCI_ROM_ADDRESS:
 246                 break;
 247         default:
 248                 printk("%s: Write to unknown register 0x%x (size %d) value=0x%x\n",
 249                        dev->dev.bus_id, where, size, val);
 250                 return PCIBIOS_BAD_REGISTER_NUMBER;
 251         }
 252         return PCIBIOS_SUCCESSFUL;
 253 }
 254
 255 static struct pci_ops vlynq_pci_ops = {
 256         vlynq_config_read,
 257         vlynq_config_write
 258 };
 259
 260 static struct pci_controller vlynq_controller = {
 261         .pci_ops        = &vlynq_pci_ops,
 262         .io_resource    = &vlynq_io_resource,
 263         .mem_resource   = &vlynq_mem_resource,
 264 };
 265
 266 static int vlynq_pci_probe(struct vlynq_device *dev)
 267 {
 268         int result, i;
 269         u32 chip_id, addr;
 270         struct vlynq_pci_private *priv;
 271         struct vlynq_mapping mapping[4] = { { 0, }, };
 272         struct vlynq_pci_config *config = NULL;
 273
 274         result = vlynq_set_local_irq(dev, 31);
 275         if (result)
 276                 return result;
 277
 278         result = vlynq_set_remote_irq(dev, 30);
 279         if (result)
 280                 return result;
 281
 282         result = vlynq_device_enable(dev);
 283         if (result)
 284                 return result;
 285
 286         chip_id = vlynq_remote_id(dev);
 287         for (i = 0; i < ARRAY_SIZE(known_devices); i++)
 288                 if (chip_id == known_devices[i].chip_id)
 289                         config = &known_devices[i];
 290
 291         if (!config) {
 292                 printk("vlynq-pci: skipping unknown device "
 293                        "%04x:%04x at %s\n", chip_id >> 16,
 294                        chip_id & 0xffff, dev->dev.bus_id);
 295                 result = -ENODEV;
 296                 goto fail;
 297         }
 298
 299         printk("vlynq-pci: attaching device %s at %s\n",
 300                config->name, dev->dev.bus_id);
 301
 302         priv = kmalloc(sizeof(struct vlynq_pci_private), GFP_KERNEL);
 303         if (!priv) {
 304                 printk(KERN_ERR "%s: failed to allocate private data\n",
 305                        dev->dev.bus_id);
 306                 result = -ENOMEM;
 307                 goto fail;
 308         }
 309
 310         memset(priv, 0, sizeof(struct vlynq_pci_private));
 311         priv->latency = 64;
 312         priv->cache_line = 32;
 313         priv->config = config;
 314
 315         mapping[0].offset = ARCH_PFN_OFFSET << PAGE_SHIFT;
 316         mapping[0].size = 0x02000000;
 317         vlynq_set_local_mapping(dev, dev->mem_start, mapping);
 318         vlynq_set_remote_mapping(dev, 0, config->rx_mapping);
 319
 320         set_irq_type(vlynq_virq_to_irq(dev, config->irq), config->irq_type);
 321
 322         addr = (u32)ioremap_nocache(dev->mem_start, 0x10000);
 323         if (!addr) {
 324                 printk(KERN_ERR "%s: failed to remap io memory\n",
 325                        dev->dev.bus_id);
 326                 result = -ENXIO;
 327                 goto fail;
 328         }
 329
 330         for (i = 0; i < config->num_regs; i++)
 331                 *(volatile u32 *)(addr + config->regs[i].offset) =
 332                         config->regs[i].value;
 333
 334         dev->priv = priv;
 335         for (i = 0; i < VLYNQ_PCI_SLOTS; i++) {
 336                 if (!slots[i]) {
 337                         slots[i] = dev;
 338                         break;
 339                 }
 340         }
 341
 342         return 0;
 343
 344 fail:
 345         vlynq_device_disable(dev);
 346
 347         return result;
 348 }
 349
 350 static int vlynq_pci_remove(struct vlynq_device *dev)
 351 {
 352         int i;
 353         struct vlynq_pci_private *priv = dev->priv;
 354
 355         for (i = 0; i < VLYNQ_PCI_SLOTS; i++)
 356                 if (slots[i] == dev)
 357                         slots[i] = NULL;
 358
 359         vlynq_device_disable(dev);
 360         kfree(priv);
 361
 362         return 0;
 363 }
 364
 365 static struct vlynq_driver vlynq_pci = {
 366         .name = "PCI over VLYNQ emulation",
 367         .probe = vlynq_pci_probe,
 368         .remove = vlynq_pci_remove,
 369 };
 370
 371 int vlynq_pci_init(void)
 372 {
 373         int res;
 374         res = vlynq_register_driver(&vlynq_pci);
 375         if (res)
 376                 return res;
 377
 378         register_pci_controller(&vlynq_controller);
 379
 380         return 0;
 381 }
 382
 383 int pcibios_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 384 {
 385         struct vlynq_device *dev;
 386         struct vlynq_pci_private *priv;
 387
 388         dev = slots[slot];
 389
 390         if (!dev)
 391                 return 0;
 392
 393         priv = dev->priv;
 394
 395         return vlynq_virq_to_irq(dev, priv->config->irq);
 396 }
 397
 398 /* Do platform specific device initialization at pci_enable_device() time */
 399 int pcibios_plat_dev_init(struct pci_dev *dev)
 400 {
 401         return 0;
 402 }