2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/platform_device.h>
22 #include <linux/kernel.h>
23 #include <linux/reboot.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
31 static int is_5315
= 0;
32 static struct resource ar5315_eth_res
[] = {
34 .name
= "eth0_membase",
35 .flags
= IORESOURCE_MEM
,
36 .start
= AR5315_ENET0
,
37 .end
= AR5315_ENET0
+ 0x2000,
41 .flags
= IORESOURCE_IRQ
,
42 .start
= AR5315_IRQ_ENET0_INTRS
,
43 .end
= AR5315_IRQ_ENET0_INTRS
,
47 static struct ar531x_eth ar5315_eth_data
= {
50 .reset_base
= AR5315_RESET
,
51 .reset_mac
= AR5315_RESET_ENET0
,
52 .reset_phy
= AR5315_RESET_EPHY0
,
53 .phy_base
= AR5315_ENET0
56 static struct platform_device ar5315_eth
= {
59 .dev
.platform_data
= &ar5315_eth_data
,
60 .resource
= ar5315_eth_res
,
61 .num_resources
= ARRAY_SIZE(ar5315_eth_res
)
64 static struct platform_device ar5315_wmac
= {
66 .name
= "ar531x-wmac",
67 /* FIXME: add resources */
70 static struct resource ar5315_spiflash_res
[] = {
73 .flags
= IORESOURCE_MEM
,
74 .start
= KSEG1ADDR(AR5315_SPI_READ
),
75 .end
= KSEG1ADDR(AR5315_SPI_READ
) + 0x800000,
79 .flags
= IORESOURCE_MEM
,
85 static struct platform_device ar5315_spiflash
= {
88 .resource
= ar5315_spiflash_res
,
89 .num_resources
= ARRAY_SIZE(ar5315_spiflash_res
)
92 static __initdata
struct platform_device
*ar5315_devs
[4];
96 static void *flash_regs
;
98 static inline __u32
spiflash_regread32(int reg
)
100 volatile __u32
*data
= (__u32
*)(flash_regs
+ reg
);
105 static inline void spiflash_regwrite32(int reg
, __u32 data
)
107 volatile __u32
*addr
= (__u32
*)(flash_regs
+ reg
);
112 #define SPI_FLASH_CTL 0x00
113 #define SPI_FLASH_OPCODE 0x04
114 #define SPI_FLASH_DATA 0x08
116 static __u8
spiflash_probe(void)
121 reg
= spiflash_regread32(SPI_FLASH_CTL
);
122 } while (reg
& SPI_CTL_BUSY
);
124 spiflash_regwrite32(SPI_FLASH_OPCODE
, 0xab);
126 reg
= (reg
& ~SPI_CTL_TX_RX_CNT_MASK
) | 4 |
127 (1 << 4) | SPI_CTL_START
;
129 spiflash_regwrite32(SPI_FLASH_CTL
, reg
);
132 reg
= spiflash_regread32(SPI_FLASH_CTL
);
133 } while (reg
& SPI_CTL_BUSY
);
135 reg
= (__u32
) spiflash_regread32(SPI_FLASH_DATA
);
142 #define STM_8MBIT_SIGNATURE 0x13
143 #define STM_16MBIT_SIGNATURE 0x14
144 #define STM_32MBIT_SIGNATURE 0x15
145 #define STM_64MBIT_SIGNATURE 0x16
148 static char __init
*ar5315_flash_limit(void)
153 /* probe the flash chip size */
154 flash_regs
= ioremap_nocache(ar5315_spiflash_res
[1].start
, ar5315_spiflash_res
[1].end
- ar5315_spiflash_res
[1].start
);
155 sig
= spiflash_probe();
159 case STM_8MBIT_SIGNATURE
:
160 flash_size
= 0x00100000;
162 case STM_16MBIT_SIGNATURE
:
163 flash_size
= 0x00200000;
165 case STM_32MBIT_SIGNATURE
:
166 flash_size
= 0x00400000;
168 case STM_64MBIT_SIGNATURE
:
169 flash_size
= 0x00800000;
173 ar5315_spiflash_res
[0].end
= ar5315_spiflash_res
[0].start
+ flash_size
;
174 return (char *) ar5315_spiflash_res
[0].end
;
177 int __init
ar5315_init_devices(void)
179 struct ar531x_config
*config
;
180 struct ar531x_boarddata
*bcfg
;
187 /* Find board configuration */
188 ar531x_find_config(ar5315_flash_limit());
189 bcfg
= (struct ar531x_boarddata
*) board_config
;
192 /* Detect the hardware based on the device ID */
193 devid
= sysRegRead(AR5315_SREV
) & AR5315_REV_MAJ
>> AR5315_REV_MAJ_S
;
196 mips_machtype
= MACH_ATHEROS_AR2317
;
198 /* FIXME: how can we detect AR2316? */
201 mips_machtype
= MACH_ATHEROS_AR2315
;
206 config
= (struct ar531x_config
*) kzalloc(sizeof(struct ar531x_config
), GFP_KERNEL
);
207 config
->board
= board_config
;
208 config
->radio
= radio_config
;
210 config
->tag
= (u_int16_t
) (sysRegRead(AR5315_SREV
) & AR5315_REV_CHIP
);
212 ar5315_eth_data
.board_config
= board_config
;
213 ar5315_eth_data
.macaddr
= bcfg
->enet0Mac
;
214 ar5315_wmac
.dev
.platform_data
= config
;
216 ar5315_devs
[dev
++] = &ar5315_eth
;
217 ar5315_devs
[dev
++] = &ar5315_wmac
;
218 ar5315_devs
[dev
++] = &ar5315_spiflash
;
220 return platform_add_devices(ar5315_devs
, dev
);
225 * Called when an interrupt is received, this function
226 * determines exactly which interrupt it was, and it
227 * invokes the appropriate handler.
229 * Implicitly, we also define interrupt priority by
230 * choosing which to dispatch first.
232 asmlinkage
void ar5315_irq_dispatch(void)
234 int pending
= read_c0_status() & read_c0_cause();
236 if (pending
& CAUSEF_IP3
)
237 do_IRQ(AR5315_IRQ_WLAN0_INTRS
);
238 else if (pending
& CAUSEF_IP4
)
239 do_IRQ(AR5315_IRQ_ENET0_INTRS
);
240 else if (pending
& CAUSEF_IP2
) {
241 unsigned int ar531x_misc_intrs
= sysRegRead(AR5315_ISR
) & sysRegRead(AR5315_IMR
);
243 if (ar531x_misc_intrs
& AR5315_ISR_TIMER
)
244 do_IRQ(AR531X_MISC_IRQ_TIMER
);
245 else if (ar531x_misc_intrs
& AR5315_ISR_AHB
)
246 do_IRQ(AR531X_MISC_IRQ_AHB_PROC
);
247 else if (ar531x_misc_intrs
& AR5315_ISR_GPIO
) {
248 sysRegWrite(AR5315_ISR
, sysRegRead(AR5315_IMR
) | ~AR5315_ISR_GPIO
);
249 } else if (ar531x_misc_intrs
& AR5315_ISR_UART0
)
250 do_IRQ(AR531X_MISC_IRQ_UART0
);
251 else if (ar531x_misc_intrs
& AR5315_ISR_WD
)
252 do_IRQ(AR531X_MISC_IRQ_WATCHDOG
);
254 do_IRQ(AR531X_MISC_IRQ_NONE
);
255 } else if (pending
& CAUSEF_IP7
)
256 do_IRQ(AR531X_IRQ_CPU_CLOCK
);
258 do_IRQ(AR531X_IRQ_NONE
);
261 static void ar5315_halt(void)
266 static void ar5315_power_off(void)
272 static void ar5315_restart(char *command
)
277 /* reset the system */
278 sysRegWrite(AR5315_COLD_RESET
,AR5317_RESET_SYSTEM
);
281 * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
284 reg
= sysRegRead(AR5315_GPIO_DO
);
285 reg
&= ~(1 << AR5315_RESET_GPIO
);
286 sysRegWrite(AR5315_GPIO_DO
, reg
);
287 (void)sysRegRead(AR5315_GPIO_DO
); /* flush write to hardware */
293 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
294 * to determine the predevisor value.
296 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE
[4] = {
303 static int __initdata PLLC_DIVIDE_TABLE
[5] = {
311 static unsigned int __init
312 ar5315_sys_clk(unsigned int clockCtl
)
314 unsigned int pllcCtrl
,cpuDiv
;
315 unsigned int pllcOut
,refdiv
,fdiv
,divby2
;
318 pllcCtrl
= sysRegRead(AR5315_PLLC_CTL
);
319 refdiv
= (pllcCtrl
& PLLC_REF_DIV_M
) >> PLLC_REF_DIV_S
;
320 refdiv
= CLOCKCTL1_PREDIVIDE_TABLE
[refdiv
];
321 fdiv
= (pllcCtrl
& PLLC_FDBACK_DIV_M
) >> PLLC_FDBACK_DIV_S
;
322 divby2
= (pllcCtrl
& PLLC_ADD_FDBACK_DIV_M
) >> PLLC_ADD_FDBACK_DIV_S
;
324 pllcOut
= (40000000/refdiv
)*(2*divby2
)*fdiv
;
327 /* clkm input selected */
328 switch(clockCtl
& CPUCLK_CLK_SEL_M
) {
331 clkDiv
= PLLC_DIVIDE_TABLE
[(pllcCtrl
& PLLC_CLKM_DIV_M
) >> PLLC_CLKM_DIV_S
];
334 clkDiv
= PLLC_DIVIDE_TABLE
[(pllcCtrl
& PLLC_CLKC_DIV_M
) >> PLLC_CLKC_DIV_S
];
341 cpuDiv
= (clockCtl
& CPUCLK_CLK_DIV_M
) >> CPUCLK_CLK_DIV_S
;
342 cpuDiv
= cpuDiv
* 2 ?: 1;
343 return (pllcOut
/(clkDiv
* cpuDiv
));
346 static inline unsigned int ar5315_cpu_frequency(void)
348 return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK
));
351 static inline unsigned int ar5315_apb_frequency(void)
353 return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK
));
356 static void __init
ar5315_time_init(void)
358 mips_hpt_frequency
= ar5315_cpu_frequency() / 2;
363 /* Enable the specified AR531X_MISC_IRQ interrupt */
365 ar5315_misc_intr_enable(unsigned int irq
)
369 imr
= sysRegRead(AR5315_IMR
);
372 case AR531X_MISC_IRQ_TIMER
:
373 imr
|= AR5315_ISR_TIMER
;
376 case AR531X_MISC_IRQ_AHB_PROC
:
377 imr
|= AR5315_ISR_AHB
;
380 case AR531X_MISC_IRQ_AHB_DMA
:
384 case AR531X_MISC_IRQ_GPIO
:
385 imr
|= AR5315_ISR_GPIO
;
388 case AR531X_MISC_IRQ_UART0
:
389 imr
|= AR5315_ISR_UART0
;
393 case AR531X_MISC_IRQ_WATCHDOG
:
394 imr
|= AR5315_ISR_WD
;
397 case AR531X_MISC_IRQ_LOCAL
:
402 sysRegWrite(AR5315_IMR
, imr
);
403 imr
=sysRegRead(AR5315_IMR
); /* flush write buffer */
406 /* Disable the specified AR531X_MISC_IRQ interrupt */
408 ar5315_misc_intr_disable(unsigned int irq
)
412 imr
= sysRegRead(AR5315_IMR
);
415 case AR531X_MISC_IRQ_TIMER
:
416 imr
&= (~AR5315_ISR_TIMER
);
419 case AR531X_MISC_IRQ_AHB_PROC
:
420 imr
&= (~AR5315_ISR_AHB
);
423 case AR531X_MISC_IRQ_AHB_DMA
:
427 case AR531X_MISC_IRQ_GPIO
:
428 imr
&= ~AR5315_ISR_GPIO
;
431 case AR531X_MISC_IRQ_UART0
:
432 imr
&= (~AR5315_ISR_UART0
);
435 case AR531X_MISC_IRQ_WATCHDOG
:
436 imr
&= (~AR5315_ISR_WD
);
439 case AR531X_MISC_IRQ_LOCAL
:
444 sysRegWrite(AR5315_IMR
, imr
);
445 sysRegRead(AR5315_IMR
); /* flush write buffer */
448 /* Turn on the specified AR531X_MISC_IRQ interrupt */
450 ar5315_misc_intr_startup(unsigned int irq
)
452 ar5315_misc_intr_enable(irq
);
456 /* Turn off the specified AR531X_MISC_IRQ interrupt */
458 ar5315_misc_intr_shutdown(unsigned int irq
)
460 ar5315_misc_intr_disable(irq
);
464 ar5315_misc_intr_ack(unsigned int irq
)
466 ar5315_misc_intr_disable(irq
);
470 ar5315_misc_intr_end(unsigned int irq
)
472 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
473 ar5315_misc_intr_enable(irq
);
476 static struct irq_chip ar5315_misc_intr_controller
= {
477 .typename
= "AR5315 misc",
478 .startup
= ar5315_misc_intr_startup
,
479 .shutdown
= ar5315_misc_intr_shutdown
,
480 .enable
= ar5315_misc_intr_enable
,
481 .disable
= ar5315_misc_intr_disable
,
482 .ack
= ar5315_misc_intr_ack
,
483 .end
= ar5315_misc_intr_end
,
486 static irqreturn_t
ar5315_ahb_proc_handler(int cpl
, void *dev_id
)
488 sysRegWrite(AR5315_AHB_ERR0
,AHB_ERROR_DET
);
489 sysRegRead(AR5315_AHB_ERR1
);
491 printk("AHB fatal error\n");
492 machine_restart("AHB error"); /* Catastrophic failure */
497 static struct irqaction ar5315_ahb_proc_interrupt
= {
498 .handler
= ar5315_ahb_proc_handler
,
499 .flags
= SA_INTERRUPT
,
500 .name
= "ar5315_ahb_proc_interrupt",
504 static struct irqaction cascade
= {
505 .handler
= no_action
,
506 .flags
= SA_INTERRUPT
,
510 void ar5315_misc_intr_init(int irq_base
)
514 for (i
= irq_base
; i
< irq_base
+ AR531X_MISC_IRQ_COUNT
; i
++) {
515 irq_desc
[i
].status
= IRQ_DISABLED
;
516 irq_desc
[i
].action
= NULL
;
517 irq_desc
[i
].depth
= 1;
518 irq_desc
[i
].chip
= &ar5315_misc_intr_controller
;
520 setup_irq(AR531X_MISC_IRQ_AHB_PROC
, &ar5315_ahb_proc_interrupt
);
521 setup_irq(AR5315_IRQ_MISC_INTRS
, &cascade
);
524 void __init
ar5315_prom_init(void)
529 memcfg
= sysRegRead(AR5315_MEM_CFG
);
530 memsize
= 1 + ((memcfg
& SDRAM_DATA_WIDTH_M
) >> SDRAM_DATA_WIDTH_S
);
531 memsize
<<= 1 + ((memcfg
& SDRAM_COL_WIDTH_M
) >> SDRAM_COL_WIDTH_S
);
532 memsize
<<= 1 + ((memcfg
& SDRAM_ROW_WIDTH_M
) >> SDRAM_ROW_WIDTH_S
);
534 add_memory_region(0, memsize
, BOOT_MEM_RAM
);
536 /* Initialize it to AR2315 for now. Real detection will be done
537 * in ar5315_init_devices() */
538 mips_machtype
= MACH_ATHEROS_AR2315
;
541 void __init
ar5315_plat_setup(void)
543 unsigned int config
= read_c0_config();
545 /* Clear any lingering AHB errors */
546 write_c0_config(config
& ~0x3);
547 sysRegWrite(AR5315_AHB_ERR0
,AHB_ERROR_DET
);
548 sysRegRead(AR5315_AHB_ERR1
);
549 sysRegWrite(AR5315_WDC
, WDC_IGNORE_EXPIRATION
);
551 board_time_init
= ar5315_time_init
;
553 _machine_restart
= ar5315_restart
;
554 _machine_halt
= ar5315_halt
;
555 pm_power_off
= ar5315_power_off
;
557 serial_setup(KSEG1ADDR(AR5315_UART0
), ar5315_apb_frequency());
560 arch_initcall(ar5315_init_devices
);