ar71xx: rewrite SPI drivers for the RB4xx boards
[openwrt.git] / target / linux / xburst / patches-2.6.35 / 006-clocksource.patch
1 From ebf176a38105200dca51a96ad1535c8d56235653 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 19 Jun 2010 04:08:10 +0000
4 Subject: [PATCH] MIPS: JZ4740: Add clocksource/clockevent support.
5
6 Add clocksource and clockevent support for the timer/counter unit on
7 JZ4740 SoCs.
8
9 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
10 Cc: linux-mips@linux-mips.org
11 Cc: linux-kernel@vger.kernel.org
12 Patchwork: https://patchwork.linux-mips.org/patch/1397/
13 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
14 ---
15 arch/mips/jz4740/time.c | 144 +++++++++++++++++++++++++++++++++++++++++++++++
16 1 files changed, 144 insertions(+), 0 deletions(-)
17 create mode 100644 arch/mips/jz4740/time.c
18
19 --- /dev/null
20 +++ b/arch/mips/jz4740/time.c
21 @@ -0,0 +1,144 @@
22 +/*
23 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
24 + * JZ4740 platform time support
25 + *
26 + * This program is free software; you can redistribute it and/or modify it
27 + * under the terms of the GNU General Public License as published by the
28 + * Free Software Foundation; either version 2 of the License, or (at your
29 + * option) any later version.
30 + *
31 + * You should have received a copy of the GNU General Public License along
32 + * with this program; if not, write to the Free Software Foundation, Inc.,
33 + * 675 Mass Ave, Cambridge, MA 02139, USA.
34 + *
35 + */
36 +
37 +#include <linux/interrupt.h>
38 +#include <linux/kernel.h>
39 +#include <linux/time.h>
40 +
41 +#include <linux/clockchips.h>
42 +
43 +#include <asm/mach-jz4740/irq.h>
44 +#include <asm/time.h>
45 +
46 +#include "clock.h"
47 +#include "timer.h"
48 +
49 +#define TIMER_CLOCKEVENT 0
50 +#define TIMER_CLOCKSOURCE 1
51 +
52 +static uint16_t jz4740_jiffies_per_tick;
53 +
54 +static cycle_t jz4740_clocksource_read(struct clocksource *cs)
55 +{
56 + return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
57 +}
58 +
59 +static struct clocksource jz4740_clocksource = {
60 + .name = "jz4740-timer",
61 + .rating = 200,
62 + .read = jz4740_clocksource_read,
63 + .mask = CLOCKSOURCE_MASK(16),
64 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
65 +};
66 +
67 +static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
68 +{
69 + struct clock_event_device *cd = devid;
70 +
71 + jz4740_timer_ack_full(TIMER_CLOCKEVENT);
72 +
73 + if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
74 + jz4740_timer_disable(TIMER_CLOCKEVENT);
75 +
76 + cd->event_handler(cd);
77 +
78 + return IRQ_HANDLED;
79 +}
80 +
81 +static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
82 + struct clock_event_device *cd)
83 +{
84 + switch (mode) {
85 + case CLOCK_EVT_MODE_PERIODIC:
86 + jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
87 + jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
88 + case CLOCK_EVT_MODE_RESUME:
89 + jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
90 + jz4740_timer_enable(TIMER_CLOCKEVENT);
91 + break;
92 + case CLOCK_EVT_MODE_ONESHOT:
93 + case CLOCK_EVT_MODE_SHUTDOWN:
94 + jz4740_timer_disable(TIMER_CLOCKEVENT);
95 + break;
96 + default:
97 + break;
98 + }
99 +}
100 +
101 +static int jz4740_clockevent_set_next(unsigned long evt,
102 + struct clock_event_device *cd)
103 +{
104 + jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
105 + jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
106 + jz4740_timer_enable(TIMER_CLOCKEVENT);
107 +
108 + return 0;
109 +}
110 +
111 +static struct clock_event_device jz4740_clockevent = {
112 + .name = "jz4740-timer",
113 + .features = CLOCK_EVT_FEAT_PERIODIC,
114 + .set_next_event = jz4740_clockevent_set_next,
115 + .set_mode = jz4740_clockevent_set_mode,
116 + .rating = 200,
117 + .irq = JZ4740_IRQ_TCU0,
118 +};
119 +
120 +static struct irqaction timer_irqaction = {
121 + .handler = jz4740_clockevent_irq,
122 + .flags = IRQF_PERCPU | IRQF_TIMER,
123 + .name = "jz4740-timerirq",
124 + .dev_id = &jz4740_clockevent,
125 +};
126 +
127 +void __init plat_time_init(void)
128 +{
129 + int ret;
130 + uint32_t clk_rate;
131 + uint16_t ctrl;
132 +
133 + jz4740_timer_init();
134 +
135 + clk_rate = jz4740_clock_bdata.ext_rate >> 4;
136 + jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
137 +
138 + clockevent_set_clock(&jz4740_clockevent, clk_rate);
139 + jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
140 + jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
141 + jz4740_clockevent.cpumask = cpumask_of(0);
142 +
143 + clockevents_register_device(&jz4740_clockevent);
144 +
145 + clocksource_set_clock(&jz4740_clocksource, clk_rate);
146 + ret = clocksource_register(&jz4740_clocksource);
147 +
148 + if (ret)
149 + printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
150 +
151 + setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
152 +
153 + ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
154 +
155 + jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
156 + jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
157 +
158 + jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
159 + jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
160 +
161 + jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
162 +
163 + jz4740_timer_enable(TIMER_CLOCKEVENT);
164 + jz4740_timer_enable(TIMER_CLOCKSOURCE);
165 +}
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