target/linux/ar71xx/patches-3.2/009-MIPS-ath79-Add-AR933X-specific-IRQ-initialization.patch

   1 From f2963f6a811da75e2531fd1312aa124cd73f15d5 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Mon, 20 Jun 2011 21:26:06 +0200
   4 Subject: [PATCH 09/27] MIPS: ath79: Add AR933X specific IRQ initialization
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 Cc: linux-mips@linux-mips.org
   8 Cc: Kathy Giori <kgiori@qca.qualcomm.com>
   9 Cc: "Luis R.  Rodriguez" <rodrigue@qca.qualcomm.com>
  10 Patchwork: https://patchwork.linux-mips.org/patch/2530/
  11 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  12 ---
  13  arch/mips/ath79/irq.c                          |    5 ++++-
  14  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    5 +++++
  15  2 files changed, 9 insertions(+), 1 deletions(-)
  16
  17 --- a/arch/mips/ath79/irq.c
  18 +++ b/arch/mips/ath79/irq.c
  19 @@ -129,7 +129,7 @@ static void __init ath79_misc_irq_init(v
  20
  21         if (soc_is_ar71xx() || soc_is_ar913x())
  22                 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
  23 -       else if (soc_is_ar724x())
  24 +       else if (soc_is_ar724x() || soc_is_ar933x())
  25                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
  26         else
  27                 BUG();
  28 @@ -186,6 +186,9 @@ void __init arch_init_irq(void)
  29         } else if (soc_is_ar913x()) {
  30                 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
  31                 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
  32 +       } else if (soc_is_ar933x()) {
  33 +               ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
  34 +               ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
  35         } else
  36                 BUG();
  37
  38 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  39 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  40 @@ -82,6 +82,11 @@
  41  #define AR913X_DDR_REG_FLUSH_USB       0x84
  42  #define AR913X_DDR_REG_FLUSH_WMAC      0x88
  43
  44 +#define AR933X_DDR_REG_FLUSH_GE0       0x7c
  45 +#define AR933X_DDR_REG_FLUSH_GE1       0x80
  46 +#define AR933X_DDR_REG_FLUSH_USB       0x84
  47 +#define AR933X_DDR_REG_FLUSH_WMAC      0x88
  48 +
  49  /*
  50   * PLL block
  51   */