Add the infrastructure to support different flash sizes/address
[openwrt.git] / target / linux / ar7-2.6 / patches / 100-board_support.patch
1 diff -Nru linux-2.6.19.2/arch/mips/Kconfig linux-ar7/arch/mips/Kconfig
2 --- linux-2.6.19.2/arch/mips/Kconfig 2006-12-12 02:32:53.000000000 +0700
3 +++ linux-ar7/arch/mips/Kconfig 2007-01-29 21:52:21.000000000 +0700
4 @@ -12,6 +12,18 @@
5 prompt "System type"
6 default SGI_IP22
7
8 +config AR7
9 + bool "Texas Instruments AR7"
10 + select BOOT_ELF32
11 + select DMA_NONCOHERENT
12 + select HW_HAS_PCI
13 + select IRQ_CPU
14 + select SWAP_IO_SPACE
15 + select SYS_HAS_CPU_MIPS32_R1
16 + select SYS_SUPPORTS_32BIT_KERNEL
17 + select SYS_SUPPORTS_LITTLE_ENDIAN
18 + select NEED_MULTIPLE_NODES
19 +
20 config MIPS_MTX1
21 bool "4G Systems MTX-1 board"
22 select DMA_NONCOHERENT
23 diff -Nru linux-2.6.19.2/arch/mips/Makefile linux-ar7/arch/mips/Makefile
24 --- linux-2.6.19.2/arch/mips/Makefile 2006-12-12 02:32:53.000000000 +0700
25 +++ linux-ar7/arch/mips/Makefile 2007-01-29 21:52:21.000000000 +0700
26 @@ -158,6 +158,13 @@
27 #
28
29 #
30 +# Texas Instruments AR7
31 +#
32 +core-$(CONFIG_AR7) += arch/mips/ar7/
33 +cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
34 +load-$(CONFIG_AR7) += 0xffffffff94100000
35 +
36 +#
37 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
38 #
39 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
40 diff -Nru linux-2.6.19.2/arch/mips/kernel/setup.c linux-ar7/arch/mips/kernel/setup.c
41 --- linux-2.6.19.2orig/arch/mips/kernel/setup.c 2006-12-12 02:32:53.000000000 +0700
42 +++ linux-ar7/arch/mips/kernel/setup.c 2007-03-04 22:32:13.000000000 +0700
43 @@ -236,7 +236,7 @@
44 * Initialize the bootmem allocator. It also setup initrd related data
45 * if needed.
46 */
47 -#ifdef CONFIG_SGI_IP27
48 +#ifdef CONFIG_NEED_MULTIPLE_NODES
49
50 static void __init bootmem_init(void)
51 {
52 @@ -244,7 +244,7 @@
53 finalize_initrd();
54 }
55
56 -#else /* !CONFIG_SGI_IP27 */
57 +#else /* !CONFIG_NEED_MULTIPLE_NODES */
58
59 static void __init bootmem_init(void)
60 {
61 @@ -349,7 +349,7 @@
62 finalize_initrd();
63 }
64
65 -#endif /* CONFIG_SGI_IP27 */
66 +#endif /* CONFIG_NEED_MULTIPLE_NODES */
67
68 /*
69 * arch_mem_init - initialize memory managment subsystem
70 diff -Nru linux-2.6.19.2/arch/mips/kernel/traps.c linux-ar7/arch/mips/kernel/traps.c
71 --- linux-2.6.19.2/arch/mips/kernel/traps.c 2007-01-11 02:10:37.000000000 +0700
72 +++ linux-ar7/arch/mips/kernel/traps.c 2007-03-15 13:19:19.000000000 +0700
73 @@ -1072,11 +1072,6 @@
74 unsigned long exception_handlers[32];
75 unsigned long vi_handlers[64];
76
77 -/*
78 - * As a side effect of the way this is implemented we're limited
79 - * to interrupt handlers in the address range from
80 - * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
81 - */
82 void *set_except_vector(int n, void *addr)
83 {
84 unsigned long handler = (unsigned long) addr;
85 @@ -1084,9 +1079,15 @@
86
87 exception_handlers[n] = handler;
88 if (n == 0 && cpu_has_divec) {
89 - *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
90 - (0x03ffffff & (handler >> 2));
91 - flush_icache_range(ebase + 0x200, ebase + 0x204);
92 + /* lui k0, 0x0000 */
93 + *(volatile u32 *)(CAC_BASE+0x200) = 0x3c1a0000 | (handler >> 16);
94 + /* ori k0, 0x0000 */
95 + *(volatile u32 *)(CAC_BASE+0x204) = 0x375a0000 | (handler & 0xffff);
96 + /* jr k0 */
97 + *(volatile u32 *)(CAC_BASE+0x208) = 0x03400008;
98 + /* nop */
99 + *(volatile u32 *)(CAC_BASE+0x20C) = 0x00000000;
100 + flush_icache_range(CAC_BASE+0x200, CAC_BASE+0x210);
101 }
102 return (void *)old_handler;
103 }
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