2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
25 static void ar71xx_pci_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
29 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS
) &
30 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
32 if (pending
& PCI_INT_DEV0
)
33 generic_handle_irq(AR71XX_PCI_IRQ_DEV0
);
35 else if (pending
& PCI_INT_DEV1
)
36 generic_handle_irq(AR71XX_PCI_IRQ_DEV1
);
38 else if (pending
& PCI_INT_DEV2
)
39 generic_handle_irq(AR71XX_PCI_IRQ_DEV2
);
41 else if (pending
& PCI_INT_CORE
)
42 generic_handle_irq(AR71XX_PCI_IRQ_CORE
);
48 static void ar71xx_pci_irq_unmask(unsigned int irq
)
50 irq
-= AR71XX_PCI_IRQ_BASE
;
51 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
52 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) | (1 << irq
));
55 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
58 static void ar71xx_pci_irq_mask(unsigned int irq
)
60 irq
-= AR71XX_PCI_IRQ_BASE
;
61 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
62 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) & ~(1 << irq
));
65 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
68 static struct irq_chip ar71xx_pci_irq_chip
= {
69 .name
= "AR71XX PCI ",
70 .mask
= ar71xx_pci_irq_mask
,
71 .unmask
= ar71xx_pci_irq_unmask
,
72 .mask_ack
= ar71xx_pci_irq_mask
,
75 static void __init
ar71xx_pci_irq_init(void)
79 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
, 0);
80 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS
, 0);
82 for (i
= AR71XX_PCI_IRQ_BASE
;
83 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
84 irq_desc
[i
].status
= IRQ_DISABLED
;
85 set_irq_chip_and_handler(i
, &ar71xx_pci_irq_chip
,
89 set_irq_chained_handler(AR71XX_CPU_IRQ_IP2
, ar71xx_pci_irq_handler
);
92 static void ar724x_pci_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
96 pending
= ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
) &
97 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
99 if (pending
& AR724X_PCI_INT_DEV0
)
100 generic_handle_irq(AR71XX_PCI_IRQ_DEV0
);
103 spurious_interrupt();
106 static void ar724x_pci_irq_unmask(unsigned int irq
)
109 case AR71XX_PCI_IRQ_DEV0
:
110 irq
-= AR71XX_PCI_IRQ_BASE
;
111 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
,
112 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
) |
113 AR724X_PCI_INT_DEV0
);
115 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
119 static void ar724x_pci_irq_mask(unsigned int irq
)
122 case AR71XX_PCI_IRQ_DEV0
:
123 irq
-= AR71XX_PCI_IRQ_BASE
;
124 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
,
125 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
) &
126 ~AR724X_PCI_INT_DEV0
);
128 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
130 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS
,
131 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
) |
132 AR724X_PCI_INT_DEV0
);
134 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
);
138 static struct irq_chip ar724x_pci_irq_chip
= {
139 .name
= "AR724X PCI ",
140 .mask
= ar724x_pci_irq_mask
,
141 .unmask
= ar724x_pci_irq_unmask
,
142 .mask_ack
= ar724x_pci_irq_mask
,
145 static void __init
ar724x_pci_irq_init(void)
150 t
= ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE
);
151 if (t
& (AR724X_RESET_PCIE
| AR724X_RESET_PCIE_PHY
|
152 AR724X_RESET_PCIE_PHY_SERIAL
)) {
156 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
, 0);
157 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS
, 0);
159 for (i
= AR71XX_PCI_IRQ_BASE
;
160 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
161 irq_desc
[i
].status
= IRQ_DISABLED
;
162 set_irq_chip_and_handler(i
, &ar724x_pci_irq_chip
,
166 set_irq_chained_handler(AR71XX_CPU_IRQ_IP2
, ar724x_pci_irq_handler
);
169 static inline void ar71xx_pci_irq_init(void) {};
170 static inline void ar724x_pci_irq_init(void) {};
171 #endif /* CONFIG_PCI */
173 static void ar71xx_gpio_irq_dispatch(void)
177 pending
= ar71xx_gpio_rr(GPIO_REG_INT_PENDING
)
178 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
181 do_IRQ(AR71XX_GPIO_IRQ_BASE
+ fls(pending
) - 1);
183 spurious_interrupt();
186 static void ar71xx_gpio_irq_unmask(unsigned int irq
)
188 irq
-= AR71XX_GPIO_IRQ_BASE
;
189 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
190 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) | (1 << irq
));
193 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
196 static void ar71xx_gpio_irq_mask(unsigned int irq
)
198 irq
-= AR71XX_GPIO_IRQ_BASE
;
199 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
200 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) & ~(1 << irq
));
203 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
207 static int ar71xx_gpio_irq_set_type(unsigned int irq
, unsigned int flow_type
)
209 /* TODO: implement */
213 #define ar71xx_gpio_irq_set_type NULL
216 static struct irq_chip ar71xx_gpio_irq_chip
= {
217 .name
= "AR71XX GPIO",
218 .unmask
= ar71xx_gpio_irq_unmask
,
219 .mask
= ar71xx_gpio_irq_mask
,
220 .mask_ack
= ar71xx_gpio_irq_mask
,
221 .set_type
= ar71xx_gpio_irq_set_type
,
224 static struct irqaction ar71xx_gpio_irqaction
= {
225 .handler
= no_action
,
226 .name
= "cascade [AR71XX GPIO]",
229 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
230 #define GPIO_INT_ALL 0xffff
232 static void __init
ar71xx_gpio_irq_init(void)
236 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
, 0);
237 ar71xx_gpio_wr(GPIO_REG_INT_PENDING
, 0);
239 /* setup type of all GPIO interrupts to level sensitive */
240 ar71xx_gpio_wr(GPIO_REG_INT_TYPE
, GPIO_INT_ALL
);
242 /* setup polarity of all GPIO interrupts to active high */
243 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY
, GPIO_INT_ALL
);
245 for (i
= AR71XX_GPIO_IRQ_BASE
;
246 i
< AR71XX_GPIO_IRQ_BASE
+ AR71XX_GPIO_IRQ_COUNT
; i
++) {
247 irq_desc
[i
].status
= GPIO_IRQ_INIT_STATUS
;
248 set_irq_chip_and_handler(i
, &ar71xx_gpio_irq_chip
,
252 setup_irq(AR71XX_MISC_IRQ_GPIO
, &ar71xx_gpio_irqaction
);
255 static void ar71xx_misc_irq_dispatch(void)
259 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
)
260 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
262 if (pending
& MISC_INT_UART
)
263 do_IRQ(AR71XX_MISC_IRQ_UART
);
265 else if (pending
& MISC_INT_DMA
)
266 do_IRQ(AR71XX_MISC_IRQ_DMA
);
268 else if (pending
& MISC_INT_PERFC
)
269 do_IRQ(AR71XX_MISC_IRQ_PERFC
);
271 else if (pending
& MISC_INT_TIMER
)
272 do_IRQ(AR71XX_MISC_IRQ_TIMER
);
274 else if (pending
& MISC_INT_OHCI
)
275 do_IRQ(AR71XX_MISC_IRQ_OHCI
);
277 else if (pending
& MISC_INT_ERROR
)
278 do_IRQ(AR71XX_MISC_IRQ_ERROR
);
280 else if (pending
& MISC_INT_GPIO
)
281 ar71xx_gpio_irq_dispatch();
283 else if (pending
& MISC_INT_WDOG
)
284 do_IRQ(AR71XX_MISC_IRQ_WDOG
);
287 spurious_interrupt();
290 static void ar71xx_misc_irq_unmask(unsigned int irq
)
292 irq
-= AR71XX_MISC_IRQ_BASE
;
293 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
294 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) | (1 << irq
));
297 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
300 static void ar71xx_misc_irq_mask(unsigned int irq
)
302 irq
-= AR71XX_MISC_IRQ_BASE
;
303 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
304 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) & ~(1 << irq
));
307 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
310 static void ar724x_misc_irq_ack(unsigned int irq
)
312 irq
-= AR71XX_MISC_IRQ_BASE
;
313 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
,
314 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
) & ~(1 << irq
));
317 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
);
320 static struct irq_chip ar71xx_misc_irq_chip
= {
321 .name
= "AR71XX MISC",
322 .unmask
= ar71xx_misc_irq_unmask
,
323 .mask
= ar71xx_misc_irq_mask
,
326 static struct irqaction ar71xx_misc_irqaction
= {
327 .handler
= no_action
,
328 .name
= "cascade [AR71XX MISC]",
331 static void __init
ar71xx_misc_irq_init(void)
335 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
, 0);
336 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
, 0);
338 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
339 ar71xx_misc_irq_chip
.ack
= ar724x_misc_irq_ack
;
341 ar71xx_misc_irq_chip
.mask_ack
= ar71xx_misc_irq_mask
;
343 for (i
= AR71XX_MISC_IRQ_BASE
;
344 i
< AR71XX_MISC_IRQ_BASE
+ AR71XX_MISC_IRQ_COUNT
; i
++) {
345 irq_desc
[i
].status
= IRQ_DISABLED
;
346 set_irq_chip_and_handler(i
, &ar71xx_misc_irq_chip
,
350 setup_irq(AR71XX_CPU_IRQ_MISC
, &ar71xx_misc_irqaction
);
353 asmlinkage
void plat_irq_dispatch(void)
355 unsigned long pending
;
357 pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
359 if (pending
& STATUSF_IP7
)
360 do_IRQ(AR71XX_CPU_IRQ_TIMER
);
362 else if (pending
& STATUSF_IP2
)
363 do_IRQ(AR71XX_CPU_IRQ_IP2
);
365 else if (pending
& STATUSF_IP4
)
366 do_IRQ(AR71XX_CPU_IRQ_GE0
);
368 else if (pending
& STATUSF_IP5
)
369 do_IRQ(AR71XX_CPU_IRQ_GE1
);
371 else if (pending
& STATUSF_IP3
)
372 do_IRQ(AR71XX_CPU_IRQ_USB
);
374 else if (pending
& STATUSF_IP6
)
375 ar71xx_misc_irq_dispatch();
378 spurious_interrupt();
381 void __init
arch_init_irq(void)
385 ar71xx_misc_irq_init();
387 cp0_perfcount_irq
= AR71XX_MISC_IRQ_PERFC
;
389 switch (ar71xx_soc
) {
390 case AR71XX_SOC_AR7130
:
391 case AR71XX_SOC_AR7141
:
392 case AR71XX_SOC_AR7161
:
393 ar71xx_pci_irq_init();
395 case AR71XX_SOC_AR7240
:
396 ar724x_pci_irq_init();
402 ar71xx_gpio_irq_init();