target/linux/brcm63xx/files/arch/mips/pci/pci-bcm63xx.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/pci.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <asm/bootinfo.h>
  14
  15 #include "pci-bcm63xx.h"
  16
  17 /* allow PCI to be disabled at runtime depending on board nvram
  18  * configuration */
  19 int bcm63xx_pci_enabled = 0;
  20
  21 static struct resource bcm_pci_mem_resource = {
  22         .name   = "bcm63xx PCI memory space",
  23         .start  = BCM_PCI_MEM_BASE_PA,
  24         .end    = BCM_PCI_MEM_END_PA,
  25         .flags  = IORESOURCE_MEM
  26 };
  27
  28 static struct resource bcm_pci_io_resource = {
  29         .name   = "bcm63xx PCI IO space",
  30         .start  = BCM_PCI_IO_BASE_PA,
  31 #ifdef CONFIG_CARDBUS
  32         .end    = BCM_PCI_IO_HALF_PA,
  33 #else
  34         .end    = BCM_PCI_IO_END_PA,
  35 #endif
  36         .flags  = IORESOURCE_IO
  37 };
  38
  39 struct pci_controller bcm63xx_controller = {
  40         .pci_ops        = &bcm63xx_pci_ops,
  41         .io_resource    = &bcm_pci_io_resource,
  42         .mem_resource   = &bcm_pci_mem_resource,
  43 };
  44
  45 /*
  46  * We handle cardbus  via a fake Cardbus bridge,  memory and io spaces
  47  * have to be  clearly separated from PCI one  since we have different
  48  * memory decoder.
  49  */
  50 #ifdef CONFIG_CARDBUS
  51 static struct resource bcm_cb_mem_resource = {
  52         .name   = "bcm63xx Cardbus memory space",
  53         .start  = BCM_CB_MEM_BASE_PA,
  54         .end    = BCM_CB_MEM_END_PA,
  55         .flags  = IORESOURCE_MEM
  56 };
  57
  58 static struct resource bcm_cb_io_resource = {
  59         .name   = "bcm63xx Cardbus IO space",
  60         .start  = BCM_PCI_IO_HALF_PA + 1,
  61         .end    = BCM_PCI_IO_END_PA,
  62         .flags  = IORESOURCE_IO
  63 };
  64
  65 struct pci_controller bcm63xx_cb_controller = {
  66         .pci_ops        = &bcm63xx_cb_ops,
  67         .io_resource    = &bcm_cb_io_resource,
  68         .mem_resource   = &bcm_cb_mem_resource,
  69 };
  70 #endif
  71
  72 static u32 bcm63xx_int_cfg_readl(u32 reg)
  73 {
  74         u32 tmp;
  75
  76         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
  77         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
  78         bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
  79         iob();
  80         return bcm_mpi_readl(MPI_PCICFGDATA_REG);
  81 }
  82
  83 static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
  84 {
  85         u32 tmp;
  86
  87         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
  88         tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
  89         bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
  90         bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
  91 }
  92
  93 void __iomem *pci_iospace_start;
  94
  95 static int __init bcm63xx_pci_init(void)
  96 {
  97         unsigned int mem_size;
  98         u32 val;
  99
 100         if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
 101                 return -ENODEV;
 102
 103         if (!bcm63xx_pci_enabled)
 104                 return -ENODEV;
 105
 106         /*
 107          * configuration  access are  done through  IO space,  remap 4
 108          * first bytes to access it from CPU.
 109          *
 110          * this means that  no io access from CPU  should happen while
 111          * we do a configuration cycle,  but there's no way we can add
 112          * a spinlock for each io access, so this is currently kind of
 113          * broken on SMP.
 114          */
 115         pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
 116         if (!pci_iospace_start)
 117                 return -ENOMEM;
 118
 119         /* setup local bus to PCI access (PCI memory) */
 120         val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
 121         bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
 122         bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
 123         bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
 124
 125         /* set Cardbus IDSEL (type 0 cfg access on primary bus for
 126          * this IDSEL will be done on Cardbus instead) */
 127         val = bcm_pcmcia_readl(PCMCIA_C1_REG);
 128         val &= ~PCMCIA_C1_CBIDSEL_MASK;
 129         val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
 130         bcm_pcmcia_writel(val, PCMCIA_C1_REG);
 131
 132 #ifdef CONFIG_CARDBUS
 133         /* setup local bus to PCI access (Cardbus memory) */
 134         val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
 135         bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
 136         bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
 137         val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
 138         bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
 139 #else
 140         /* disable second access windows */
 141         bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
 142 #endif
 143
 144         /* setup local bus  to PCI access (IO memory),  we have only 1
 145          * IO window  for both PCI  and cardbus, but it  cannot handle
 146          * both  at the  same time,  assume standard  PCI for  now, if
 147          * cardbus card has  IO zone, PCI fixup will  change window to
 148          * cardbus */
 149         val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
 150         bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
 151         bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
 152         bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
 153
 154         /* enable PCI related GPIO pins */
 155         bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
 156
 157         /* setup PCI to local bus access, used by PCI device to target
 158          * local RAM while bus mastering */
 159         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 160         if (BCMCPU_IS_6358())
 161                 val = MPI_SP0_REMAP_ENABLE_MASK;
 162         else
 163                 val = 0;
 164         bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
 165
 166         bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
 167         bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
 168
 169         mem_size = bcm63xx_get_memory_size();
 170
 171         /* 6348 before rev b0 exposes only 16 MB of RAM memory through
 172          * PCI, throw a warning if we have more memory */
 173         if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
 174                 if (mem_size > (16 * 1024 * 1024))
 175                         printk(KERN_WARNING "bcm63xx: this CPU "
 176                                "revision cannot handle more than 16MB "
 177                                "of RAM for PCI bus mastering\n");
 178         } else {
 179                 /* setup sp0 range to local RAM size */
 180                 bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
 181                 bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
 182         }
 183
 184         /* change  host bridge  retry  counter to  infinite number  of
 185          * retry,  needed for  some broadcom  wifi cards  with Silicon
 186          * Backplane bus where access to srom seems very slow  */
 187         val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
 188         val &= ~REG_TIMER_RETRY_MASK;
 189         bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 190
 191         /* enable memory decoder and bus mastering */
 192         val = bcm63xx_int_cfg_readl(PCI_COMMAND);
 193         val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 194         bcm63xx_int_cfg_writel(val, PCI_COMMAND);
 195
 196         /* enable read prefetching & disable byte swapping for bus
 197          * mastering transfers */
 198         val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
 199         val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 200         val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 201         val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 202         val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 203         bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
 204
 205         /* enable pci interrupt */
 206         val = bcm_mpi_readl(MPI_LOCINT_REG);
 207         val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 208         bcm_mpi_writel(val, MPI_LOCINT_REG);
 209
 210         register_pci_controller(&bcm63xx_controller);
 211
 212 #ifdef CONFIG_CARDBUS
 213         register_pci_controller(&bcm63xx_cb_controller);
 214 #endif
 215
 216         /* mark memory space used for IO mapping as reserved */
 217         request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
 218                            "bcm63xx PCI IO space");
 219         return 0;
 220 }
 221
 222 arch_initcall(bcm63xx_pci_init);