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ar71xx: don't init PCI irqs on the AR7240 if the PCIe subsystem are in reset
[openwrt.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c
1 /*
2 * Atheros AR71xx PCI host controller driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/resource.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/pci.h>
19 #include <linux/pci_regs.h>
20
21 #include <asm/mach-ar71xx/ar71xx.h>
22 #include <asm/mach-ar71xx/pci.h>
23
24 #undef DEBUG
25 #ifdef DEBUG
26 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
27 #else
28 #define DBG(fmt, args...)
29 #endif
30
31 #define AR71XX_PCI_DELAY 100 /* msecs */
32
33 #if 0
34 #define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
35 #else
36 #define PCI_IDSEL_BASE 0
37 #endif
38
39 static void __iomem *ar71xx_pcicfg_base;
40 static DEFINE_SPINLOCK(ar71xx_pci_lock);
41 static int ar71xx_pci_fixup_enable;
42
43 static inline void ar71xx_pci_delay(void)
44 {
45 mdelay(AR71XX_PCI_DELAY);
46 }
47
48 static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
49 {
50 return __raw_readl(ar71xx_pcicfg_base + reg);
51 }
52
53 static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
54 {
55 __raw_writel(val, ar71xx_pcicfg_base + reg);
56 }
57
58 /* Byte lane enable bits */
59 static u8 ble_table[4][4] = {
60 {0x0, 0xf, 0xf, 0xf},
61 {0xe, 0xd, 0xb, 0x7},
62 {0xc, 0xf, 0x3, 0xf},
63 {0xf, 0xf, 0xf, 0xf},
64 };
65
66 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
67 {
68 u32 t;
69
70 t = ble_table[size & 3][where & 3];
71 BUG_ON(t == 0xf);
72 t <<= (local) ? 20 : 4;
73 return t;
74 }
75
76 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
77 int where)
78 {
79 u32 ret;
80
81 if (!bus->number) {
82 /* type 0 */
83 ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
84 | (PCI_FUNC(devfn) << 8) | (where & ~3);
85 } else {
86 /* type 1 */
87 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
88 | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
89 }
90
91 return ret;
92 }
93
94 int ar71xx_pci_be_handler(int is_fixup)
95 {
96 u32 pci_err;
97 u32 ahb_err;
98
99 pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
100 if (pci_err) {
101 if (!is_fixup)
102 printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
103 pci_err,
104 ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
105
106 ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
107 }
108
109 ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
110 if (ahb_err) {
111 if (!is_fixup)
112 printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
113 ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
114
115 ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
116 }
117
118 return ((ahb_err | pci_err) ? 1 : 0);
119 }
120
121 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
122 unsigned int devfn, int where, int size, u32 cmd)
123 {
124 u32 addr;
125
126 addr = ar71xx_pci_bus_addr(bus, devfn, where);
127
128 DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
129 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
130 where, size, addr);
131
132 ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
133 ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
134 cmd | ar71xx_pci_get_ble(where, size, 0));
135
136 return ar71xx_pci_be_handler(1);
137 }
138
139 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
140 int where, int size, u32 *value)
141 {
142 static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
143 unsigned long flags;
144 u32 data;
145 int ret;
146
147 ret = PCIBIOS_SUCCESSFUL;
148
149 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
150 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
151
152 spin_lock_irqsave(&ar71xx_pci_lock, flags);
153
154 if (bus->number == 0 && devfn == 0) {
155 u32 t;
156
157 t = PCI_CRP_CMD_READ | (where & ~3);
158
159 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
160 data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
161
162 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
163
164 } else {
165 int err;
166
167 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
168 PCI_CFG_CMD_READ);
169
170 if (err == 0) {
171 data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
172 } else {
173 ret = PCIBIOS_DEVICE_NOT_FOUND;
174 data = ~0;
175 }
176 }
177
178 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
179
180 DBG("PCI: read config: data=%08x raw=%08x\n",
181 (data >> (8 * (where & 3))) & mask[size & 7], data);
182
183 *value = (data >> (8 * (where & 3))) & mask[size & 7];
184
185 return ret;
186 }
187
188 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
189 int where, int size, u32 value)
190 {
191 unsigned long flags;
192 int ret;
193
194 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
195 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
196 where, size, value);
197
198 value = value << (8 * (where & 3));
199 ret = PCIBIOS_SUCCESSFUL;
200
201 spin_lock_irqsave(&ar71xx_pci_lock, flags);
202 if (bus->number == 0 && devfn == 0) {
203 u32 t;
204
205 t = PCI_CRP_CMD_WRITE | (where & ~3);
206 t |= ar71xx_pci_get_ble(where, size, 1);
207
208 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
209
210 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
211 ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
212 } else {
213 int err;
214
215 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
216 PCI_CFG_CMD_WRITE);
217
218 if (err == 0)
219 ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
220 else
221 ret = PCIBIOS_DEVICE_NOT_FOUND;
222 }
223 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
224
225 return ret;
226 }
227
228 static void ar71xx_pci_fixup(struct pci_dev *dev)
229 {
230 u32 t;
231
232 if (!ar71xx_pci_fixup_enable)
233 return;
234
235 if (dev->bus->number != 0 || dev->devfn != 0)
236 return;
237
238 DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
239 dev->vendor, dev->device);
240
241 /* setup COMMAND register */
242 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
243 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
244
245 pci_write_config_word(dev, PCI_COMMAND, t);
246 }
247 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
248
249 int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
250 uint8_t pin)
251 {
252 int irq = -1;
253 int i;
254
255 slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
256
257 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
258 struct ar71xx_pci_irq *entry;
259
260 entry = &ar71xx_pci_irq_map[i];
261 if (entry->slot == slot && entry->pin == pin) {
262 irq = entry->irq;
263 break;
264 }
265 }
266
267 if (irq < 0) {
268 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
269 pin, pci_name((struct pci_dev *)dev));
270 } else {
271 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
272 irq, pin, pci_name((struct pci_dev *)dev));
273 }
274
275 return irq;
276 }
277
278 static struct pci_ops ar71xx_pci_ops = {
279 .read = ar71xx_pci_read_config,
280 .write = ar71xx_pci_write_config,
281 };
282
283 static struct resource ar71xx_pci_io_resource = {
284 .name = "PCI IO space",
285 .start = 0,
286 .end = 0,
287 .flags = IORESOURCE_IO,
288 };
289
290 static struct resource ar71xx_pci_mem_resource = {
291 .name = "PCI memory space",
292 .start = AR71XX_PCI_MEM_BASE,
293 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
294 .flags = IORESOURCE_MEM
295 };
296
297 static struct pci_controller ar71xx_pci_controller = {
298 .pci_ops = &ar71xx_pci_ops,
299 .mem_resource = &ar71xx_pci_mem_resource,
300 .io_resource = &ar71xx_pci_io_resource,
301 };
302
303 int __init ar71xx_pcibios_init(void)
304 {
305 ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
306 ar71xx_pci_delay();
307
308 ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
309 ar71xx_pci_delay();
310
311 ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
312 AR71XX_PCI_CFG_SIZE);
313
314 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
315 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
316 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
317 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
318 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
319 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
320 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
321 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
322
323 ar71xx_pci_delay();
324
325 /* clear bus errors */
326 (void)ar71xx_pci_be_handler(1);
327
328 ar71xx_pci_fixup_enable = 1;
329 register_pci_controller(&ar71xx_pci_controller);
330
331 return 0;
332 }
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