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[ar71xx] tune rtl8366s default config, make vlan 1 cpu port tagged and use eth0.1...
[openwrt.git] / target / linux / generic / patches-2.6.32 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -373,6 +373,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
4 {
5 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
6 }
7 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
8
9 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
10 {
11 --- a/drivers/ssb/driver_chipcommon_pmu.c
12 +++ b/drivers/ssb/driver_chipcommon_pmu.c
13 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
14 case 0x5354:
15 ssb_pmu0_pllinit_r0(cc, crystalfreq);
16 break;
17 + case 0x4322:
18 + if (cc->pmu.rev == 2) {
19 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
20 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
21 + }
22 + break;
23 default:
24 ssb_printk(KERN_ERR PFX
25 "ERROR: PLL init unknown for device %04X\n",
26 @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
27
28 switch (bus->chip_id) {
29 case 0x4312:
30 + case 0x4322:
31 /* We keep the default settings:
32 * min_msk = 0xCBB
33 * max_msk = 0x7FFFF
34 --- a/drivers/ssb/driver_gige.c
35 +++ b/drivers/ssb/driver_gige.c
36 @@ -12,6 +12,7 @@
37 #include <linux/ssb/ssb_driver_gige.h>
38 #include <linux/pci.h>
39 #include <linux/pci_regs.h>
40 +#include <linux/slab.h>
41
42
43 /*
44 --- a/drivers/ssb/driver_mipscore.c
45 +++ b/drivers/ssb/driver_mipscore.c
46 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
47 set_irq(dev, irq++);
48 }
49 break;
50 - /* fallthrough */
51 case SSB_DEV_PCI:
52 case SSB_DEV_ETHERNET:
53 case SSB_DEV_ETHERNET_GBIT:
54 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
55 set_irq(dev, irq++);
56 break;
57 }
58 + /* fallthrough */
59 + case SSB_DEV_EXTIF:
60 + set_irq(dev, 0);
61 + break;
62 }
63 }
64 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
65 --- a/drivers/ssb/driver_pcicore.c
66 +++ b/drivers/ssb/driver_pcicore.c
67 @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
68 .pci_ops = &ssb_pcicore_pciops,
69 .io_resource = &ssb_pcicore_io_resource,
70 .mem_resource = &ssb_pcicore_mem_resource,
71 - .mem_offset = 0x24000000,
72 };
73
74 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
75 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
76 -
77 /* This function is called when doing a pci_enable_device().
78 * We must first check if the device is a device on the PCI-core bridge. */
79 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
80 {
81 - struct resource *res;
82 - int pos, size;
83 - u32 *base;
84 -
85 if (d->bus->ops != &ssb_pcicore_pciops) {
86 /* This is not a device on the PCI-core bridge. */
87 return -ENODEV;
88 @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
89 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
90 pci_name(d));
91
92 - /* Fix up resource bases */
93 - for (pos = 0; pos < 6; pos++) {
94 - res = &d->resource[pos];
95 - if (res->flags & IORESOURCE_IO)
96 - base = &ssb_pcicore_pcibus_iobase;
97 - else
98 - base = &ssb_pcicore_pcibus_membase;
99 - res->flags |= IORESOURCE_PCI_FIXED;
100 - if (res->end) {
101 - size = res->end - res->start + 1;
102 - if (*base & (size - 1))
103 - *base = (*base + size) & ~(size - 1);
104 - res->start = *base;
105 - res->end = res->start + size - 1;
106 - *base += size;
107 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
108 - }
109 - /* Fix up PCI bridge BAR0 only */
110 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
111 - break;
112 - }
113 /* Fix up interrupt lines */
114 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
115 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
116 @@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
117 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
118
119 /* Enable interrupts for this device. */
120 - if (bus->host_pci &&
121 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
122 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
123 u32 coremask;
124
125 /* Calculate the "coremask" for the device. */
126 coremask = (1 << dev->core_index);
127
128 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
129 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
130 if (err)
131 goto out;
132 --- a/drivers/ssb/main.c
133 +++ b/drivers/ssb/main.c
134 @@ -18,6 +18,7 @@
135 #include <linux/dma-mapping.h>
136 #include <linux/pci.h>
137 #include <linux/mmc/sdio_func.h>
138 +#include <linux/slab.h>
139
140 #include <pcmcia/cs_types.h>
141 #include <pcmcia/cs.h>
142 @@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
143 put_device(dev->dev);
144 }
145
146 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
147 +{
148 + if (drv)
149 + get_driver(&drv->drv);
150 + return drv;
151 +}
152 +
153 +static inline void ssb_driver_put(struct ssb_driver *drv)
154 +{
155 + if (drv)
156 + put_driver(&drv->drv);
157 +}
158 +
159 static int ssb_device_resume(struct device *dev)
160 {
161 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
162 @@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
163 EXPORT_SYMBOL(ssb_bus_suspend);
164
165 #ifdef CONFIG_SSB_SPROM
166 -int ssb_devices_freeze(struct ssb_bus *bus)
167 +/** ssb_devices_freeze - Freeze all devices on the bus.
168 + *
169 + * After freezing no device driver will be handling a device
170 + * on this bus anymore. ssb_devices_thaw() must be called after
171 + * a successful freeze to reactivate the devices.
172 + *
173 + * @bus: The bus.
174 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
175 + */
176 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
177 {
178 - struct ssb_device *dev;
179 - struct ssb_driver *drv;
180 - int err = 0;
181 - int i;
182 - pm_message_t state = PMSG_FREEZE;
183 + struct ssb_device *sdev;
184 + struct ssb_driver *sdrv;
185 + unsigned int i;
186 +
187 + memset(ctx, 0, sizeof(*ctx));
188 + ctx->bus = bus;
189 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
190
191 - /* First check that we are capable to freeze all devices. */
192 for (i = 0; i < bus->nr_devices; i++) {
193 - dev = &(bus->devices[i]);
194 - if (!dev->dev ||
195 - !dev->dev->driver ||
196 - !device_is_registered(dev->dev))
197 - continue;
198 - drv = drv_to_ssb_drv(dev->dev->driver);
199 - if (!drv)
200 + sdev = ssb_device_get(&bus->devices[i]);
201 +
202 + if (!sdev->dev || !sdev->dev->driver ||
203 + !device_is_registered(sdev->dev)) {
204 + ssb_device_put(sdev);
205 continue;
206 - if (!drv->suspend) {
207 - /* Nope, can't suspend this one. */
208 - return -EOPNOTSUPP;
209 }
210 - }
211 - /* Now suspend all devices */
212 - for (i = 0; i < bus->nr_devices; i++) {
213 - dev = &(bus->devices[i]);
214 - if (!dev->dev ||
215 - !dev->dev->driver ||
216 - !device_is_registered(dev->dev))
217 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
218 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
219 + ssb_device_put(sdev);
220 continue;
221 - drv = drv_to_ssb_drv(dev->dev->driver);
222 - if (!drv)
223 - continue;
224 - err = drv->suspend(dev, state);
225 - if (err) {
226 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
227 - dev_name(dev->dev));
228 - goto err_unwind;
229 }
230 + sdrv->remove(sdev);
231 + ctx->device_frozen[i] = 1;
232 }
233
234 return 0;
235 -err_unwind:
236 - for (i--; i >= 0; i--) {
237 - dev = &(bus->devices[i]);
238 - if (!dev->dev ||
239 - !dev->dev->driver ||
240 - !device_is_registered(dev->dev))
241 - continue;
242 - drv = drv_to_ssb_drv(dev->dev->driver);
243 - if (!drv)
244 - continue;
245 - if (drv->resume)
246 - drv->resume(dev);
247 - }
248 - return err;
249 }
250
251 -int ssb_devices_thaw(struct ssb_bus *bus)
252 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
253 + *
254 + * This will re-attach the device drivers and re-init the devices.
255 + *
256 + * @ctx: The context structure from ssb_devices_freeze()
257 + */
258 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
259 {
260 - struct ssb_device *dev;
261 - struct ssb_driver *drv;
262 - int err;
263 - int i;
264 + struct ssb_bus *bus = ctx->bus;
265 + struct ssb_device *sdev;
266 + struct ssb_driver *sdrv;
267 + unsigned int i;
268 + int err, result = 0;
269
270 for (i = 0; i < bus->nr_devices; i++) {
271 - dev = &(bus->devices[i]);
272 - if (!dev->dev ||
273 - !dev->dev->driver ||
274 - !device_is_registered(dev->dev))
275 + if (!ctx->device_frozen[i])
276 continue;
277 - drv = drv_to_ssb_drv(dev->dev->driver);
278 - if (!drv)
279 + sdev = &bus->devices[i];
280 +
281 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
282 continue;
283 - if (SSB_WARN_ON(!drv->resume))
284 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
285 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
286 continue;
287 - err = drv->resume(dev);
288 +
289 + err = sdrv->probe(sdev, &sdev->id);
290 if (err) {
291 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
292 - dev_name(dev->dev));
293 + dev_name(sdev->dev));
294 + result = err;
295 }
296 + ssb_driver_put(sdrv);
297 + ssb_device_put(sdev);
298 }
299
300 - return 0;
301 + return result;
302 }
303 #endif /* CONFIG_SSB_SPROM */
304
305 @@ -490,8 +495,7 @@ static int ssb_devices_register(struct s
306 #endif
307 break;
308 case SSB_BUSTYPE_SDIO:
309 -#ifdef CONFIG_SSB_SDIO
310 - sdev->irq = bus->host_sdio->dev.irq;
311 +#ifdef CONFIG_SSB_SDIOHOST
312 dev->parent = &bus->host_sdio->dev;
313 #endif
314 break;
315 @@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
316 if (!err) {
317 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
318 "PCI device %s\n", dev_name(&host_pci->dev));
319 + } else {
320 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
321 + " of SSB with error %d\n", err);
322 }
323
324 return err;
325 --- a/drivers/ssb/pcihost_wrapper.c
326 +++ b/drivers/ssb/pcihost_wrapper.c
327 @@ -12,6 +12,7 @@
328 */
329
330 #include <linux/pci.h>
331 +#include <linux/slab.h>
332 #include <linux/ssb/ssb.h>
333
334
335 --- a/drivers/ssb/pcmcia.c
336 +++ b/drivers/ssb/pcmcia.c
337 @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
338 } \
339 } while (0)
340
341 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
342 - struct ssb_init_invariants *iv)
343 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
344 + tuple_t *tuple,
345 + void *priv)
346 {
347 - tuple_t tuple;
348 - int res;
349 - unsigned char buf[32];
350 + struct ssb_sprom *sprom = priv;
351 +
352 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
353 + return -EINVAL;
354 + if (tuple->TupleDataLen != ETH_ALEN + 2)
355 + return -EINVAL;
356 + if (tuple->TupleData[1] != ETH_ALEN)
357 + return -EINVAL;
358 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
359 + return 0;
360 +};
361 +
362 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
363 + tuple_t *tuple,
364 + void *priv)
365 +{
366 + struct ssb_init_invariants *iv = priv;
367 struct ssb_sprom *sprom = &iv->sprom;
368 struct ssb_boardinfo *bi = &iv->boardinfo;
369 const char *error_description;
370
371 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
372 + switch (tuple->TupleData[0]) {
373 + case SSB_PCMCIA_CIS_ID:
374 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
375 + (tuple->TupleDataLen != 7),
376 + "id tpl size");
377 + bi->vendor = tuple->TupleData[1] |
378 + ((u16)tuple->TupleData[2] << 8);
379 + break;
380 + case SSB_PCMCIA_CIS_BOARDREV:
381 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
382 + "boardrev tpl size");
383 + sprom->board_rev = tuple->TupleData[1];
384 + break;
385 + case SSB_PCMCIA_CIS_PA:
386 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
387 + (tuple->TupleDataLen != 10),
388 + "pa tpl size");
389 + sprom->pa0b0 = tuple->TupleData[1] |
390 + ((u16)tuple->TupleData[2] << 8);
391 + sprom->pa0b1 = tuple->TupleData[3] |
392 + ((u16)tuple->TupleData[4] << 8);
393 + sprom->pa0b2 = tuple->TupleData[5] |
394 + ((u16)tuple->TupleData[6] << 8);
395 + sprom->itssi_a = tuple->TupleData[7];
396 + sprom->itssi_bg = tuple->TupleData[7];
397 + sprom->maxpwr_a = tuple->TupleData[8];
398 + sprom->maxpwr_bg = tuple->TupleData[8];
399 + break;
400 + case SSB_PCMCIA_CIS_OEMNAME:
401 + /* We ignore this. */
402 + break;
403 + case SSB_PCMCIA_CIS_CCODE:
404 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
405 + "ccode tpl size");
406 + sprom->country_code = tuple->TupleData[1];
407 + break;
408 + case SSB_PCMCIA_CIS_ANTENNA:
409 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
410 + "ant tpl size");
411 + sprom->ant_available_a = tuple->TupleData[1];
412 + sprom->ant_available_bg = tuple->TupleData[1];
413 + break;
414 + case SSB_PCMCIA_CIS_ANTGAIN:
415 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
416 + "antg tpl size");
417 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
418 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
419 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
420 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
421 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
422 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
423 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
424 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
425 + break;
426 + case SSB_PCMCIA_CIS_BFLAGS:
427 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
428 + (tuple->TupleDataLen != 5),
429 + "bfl tpl size");
430 + sprom->boardflags_lo = tuple->TupleData[1] |
431 + ((u16)tuple->TupleData[2] << 8);
432 + break;
433 + case SSB_PCMCIA_CIS_LEDS:
434 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
435 + "leds tpl size");
436 + sprom->gpio0 = tuple->TupleData[1];
437 + sprom->gpio1 = tuple->TupleData[2];
438 + sprom->gpio2 = tuple->TupleData[3];
439 + sprom->gpio3 = tuple->TupleData[4];
440 + break;
441 + }
442 + return -ENOSPC; /* continue with next entry */
443 +
444 +error:
445 + ssb_printk(KERN_ERR PFX
446 + "PCMCIA: Failed to fetch device invariants: %s\n",
447 + error_description);
448 + return -ENODEV;
449 +}
450 +
451 +
452 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
453 + struct ssb_init_invariants *iv)
454 +{
455 + struct ssb_sprom *sprom = &iv->sprom;
456 + int res;
457 +
458 memset(sprom, 0xFF, sizeof(*sprom));
459 sprom->revision = 1;
460 sprom->boardflags_lo = 0;
461 sprom->boardflags_hi = 0;
462
463 /* First fetch the MAC address. */
464 - memset(&tuple, 0, sizeof(tuple));
465 - tuple.DesiredTuple = CISTPL_FUNCE;
466 - tuple.TupleData = buf;
467 - tuple.TupleDataMax = sizeof(buf);
468 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
469 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
470 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
471 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
472 - while (1) {
473 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
474 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
475 - break;
476 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
477 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
478 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
479 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
480 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
481 + ssb_pcmcia_get_mac, sprom);
482 + if (res != 0) {
483 + ssb_printk(KERN_ERR PFX
484 + "PCMCIA: Failed to fetch MAC address\n");
485 + return -ENODEV;
486 }
487 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
488 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
489
490 /* Fetch the vendor specific tuples. */
491 - memset(&tuple, 0, sizeof(tuple));
492 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
493 - tuple.TupleData = buf;
494 - tuple.TupleDataMax = sizeof(buf);
495 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
496 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
497 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
498 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
499 - while (1) {
500 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
501 - switch (tuple.TupleData[0]) {
502 - case SSB_PCMCIA_CIS_ID:
503 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
504 - (tuple.TupleDataLen != 7),
505 - "id tpl size");
506 - bi->vendor = tuple.TupleData[1] |
507 - ((u16)tuple.TupleData[2] << 8);
508 - break;
509 - case SSB_PCMCIA_CIS_BOARDREV:
510 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
511 - "boardrev tpl size");
512 - sprom->board_rev = tuple.TupleData[1];
513 - break;
514 - case SSB_PCMCIA_CIS_PA:
515 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
516 - (tuple.TupleDataLen != 10),
517 - "pa tpl size");
518 - sprom->pa0b0 = tuple.TupleData[1] |
519 - ((u16)tuple.TupleData[2] << 8);
520 - sprom->pa0b1 = tuple.TupleData[3] |
521 - ((u16)tuple.TupleData[4] << 8);
522 - sprom->pa0b2 = tuple.TupleData[5] |
523 - ((u16)tuple.TupleData[6] << 8);
524 - sprom->itssi_a = tuple.TupleData[7];
525 - sprom->itssi_bg = tuple.TupleData[7];
526 - sprom->maxpwr_a = tuple.TupleData[8];
527 - sprom->maxpwr_bg = tuple.TupleData[8];
528 - break;
529 - case SSB_PCMCIA_CIS_OEMNAME:
530 - /* We ignore this. */
531 - break;
532 - case SSB_PCMCIA_CIS_CCODE:
533 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
534 - "ccode tpl size");
535 - sprom->country_code = tuple.TupleData[1];
536 - break;
537 - case SSB_PCMCIA_CIS_ANTENNA:
538 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
539 - "ant tpl size");
540 - sprom->ant_available_a = tuple.TupleData[1];
541 - sprom->ant_available_bg = tuple.TupleData[1];
542 - break;
543 - case SSB_PCMCIA_CIS_ANTGAIN:
544 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
545 - "antg tpl size");
546 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
547 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
548 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
549 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
550 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
551 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
552 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
553 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
554 - break;
555 - case SSB_PCMCIA_CIS_BFLAGS:
556 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
557 - (tuple.TupleDataLen != 5),
558 - "bfl tpl size");
559 - sprom->boardflags_lo = tuple.TupleData[1] |
560 - ((u16)tuple.TupleData[2] << 8);
561 - break;
562 - case SSB_PCMCIA_CIS_LEDS:
563 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
564 - "leds tpl size");
565 - sprom->gpio0 = tuple.TupleData[1];
566 - sprom->gpio1 = tuple.TupleData[2];
567 - sprom->gpio2 = tuple.TupleData[3];
568 - sprom->gpio3 = tuple.TupleData[4];
569 - break;
570 - }
571 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
572 - if (res == -ENOSPC)
573 - break;
574 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
575 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
576 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
577 - }
578 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
579 + ssb_pcmcia_do_get_invariants, sprom);
580 + if ((res == 0) || (res == -ENOSPC))
581 + return 0;
582
583 - return 0;
584 -error:
585 ssb_printk(KERN_ERR PFX
586 - "PCMCIA: Failed to fetch device invariants: %s\n",
587 - error_description);
588 + "PCMCIA: Failed to fetch device invariants\n");
589 return -ENODEV;
590 }
591
592 --- a/drivers/ssb/scan.c
593 +++ b/drivers/ssb/scan.c
594 @@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
595 dev->bus = bus;
596 dev->ops = bus->ops;
597
598 - ssb_dprintk(KERN_INFO PFX
599 + printk(KERN_DEBUG PFX
600 "Core %d found: %s "
601 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
602 i, ssb_core_name(dev->id.coreid),
603 --- a/drivers/ssb/sprom.c
604 +++ b/drivers/ssb/sprom.c
605 @@ -14,6 +14,7 @@
606 #include "ssb_private.h"
607
608 #include <linux/ctype.h>
609 +#include <linux/slab.h>
610
611
612 static const struct ssb_sprom *fallback_sprom;
613 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
614 u16 *sprom;
615 int res = 0, err = -ENOMEM;
616 size_t sprom_size_words = bus->sprom_size;
617 + struct ssb_freeze_context freeze;
618
619 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
620 if (!sprom)
621 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
622 err = -ERESTARTSYS;
623 if (mutex_lock_interruptible(&bus->sprom_mutex))
624 goto out_kfree;
625 - err = ssb_devices_freeze(bus);
626 - if (err == -EOPNOTSUPP) {
627 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
628 - "No suspend support. Is CONFIG_PM enabled?\n");
629 - goto out_unlock;
630 - }
631 + err = ssb_devices_freeze(bus, &freeze);
632 if (err) {
633 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
634 goto out_unlock;
635 }
636 res = sprom_write(bus, sprom);
637 - err = ssb_devices_thaw(bus);
638 + err = ssb_devices_thaw(&freeze);
639 if (err)
640 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
641 out_unlock:
642 --- a/drivers/ssb/ssb_private.h
643 +++ b/drivers/ssb/ssb_private.h
644 @@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
645
646 /* core.c */
647 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
648 -extern int ssb_devices_freeze(struct ssb_bus *bus);
649 -extern int ssb_devices_thaw(struct ssb_bus *bus);
650 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
651 int ssb_for_each_bus_call(unsigned long data,
652 int (*func)(struct ssb_bus *bus, unsigned long data));
653 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
654
655 +struct ssb_freeze_context {
656 + /* Pointer to the bus */
657 + struct ssb_bus *bus;
658 + /* Boolean list to indicate whether a device is frozen on this bus. */
659 + bool device_frozen[SSB_MAX_NR_CORES];
660 +};
661 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
662 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
663 +
664 +
665
666 /* b43_pci_bridge.c */
667 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
668 extern int __init b43_pci_ssb_bridge_init(void);
669 extern void __exit b43_pci_ssb_bridge_exit(void);
670 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
671 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
672 static inline int b43_pci_ssb_bridge_init(void)
673 {
674 return 0;
675 @@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
676 static inline void b43_pci_ssb_bridge_exit(void)
677 {
678 }
679 -#endif /* CONFIG_SSB_PCIHOST */
680 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
681
682 #endif /* LINUX_SSB_PRIVATE_H_ */
683 --- a/include/linux/ssb/ssb.h
684 +++ b/include/linux/ssb/ssb.h
685 @@ -269,7 +269,8 @@ struct ssb_bus {
686
687 const struct ssb_bus_ops *ops;
688
689 - /* The core in the basic address register window. (PCI bus only) */
690 + /* The core currently mapped into the MMIO window.
691 + * Not valid on all host-buses. So don't use outside of SSB. */
692 struct ssb_device *mapped_device;
693 union {
694 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
695 @@ -281,14 +282,17 @@ struct ssb_bus {
696 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
697 spinlock_t bar_lock;
698
699 - /* The bus this backplane is running on. */
700 + /* The host-bus this backplane is running on. */
701 enum ssb_bustype bustype;
702 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
703 - struct pci_dev *host_pci;
704 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
705 - struct pcmcia_device *host_pcmcia;
706 - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
707 - struct sdio_func *host_sdio;
708 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
709 + union {
710 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
711 + struct pci_dev *host_pci;
712 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
713 + struct pcmcia_device *host_pcmcia;
714 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
715 + struct sdio_func *host_sdio;
716 + };
717
718 /* See enum ssb_quirks */
719 unsigned int quirks;
720 --- a/include/linux/ssb/ssb_regs.h
721 +++ b/include/linux/ssb/ssb_regs.h
722 @@ -198,63 +198,63 @@
723 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
724 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
725 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
726 -#define SSB_SPROM1_PA0B0 0x105E
727 -#define SSB_SPROM1_PA0B1 0x1060
728 -#define SSB_SPROM1_PA0B2 0x1062
729 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
730 +#define SSB_SPROM1_PA0B0 0x005E
731 +#define SSB_SPROM1_PA0B1 0x0060
732 +#define SSB_SPROM1_PA0B2 0x0062
733 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
734 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
735 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
736 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
737 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
738 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
739 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
740 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
741 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
742 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
743 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
744 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
745 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
746 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
747 -#define SSB_SPROM1_PA1B0 0x106A
748 -#define SSB_SPROM1_PA1B1 0x106C
749 -#define SSB_SPROM1_PA1B2 0x106E
750 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
751 +#define SSB_SPROM1_PA1B0 0x006A
752 +#define SSB_SPROM1_PA1B1 0x006C
753 +#define SSB_SPROM1_PA1B2 0x006E
754 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
755 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
756 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
757 #define SSB_SPROM1_ITSSI_A_SHIFT 8
758 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
759 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
760 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
761 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
762 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
763 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
764 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
765 #define SSB_SPROM1_AGAIN_A_SHIFT 8
766
767 /* SPROM Revision 2 (inherits from rev 1) */
768 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
769 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
770 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
771 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
772 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
773 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
774 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
775 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
776 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
777 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
778 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
779 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
780 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
781 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
782 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
783 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
784 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
785 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
786 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
787 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
788 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
789 #define SSB_SPROM2_OPO_VALUE 0x00FF
790 #define SSB_SPROM2_OPO_UNUSED 0xFF00
791 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
792 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
793
794 /* SPROM Revision 3 (inherits most data from rev 2) */
795 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
796 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
797 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
798 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
799 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
800 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
801 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
802 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
803 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
804 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
805 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
806 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
807 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
808 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
809 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
810 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
811 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
812 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
813 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
814 @@ -265,100 +265,100 @@
815 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
816
817 /* SPROM Revision 4 */
818 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
819 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
820 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
821 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
822 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
823 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
824 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
825 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
826 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
827 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
828 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
829 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
830 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
831 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
832 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
833 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
834 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
835 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
836 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
837 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
838 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
839 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
840 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
841 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
842 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
843 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
844 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
845 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
846 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
847 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
848 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
849 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
850 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
851 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
852 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
853 #define SSB_SPROM4_AGAIN0_SHIFT 0
854 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
855 #define SSB_SPROM4_AGAIN1_SHIFT 8
856 -#define SSB_SPROM4_AGAIN23 0x1060
857 +#define SSB_SPROM4_AGAIN23 0x0060
858 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
859 #define SSB_SPROM4_AGAIN2_SHIFT 0
860 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
861 #define SSB_SPROM4_AGAIN3_SHIFT 8
862 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
863 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
864 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
865 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
866 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
867 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
868 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
869 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
870 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
871 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
872 #define SSB_SPROM4_ITSSI_A_SHIFT 8
873 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
874 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
875 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
876 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
877 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
878 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
879 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
880 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
881 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
882 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
883 -#define SSB_SPROM4_PA0B2 0x1086
884 -#define SSB_SPROM4_PA1B0 0x108E
885 -#define SSB_SPROM4_PA1B1 0x1090
886 -#define SSB_SPROM4_PA1B2 0x1092
887 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
888 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
889 +#define SSB_SPROM4_PA0B2 0x0086
890 +#define SSB_SPROM4_PA1B0 0x008E
891 +#define SSB_SPROM4_PA1B1 0x0090
892 +#define SSB_SPROM4_PA1B2 0x0092
893
894 /* SPROM Revision 5 (inherits most data from rev 4) */
895 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
896 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
897 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
898 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
899 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
900 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
901 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
902 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
903 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
904 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
905 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
906 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
907 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
908 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
909 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
910 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
911 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
912 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
913
914 /* SPROM Revision 8 */
915 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
916 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
917 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
918 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
919 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
920 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
921 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
922 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
923 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
924 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
925 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
926 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
927 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
928 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
929 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
930 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
931 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
932 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
933 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
934 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
935 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
936 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
937 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
938 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
939 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
940 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
941 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
942 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
943 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
944 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
945 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
946 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
947 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
948 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
949 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
950 #define SSB_SPROM8_AGAIN0_SHIFT 0
951 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
952 #define SSB_SPROM8_AGAIN1_SHIFT 8
953 -#define SSB_SPROM8_AGAIN23 0x10A0
954 +#define SSB_SPROM8_AGAIN23 0x00A0
955 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
956 #define SSB_SPROM8_AGAIN2_SHIFT 0
957 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
958 #define SSB_SPROM8_AGAIN3_SHIFT 8
959 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
960 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
961 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
962 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
963 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
964 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
965 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
966 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
967 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
968 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
969 #define SSB_SPROM8_RSSISMF2G 0x000F
970 #define SSB_SPROM8_RSSISMC2G 0x00F0
971 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
972 @@ -366,7 +366,7 @@
973 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
974 #define SSB_SPROM8_BXA2G 0x1800
975 #define SSB_SPROM8_BXA2G_SHIFT 11
976 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
977 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
978 #define SSB_SPROM8_RSSISMF5G 0x000F
979 #define SSB_SPROM8_RSSISMC5G 0x00F0
980 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
981 @@ -374,47 +374,47 @@
982 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
983 #define SSB_SPROM8_BXA5G 0x1800
984 #define SSB_SPROM8_BXA5G_SHIFT 11
985 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
986 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
987 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
988 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
989 #define SSB_SPROM8_TRI5G_SHIFT 8
990 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
991 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
992 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
993 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
994 #define SSB_SPROM8_TRI5GH_SHIFT 8
995 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
996 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
997 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
998 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
999 #define SSB_SPROM8_RXPO5G_SHIFT 8
1000 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1001 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1002 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1003 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1004 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1005 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1006 -#define SSB_SPROM8_PA0B1 0x10C4
1007 -#define SSB_SPROM8_PA0B2 0x10C6
1008 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1009 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1010 +#define SSB_SPROM8_PA0B1 0x00C4
1011 +#define SSB_SPROM8_PA0B2 0x00C6
1012 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1013 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1014 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1015 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1016 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1017 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1018 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1019 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1020 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1021 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1022 -#define SSB_SPROM8_PA1B1 0x10CE
1023 -#define SSB_SPROM8_PA1B2 0x10D0
1024 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1025 -#define SSB_SPROM8_PA1LOB1 0x10D4
1026 -#define SSB_SPROM8_PA1LOB2 0x10D6
1027 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1028 -#define SSB_SPROM8_PA1HIB1 0x10DA
1029 -#define SSB_SPROM8_PA1HIB2 0x10DC
1030 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1031 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1032 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1033 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1034 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1035 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1036 +#define SSB_SPROM8_PA1B1 0x00CE
1037 +#define SSB_SPROM8_PA1B2 0x00D0
1038 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1039 +#define SSB_SPROM8_PA1LOB1 0x00D4
1040 +#define SSB_SPROM8_PA1LOB2 0x00D6
1041 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1042 +#define SSB_SPROM8_PA1HIB1 0x00DA
1043 +#define SSB_SPROM8_PA1HIB2 0x00DC
1044 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1045 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1046 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1047 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1048 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1049
1050 /* Values for SSB_SPROM1_BINF_CCODE */
1051 enum {
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