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[ar71xx] tune rtl8366s default config, make vlan 1 cpu port tagged and use eth0.1...
[openwrt.git] / target / linux / xburst / patches-2.6.34 / 056-udc.patch
1 From 644d56ba485f220b1b740b320760a12b5e4e0308 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH] Add jz4740 udc driver
5
6 ---
7 drivers/usb/gadget/Kconfig | 14 +
8 drivers/usb/gadget/Makefile | 1 +
9 drivers/usb/gadget/gadget_chips.h | 9 +
10 drivers/usb/gadget/jz4740_udc.c | 2437 +++++++++++++++++++++++++++++++++++++
11 drivers/usb/gadget/jz4740_udc.h | 100 ++
12 5 files changed, 2561 insertions(+), 0 deletions(-)
13 create mode 100644 drivers/usb/gadget/jz4740_udc.c
14 create mode 100644 drivers/usb/gadget/jz4740_udc.h
15
16 diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
17 index 11a3e0f..a33d0c8 100644
18 --- a/drivers/usb/gadget/Kconfig
19 +++ b/drivers/usb/gadget/Kconfig
20 @@ -121,11 +121,25 @@ choice
21 #
22 # Integrated controllers
23 #
24 +config USB_GADGET_JZ4740
25 + boolean "JZ4740 UDC"
26 + depends on SOC_JZ4740
27 + select USB_GADGET_SELECTED
28 + select USB_GADGET_DUALSPEED
29 + help
30 + Select this to support the Ingenic JZ4740 processor
31 + high speed USB device controller.
32 +
33 +config USB_JZ4740
34 + tristate
35 + depends on USB_GADGET_JZ4740
36 + default USB_GADGET
37
38 config USB_GADGET_AT91
39 boolean "Atmel AT91 USB Device Port"
40 depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
41 select USB_GADGET_SELECTED
42 +
43 help
44 Many Atmel AT91 processors (such as the AT91RM2000) have a
45 full speed USB Device Port with support for five configurable
46 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
47 index 43b51da..8c6ee6b 100644
48 --- a/drivers/usb/gadget/Makefile
49 +++ b/drivers/usb/gadget/Makefile
50 @@ -28,6 +28,7 @@ obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
51 obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
52 obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
53 obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
54 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
55
56 #
57 # USB gadget drivers
58 diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
59 index e511fec..b2ec5fb 100644
60 --- a/drivers/usb/gadget/gadget_chips.h
61 +++ b/drivers/usb/gadget/gadget_chips.h
62 @@ -15,6 +15,12 @@
63 #ifndef __GADGET_CHIPS_H
64 #define __GADGET_CHIPS_H
65
66 +#ifdef CONFIG_USB_GADGET_JZ4740
67 +#define gadget_is_jz4740(g) !strcmp("ingenic_hsusb", (g)->name)
68 +#else
69 +#define gadget_is_jz4740(g) 0
70 +#endif
71 +
72 #ifdef CONFIG_USB_GADGET_NET2280
73 #define gadget_is_net2280(g) !strcmp("net2280", (g)->name)
74 #else
75 @@ -200,6 +206,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
76 return 0x25;
77 else if (gadget_is_s3c_hsotg(gadget))
78 return 0x26;
79 + else if (gadget_is_jz4740(gadget))
80 + return 0x27;
81 +
82 return -ENOENT;
83 }
84
85 diff --git a/drivers/usb/gadget/jz4740_udc.c b/drivers/usb/gadget/jz4740_udc.c
86 new file mode 100644
87 index 0000000..e84c817
88 --- /dev/null
89 +++ b/drivers/usb/gadget/jz4740_udc.c
90 @@ -0,0 +1,2437 @@
91 +/*
92 + * linux/drivers/usb/gadget/jz4740_udc.c
93 + *
94 + * Ingenic JZ4740 on-chip high speed USB device controller
95 + *
96 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
97 + * Author: <jlwei@ingenic.cn>
98 + *
99 + * This program is free software; you can redistribute it and/or modify
100 + * it under the terms of the GNU General Public License as published by
101 + * the Free Software Foundation; either version 2 of the License, or
102 + * (at your option) any later version.
103 + */
104 +
105 +/*
106 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
107 + *
108 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
109 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
110 + */
111 +
112 +#include <linux/kernel.h>
113 +#include <linux/module.h>
114 +#include <linux/platform_device.h>
115 +#include <linux/delay.h>
116 +#include <linux/ioport.h>
117 +#include <linux/slab.h>
118 +#include <linux/errno.h>
119 +#include <linux/init.h>
120 +#include <linux/list.h>
121 +#include <linux/interrupt.h>
122 +#include <linux/proc_fs.h>
123 +#include <linux/usb.h>
124 +#include <linux/usb/gadget.h>
125 +#include <linux/clk.h>
126 +
127 +#include <asm/byteorder.h>
128 +#include <asm/io.h>
129 +#include <asm/irq.h>
130 +#include <asm/system.h>
131 +#include <asm/mach-jz4740/clock.h>
132 +
133 +#include "jz4740_udc.h"
134 +
135 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
136 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
137 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
138 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
139 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
140 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
141 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
142 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
143 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
144 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
145 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
146 +
147 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
148 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
149 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
150 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
151 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
152 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
153 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
154 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
155 +
156 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
157 +
158 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
159 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
160 +
161 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
162 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
163 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
164 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
165 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
166 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
167 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
168 +
169 +/* Power register bit masks */
170 +#define USB_POWER_SUSPENDM 0x01
171 +#define USB_POWER_RESUME 0x04
172 +#define USB_POWER_HSMODE 0x10
173 +#define USB_POWER_HSENAB 0x20
174 +#define USB_POWER_SOFTCONN 0x40
175 +
176 +/* Interrupt register bit masks */
177 +#define USB_INTR_SUSPEND 0x01
178 +#define USB_INTR_RESUME 0x02
179 +#define USB_INTR_RESET 0x04
180 +
181 +#define USB_INTR_EP0 0x0001
182 +#define USB_INTR_INEP1 0x0002
183 +#define USB_INTR_INEP2 0x0004
184 +#define USB_INTR_OUTEP1 0x0002
185 +
186 +/* CSR0 bit masks */
187 +#define USB_CSR0_OUTPKTRDY 0x01
188 +#define USB_CSR0_INPKTRDY 0x02
189 +#define USB_CSR0_SENTSTALL 0x04
190 +#define USB_CSR0_DATAEND 0x08
191 +#define USB_CSR0_SETUPEND 0x10
192 +#define USB_CSR0_SENDSTALL 0x20
193 +#define USB_CSR0_SVDOUTPKTRDY 0x40
194 +#define USB_CSR0_SVDSETUPEND 0x80
195 +
196 +/* Endpoint CSR register bits */
197 +#define USB_INCSRH_AUTOSET 0x80
198 +#define USB_INCSRH_ISO 0x40
199 +#define USB_INCSRH_MODE 0x20
200 +#define USB_INCSRH_DMAREQENAB 0x10
201 +#define USB_INCSRH_DMAREQMODE 0x04
202 +#define USB_INCSR_CDT 0x40
203 +#define USB_INCSR_SENTSTALL 0x20
204 +#define USB_INCSR_SENDSTALL 0x10
205 +#define USB_INCSR_FF 0x08
206 +#define USB_INCSR_UNDERRUN 0x04
207 +#define USB_INCSR_FFNOTEMPT 0x02
208 +#define USB_INCSR_INPKTRDY 0x01
209 +#define USB_OUTCSRH_AUTOCLR 0x80
210 +#define USB_OUTCSRH_ISO 0x40
211 +#define USB_OUTCSRH_DMAREQENAB 0x20
212 +#define USB_OUTCSRH_DNYT 0x10
213 +#define USB_OUTCSRH_DMAREQMODE 0x08
214 +#define USB_OUTCSR_CDT 0x80
215 +#define USB_OUTCSR_SENTSTALL 0x40
216 +#define USB_OUTCSR_SENDSTALL 0x20
217 +#define USB_OUTCSR_FF 0x10
218 +#define USB_OUTCSR_DATAERR 0x08
219 +#define USB_OUTCSR_OVERRUN 0x04
220 +#define USB_OUTCSR_FFFULL 0x02
221 +#define USB_OUTCSR_OUTPKTRDY 0x01
222 +
223 +/* Testmode register bits */
224 +#define USB_TEST_SE0NAK 0x01
225 +#define USB_TEST_J 0x02
226 +#define USB_TEST_K 0x04
227 +#define USB_TEST_PACKET 0x08
228 +
229 +/* DMA control bits */
230 +#define USB_CNTL_ENA 0x01
231 +#define USB_CNTL_DIR_IN 0x02
232 +#define USB_CNTL_MODE_1 0x04
233 +#define USB_CNTL_INTR_EN 0x08
234 +#define USB_CNTL_EP(n) ((n) << 4)
235 +#define USB_CNTL_BURST_0 (0 << 9)
236 +#define USB_CNTL_BURST_4 (1 << 9)
237 +#define USB_CNTL_BURST_8 (2 << 9)
238 +#define USB_CNTL_BURST_16 (3 << 9)
239 +
240 +
241 +#ifndef DEBUG
242 +# define DEBUG(fmt,args...) do {} while(0)
243 +#endif
244 +#ifndef DEBUG_EP0
245 +# define NO_STATES
246 +# define DEBUG_EP0(fmt,args...) do {} while(0)
247 +#endif
248 +#ifndef DEBUG_SETUP
249 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
250 +#endif
251 +
252 +static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */
253 +
254 +module_param(use_dma, int, 0);
255 +MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
256 +
257 +struct jz4740_udc *the_controller;
258 +
259 +/*
260 + * Local declarations.
261 + */
262 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
263 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
264 +
265 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
266 + int status);
267 +static void pio_irq_enable(struct jz4740_ep *ep);
268 +static void pio_irq_disable(struct jz4740_ep *ep);
269 +static void stop_activity(struct jz4740_udc *dev,
270 + struct usb_gadget_driver *driver);
271 +static void nuke(struct jz4740_ep *ep, int status);
272 +static void flush(struct jz4740_ep *ep);
273 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
274 +
275 +/*-------------------------------------------------------------------------*/
276 +
277 +/* inline functions of register read/write/set/clear */
278 +
279 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
280 +{
281 + return readb(udc->base + reg);
282 +}
283 +
284 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
285 +{
286 + return readw(udc->base + reg);
287 +}
288 +
289 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
290 +{
291 + return readl(udc->base + reg);
292 +}
293 +
294 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
295 +{
296 + writeb(val, udc->base + reg);
297 +}
298 +
299 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
300 +{
301 + writew(val, udc->base + reg);
302 +}
303 +
304 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
305 +{
306 + writel(val, udc->base + reg);
307 +}
308 +
309 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
310 +{
311 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
312 +}
313 +
314 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
315 +{
316 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
317 +}
318 +
319 +static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
320 +{
321 + usb_writel(udc, reg, usb_readl(udc, reg) | mask);
322 +}
323 +
324 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
325 +{
326 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
327 +}
328 +
329 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
330 +{
331 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
332 +}
333 +
334 +static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
335 +{
336 + usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
337 +}
338 +
339 +/*-------------------------------------------------------------------------*/
340 +
341 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
342 +{
343 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
344 +}
345 +
346 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
347 +{
348 + jz_udc_set_index(ep->dev, ep_index(ep));
349 +}
350 +
351 +static inline int write_packet(struct jz4740_ep *ep,
352 + struct jz4740_request *req, int max)
353 +{
354 + uint8_t *buf;
355 + int length, nlong, nbyte;
356 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
357 +
358 + buf = req->req.buf + req->req.actual;
359 + prefetch(buf);
360 +
361 + length = req->req.length - req->req.actual;
362 + length = min(length, max);
363 + req->req.actual += length;
364 +
365 + DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
366 +
367 + nlong = length >> 2;
368 + nbyte = length & 0x3;
369 + while (nlong--) {
370 + usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
371 + buf += 4;
372 + }
373 + while (nbyte--) {
374 + usb_writeb(ep->dev, ep->fifo, *buf++);
375 + }
376 +
377 + return length;
378 +}
379 +
380 +static inline int read_packet(struct jz4740_ep *ep,
381 + struct jz4740_request *req, int count)
382 +{
383 + uint8_t *buf;
384 + int length, nlong, nbyte;
385 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
386 +
387 + buf = req->req.buf + req->req.actual;
388 + prefetchw(buf);
389 +
390 + length = req->req.length - req->req.actual;
391 + length = min(length, count);
392 + req->req.actual += length;
393 +
394 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
395 +
396 + nlong = length >> 2;
397 + nbyte = length & 0x3;
398 + while (nlong--) {
399 + *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
400 + buf += 4;
401 + }
402 + while (nbyte--) {
403 + *buf++ = usb_readb(ep->dev, ep->fifo);
404 + }
405 +
406 + return length;
407 +}
408 +
409 +/*-------------------------------------------------------------------------*/
410 +
411 +/*
412 + * udc_disable - disable USB device controller
413 + */
414 +static void udc_disable(struct jz4740_udc *dev)
415 +{
416 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
417 +
418 + udc_set_address(dev, 0);
419 +
420 + /* Disable interrupts */
421 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
422 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
423 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
424 +
425 + /* Disable DMA */
426 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
427 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
428 +
429 + /* Disconnect from usb */
430 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
431 +
432 + /* Disable the USB PHY */
433 + clk_disable(dev->clk);
434 +
435 + dev->ep0state = WAIT_FOR_SETUP;
436 + dev->gadget.speed = USB_SPEED_UNKNOWN;
437 +
438 + return;
439 +}
440 +
441 +/*
442 + * udc_reinit - initialize software state
443 + */
444 +static void udc_reinit(struct jz4740_udc *dev)
445 +{
446 + int i;
447 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
448 +
449 + /* device/ep0 records init */
450 + INIT_LIST_HEAD(&dev->gadget.ep_list);
451 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
452 + dev->ep0state = WAIT_FOR_SETUP;
453 +
454 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
455 + struct jz4740_ep *ep = &dev->ep[i];
456 +
457 + if (i != 0)
458 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
459 +
460 + INIT_LIST_HEAD(&ep->queue);
461 + ep->desc = 0;
462 + ep->stopped = 0;
463 + ep->pio_irqs = 0;
464 + }
465 +}
466 +
467 +/* until it's enabled, this UDC should be completely invisible
468 + * to any USB host.
469 + */
470 +static void udc_enable(struct jz4740_udc *dev)
471 +{
472 + int i;
473 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
474 +
475 + /* UDC state is incorrect - Added by River */
476 + if (dev->state != UDC_STATE_ENABLE) {
477 + return;
478 + }
479 +
480 + dev->gadget.speed = USB_SPEED_UNKNOWN;
481 +
482 + /* Flush FIFO for each */
483 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
484 + struct jz4740_ep *ep = &dev->ep[i];
485 +
486 + jz_udc_set_index(dev, ep_index(ep));
487 + flush(ep);
488 + }
489 +
490 + /* Set this bit to allow the UDC entering low-power mode when
491 + * there are no actions on the USB bus.
492 + * UDC still works during this bit was set.
493 + */
494 + jz4740_clock_udc_enable_auto_suspend();
495 +
496 + /* Enable the USB PHY */
497 + clk_enable(dev->clk);
498 +
499 + /* Disable interrupts */
500 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
501 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
502 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
503 +
504 + /* Enable interrupts */
505 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
506 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
507 + /* Don't enable rest of the interrupts */
508 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
509 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
510 +
511 + /* Enable SUSPEND */
512 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
513 +
514 + /* Enable HS Mode */
515 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
516 +
517 + /* Let host detect UDC:
518 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
519 + * transistor on and pull the USBDP pin HIGH.
520 + */
521 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
522 +
523 + return;
524 +}
525 +
526 +/*-------------------------------------------------------------------------*/
527 +
528 +/* keeping it simple:
529 + * - one bus driver, initted first;
530 + * - one function driver, initted second
531 + */
532 +
533 +/*
534 + * Register entry point for the peripheral controller driver.
535 + */
536 +
537 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
538 +{
539 + struct jz4740_udc *dev = the_controller;
540 + int retval;
541 +
542 + if (!driver || !driver->bind) {
543 + return -EINVAL;
544 + }
545 +
546 + if (!dev) {
547 + return -ENODEV;
548 + }
549 +
550 + if (dev->driver) {
551 + return -EBUSY;
552 + }
553 +
554 + /* hook up the driver */
555 + dev->driver = driver;
556 + dev->gadget.dev.driver = &driver->driver;
557 +
558 + retval = driver->bind(&dev->gadget);
559 + if (retval) {
560 + DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
561 + driver->driver.name, retval);
562 + dev->driver = 0;
563 + return retval;
564 + }
565 +
566 + /* then enable host detection and ep0; and we're ready
567 + * for set_configuration as well as eventual disconnect.
568 + */
569 + udc_enable(dev);
570 +
571 + DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
572 + driver->driver.name);
573 +
574 + return 0;
575 +}
576 +
577 +EXPORT_SYMBOL(usb_gadget_register_driver);
578 +
579 +static void stop_activity(struct jz4740_udc *dev,
580 + struct usb_gadget_driver *driver)
581 +{
582 + int i;
583 +
584 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
585 +
586 + /* don't disconnect drivers more than once */
587 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
588 + driver = 0;
589 + dev->gadget.speed = USB_SPEED_UNKNOWN;
590 +
591 + /* prevent new request submissions, kill any outstanding requests */
592 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
593 + struct jz4740_ep *ep = &dev->ep[i];
594 +
595 + ep->stopped = 1;
596 +
597 + jz_udc_set_index(dev, ep_index(ep));
598 + nuke(ep, -ESHUTDOWN);
599 + }
600 +
601 + /* report disconnect; the driver is already quiesced */
602 + if (driver) {
603 + spin_unlock(&dev->lock);
604 + driver->disconnect(&dev->gadget);
605 + spin_lock(&dev->lock);
606 + }
607 +
608 + /* re-init driver-visible data structures */
609 + udc_reinit(dev);
610 +}
611 +
612 +
613 +/*
614 + * Unregister entry point for the peripheral controller driver.
615 + */
616 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
617 +{
618 + struct jz4740_udc *dev = the_controller;
619 + unsigned long flags;
620 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
621 +
622 + if (!dev)
623 + return -ENODEV;
624 + if (!driver || driver != dev->driver)
625 + return -EINVAL;
626 + if (!driver->unbind)
627 + return -EBUSY;
628 +
629 + spin_lock_irqsave(&dev->lock, flags);
630 + dev->driver = 0;
631 + stop_activity(dev, driver);
632 + spin_unlock_irqrestore(&dev->lock, flags);
633 +
634 + driver->unbind(&dev->gadget);
635 +
636 + udc_disable(dev);
637 +
638 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
639 +
640 + return 0;
641 +}
642 +
643 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
644 +
645 +/*-------------------------------------------------------------------------*/
646 +
647 +/*
648 + * Starting DMA using mode 1
649 + */
650 +static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
651 +{
652 + struct jz4740_udc *dev = ep->dev;
653 + uint32_t count = req->req.length;
654 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
655 +
656 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
657 +
658 + jz_udc_select_ep(ep);
659 +
660 + if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
661 + ep->reg_addr = JZ_REG_UDC_ADDR1;
662 +
663 + dma_cache_wback_inv((unsigned long)req->req.buf, count);
664 +
665 + pio_irq_enable(ep);
666 +
667 + usb_writeb(dev, JZ_REG_UDC_INCSRH,
668 + USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
669 +
670 + usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
671 + usb_writel(dev, JZ_REG_UDC_COUNT1, count);
672 + usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
673 + USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
674 + }
675 + else { /* Bulk-OUT transfer using DMA channel 2 */
676 + ep->reg_addr = JZ_REG_UDC_ADDR2;
677 +
678 + dma_cache_wback_inv((unsigned long)req->req.buf, count);
679 +
680 + pio_irq_enable(ep);
681 +
682 + usb_setb(dev, JZ_REG_UDC_OUTCSRH,
683 + USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
684 +
685 + usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
686 + usb_writel(dev, JZ_REG_UDC_COUNT2, count);
687 + usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
688 + USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
689 + }
690 +}
691 +
692 +/*-------------------------------------------------------------------------*/
693 +
694 +/** Write request to FIFO (max write == maxp size)
695 + * Return: 0 = still running, 1 = completed, negative = errno
696 + * NOTE: INDEX register must be set for EP
697 + */
698 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
699 +{
700 + struct jz4740_udc *dev = ep->dev;
701 + uint32_t max, csr;
702 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
703 +
704 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
705 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
706 +
707 + if (use_dma) {
708 + uint32_t dma_count;
709 +
710 + /* DMA interrupt generated due to the last packet loaded into the FIFO */
711 +
712 + dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
713 + req->req.actual += dma_count;
714 +
715 + if (dma_count % max) {
716 + /* If the last packet is less than MAXP, set INPKTRDY manually */
717 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
718 + }
719 +
720 + done(ep, req, 0);
721 + if (list_empty(&ep->queue)) {
722 + pio_irq_disable(ep);
723 + return 1;
724 + }
725 + else {
726 + /* advance the request queue */
727 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
728 + kick_dma(ep, req);
729 + return 0;
730 + }
731 + }
732 +
733 + /*
734 + * PIO mode handling starts here ...
735 + */
736 +
737 + csr = usb_readb(dev, ep->csr);
738 +
739 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
740 + unsigned count;
741 + int is_last, is_short;
742 +
743 + count = write_packet(ep, req, max);
744 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
745 +
746 + /* last packet is usually short (or a zlp) */
747 + if (unlikely(count != max))
748 + is_last = is_short = 1;
749 + else {
750 + if (likely(req->req.length != req->req.actual)
751 + || req->req.zero)
752 + is_last = 0;
753 + else
754 + is_last = 1;
755 + /* interrupt/iso maxpacket may not fill the fifo */
756 + is_short = unlikely(max < ep_maxpacket(ep));
757 + }
758 +
759 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
760 + ep->ep.name, count,
761 + is_last ? "/L" : "", is_short ? "/S" : "",
762 + req->req.length - req->req.actual, req);
763 +
764 + /* requests complete when all IN data is in the FIFO */
765 + if (is_last) {
766 + done(ep, req, 0);
767 + if (list_empty(&ep->queue)) {
768 + pio_irq_disable(ep);
769 + }
770 + return 1;
771 + }
772 + } else {
773 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
774 + }
775 +
776 + return 0;
777 +}
778 +
779 +/** Read to request from FIFO (max read == bytes in fifo)
780 + * Return: 0 = still running, 1 = completed, negative = errno
781 + * NOTE: INDEX register must be set for EP
782 + */
783 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
784 +{
785 + struct jz4740_udc *dev = ep->dev;
786 + uint32_t csr;
787 + unsigned count, is_short;
788 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
789 +
790 + if (use_dma) {
791 + uint32_t dma_count;
792 +
793 + /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
794 +
795 + dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
796 + req->req.actual += dma_count;
797 +
798 + /* Disable interrupt and DMA */
799 + pio_irq_disable(ep);
800 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
801 +
802 + /* Read all bytes from this packet */
803 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
804 + count = read_packet(ep, req, count);
805 +
806 + if (count) {
807 + /* If the last packet is greater than zero, clear OUTPKTRDY manually */
808 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
809 + }
810 + done(ep, req, 0);
811 +
812 + if (!list_empty(&ep->queue)) {
813 + /* advance the request queue */
814 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
815 + kick_dma(ep, req);
816 + }
817 +
818 + return 1;
819 + }
820 +
821 + /*
822 + * PIO mode handling starts here ...
823 + */
824 +
825 + /* make sure there's a packet in the FIFO. */
826 + csr = usb_readb(dev, ep->csr);
827 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
828 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
829 + return -EINVAL;
830 + }
831 +
832 + /* read all bytes from this packet */
833 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
834 +
835 + is_short = (count < ep->ep.maxpacket);
836 +
837 + count = read_packet(ep, req, count);
838 +
839 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
840 + ep->ep.name, csr, count,
841 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
842 +
843 + /* Clear OutPktRdy */
844 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
845 +
846 + /* completion */
847 + if (is_short || req->req.actual == req->req.length) {
848 + done(ep, req, 0);
849 +
850 + if (list_empty(&ep->queue))
851 + pio_irq_disable(ep);
852 + return 1;
853 + }
854 +
855 + /* finished that packet. the next one may be waiting... */
856 + return 0;
857 +}
858 +
859 +/*
860 + * done - retire a request; caller blocked irqs
861 + * INDEX register is preserved to keep same
862 + */
863 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
864 +{
865 + unsigned int stopped = ep->stopped;
866 + uint32_t index;
867 +
868 + DEBUG("%s, %p\n", __FUNCTION__, ep);
869 + list_del_init(&req->queue);
870 +
871 + if (likely(req->req.status == -EINPROGRESS))
872 + req->req.status = status;
873 + else
874 + status = req->req.status;
875 +
876 + if (status && status != -ESHUTDOWN)
877 + DEBUG("complete %s req %p stat %d len %u/%u\n",
878 + ep->ep.name, &req->req, status,
879 + req->req.actual, req->req.length);
880 +
881 + /* don't modify queue heads during completion callback */
882 + ep->stopped = 1;
883 + /* Read current index (completion may modify it) */
884 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
885 + spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
886 +
887 + req->req.complete(&ep->ep, &req->req);
888 +
889 + spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
890 + /* Restore index */
891 + jz_udc_set_index(ep->dev, index);
892 + ep->stopped = stopped;
893 +}
894 +
895 +/** Enable EP interrupt */
896 +static void pio_irq_enable(struct jz4740_ep *ep)
897 +{
898 + uint8_t index = ep_index(ep);
899 + struct jz4740_udc *dev = ep->dev;
900 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
901 +
902 + if (ep_is_in(ep)) {
903 + switch (index) {
904 + case 1:
905 + case 2:
906 + usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
907 + dev->in_mask |= BIT(index);
908 + break;
909 + default:
910 + DEBUG("Unknown endpoint: %d\n", index);
911 + break;
912 + }
913 + }
914 + else {
915 + switch (index) {
916 + case 1:
917 + usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
918 + dev->out_mask |= BIT(index);
919 + break;
920 + default:
921 + DEBUG("Unknown endpoint: %d\n", index);
922 + break;
923 + }
924 + }
925 +}
926 +
927 +/** Disable EP interrupt */
928 +static void pio_irq_disable(struct jz4740_ep *ep)
929 +{
930 + uint8_t index = ep_index(ep);
931 + struct jz4740_udc *dev = ep->dev;
932 +
933 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
934 +
935 + if (ep_is_in(ep)) {
936 + switch (ep_index(ep)) {
937 + case 1:
938 + case 2:
939 + usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
940 + dev->in_mask &= ~BIT(index);
941 + break;
942 + default:
943 + DEBUG("Unknown endpoint: %d\n", index);
944 + break;
945 + }
946 + }
947 + else {
948 + switch (ep_index(ep)) {
949 + case 1:
950 + usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
951 + dev->out_mask &= ~BIT(index);
952 + break;
953 + default:
954 + DEBUG("Unknown endpoint: %d\n", index);
955 + break;
956 + }
957 + }
958 +}
959 +
960 +/*
961 + * nuke - dequeue ALL requests
962 + */
963 +static void nuke(struct jz4740_ep *ep, int status)
964 +{
965 + struct jz4740_request *req;
966 +
967 + DEBUG("%s, %p\n", __FUNCTION__, ep);
968 +
969 + /* Flush FIFO */
970 + flush(ep);
971 +
972 + /* called with irqs blocked */
973 + while (!list_empty(&ep->queue)) {
974 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
975 + done(ep, req, status);
976 + }
977 +
978 + /* Disable IRQ if EP is enabled (has descriptor) */
979 + if (ep->desc)
980 + pio_irq_disable(ep);
981 +}
982 +
983 +/** Flush EP FIFO
984 + * NOTE: INDEX register must be set before this call
985 + */
986 +static void flush(struct jz4740_ep *ep)
987 +{
988 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
989 +
990 + switch (ep->type) {
991 + case ep_bulk_in:
992 + case ep_interrupt:
993 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
994 + break;
995 + case ep_bulk_out:
996 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
997 + break;
998 + case ep_control:
999 + break;
1000 + }
1001 +}
1002 +
1003 +/**
1004 + * jz4740_in_epn - handle IN interrupt
1005 + */
1006 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
1007 +{
1008 + uint32_t csr;
1009 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
1010 + struct jz4740_request *req;
1011 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1012 +
1013 + jz_udc_set_index(dev, ep_index(ep));
1014 +
1015 + csr = usb_readb(dev, ep->csr);
1016 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
1017 +
1018 + if (csr & USB_INCSR_SENTSTALL) {
1019 + DEBUG("USB_INCSR_SENTSTALL\n");
1020 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
1021 + return;
1022 + }
1023 +
1024 + if (!ep->desc) {
1025 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
1026 + return;
1027 + }
1028 +
1029 + if (list_empty(&ep->queue))
1030 + req = 0;
1031 + else
1032 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1033 +
1034 + DEBUG("req: %p\n", req);
1035 +
1036 + if (!req)
1037 + return;
1038 +
1039 + write_fifo(ep, req);
1040 +}
1041 +
1042 +/*
1043 + * Bulk OUT (recv)
1044 + */
1045 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
1046 +{
1047 + struct jz4740_ep *ep = &dev->ep[ep_idx];
1048 + struct jz4740_request *req;
1049 +
1050 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
1051 +
1052 + jz_udc_set_index(dev, ep_index(ep));
1053 + if (ep->desc) {
1054 + uint32_t csr;
1055 +
1056 + if (use_dma) {
1057 + /* DMA starts here ... */
1058 + if (list_empty(&ep->queue))
1059 + req = 0;
1060 + else
1061 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1062 +
1063 + if (req)
1064 + read_fifo(ep, req);
1065 + return;
1066 + }
1067 +
1068 + /*
1069 + * PIO mode starts here ...
1070 + */
1071 +
1072 + while ((csr = usb_readb(dev, ep->csr)) &
1073 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
1074 + DEBUG("%s: %x\n", __FUNCTION__, csr);
1075 +
1076 + if (csr & USB_OUTCSR_SENTSTALL) {
1077 + DEBUG("%s: stall sent, flush fifo\n",
1078 + __FUNCTION__);
1079 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
1080 + flush(ep);
1081 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
1082 + if (list_empty(&ep->queue))
1083 + req = 0;
1084 + else
1085 + req =
1086 + list_entry(ep->queue.next,
1087 + struct jz4740_request,
1088 + queue);
1089 +
1090 + if (!req) {
1091 + DEBUG("%s: NULL REQ %d\n",
1092 + __FUNCTION__, ep_idx);
1093 + break;
1094 + } else {
1095 + read_fifo(ep, req);
1096 + }
1097 + }
1098 + }
1099 + } else {
1100 + /* Throw packet away.. */
1101 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1102 + flush(ep);
1103 + }
1104 +}
1105 +
1106 +/** Halt specific EP
1107 + * Return 0 if success
1108 + * NOTE: Sets INDEX register to EP !
1109 + */
1110 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
1111 +{
1112 + struct jz4740_udc *dev;
1113 + struct jz4740_ep *ep;
1114 + unsigned long flags;
1115 +
1116 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1117 +
1118 + ep = container_of(_ep, struct jz4740_ep, ep);
1119 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1120 + DEBUG("%s, bad ep\n", __FUNCTION__);
1121 + return -EINVAL;
1122 + }
1123 +
1124 + dev = ep->dev;
1125 +
1126 + spin_lock_irqsave(&dev->lock, flags);
1127 +
1128 + jz_udc_select_ep(ep);
1129 +
1130 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1131 +
1132 + if (ep_index(ep) == 0) {
1133 + /* EP0 */
1134 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1135 + } else if (ep_is_in(ep)) {
1136 + uint32_t csr = usb_readb(dev, ep->csr);
1137 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
1138 + || !list_empty(&ep->queue))) {
1139 + /*
1140 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1141 + * if any transfer requests are still queued, or if the controller
1142 + * FIFO still holds bytes that the host hasn\92t collected.
1143 + */
1144 + spin_unlock_irqrestore(&dev->lock, flags);
1145 + DEBUG
1146 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1147 + (csr & USB_INCSR_FFNOTEMPT),
1148 + !list_empty(&ep->queue));
1149 + return -EAGAIN;
1150 + }
1151 + flush(ep);
1152 + if (value) {
1153 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1154 + }
1155 + else {
1156 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1157 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
1158 + }
1159 + } else {
1160 +
1161 + flush(ep);
1162 + if (value) {
1163 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1164 + }
1165 + else {
1166 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1167 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1168 + }
1169 + }
1170 +
1171 + if (value) {
1172 + ep->stopped = 1;
1173 + } else {
1174 + ep->stopped = 0;
1175 + }
1176 +
1177 + spin_unlock_irqrestore(&dev->lock, flags);
1178 +
1179 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1180 +
1181 + return 0;
1182 +}
1183 +
1184 +
1185 +static int jz4740_ep_enable(struct usb_ep *_ep,
1186 + const struct usb_endpoint_descriptor *desc)
1187 +{
1188 + struct jz4740_ep *ep;
1189 + struct jz4740_udc *dev;
1190 + unsigned long flags;
1191 + uint32_t max, csrh = 0;
1192 +
1193 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1194 +
1195 + if (!_ep || !desc)
1196 + return -EINVAL;
1197 +
1198 + ep = container_of(_ep, struct jz4740_ep, ep);
1199 + if (ep->desc || ep->type == ep_control
1200 + || desc->bDescriptorType != USB_DT_ENDPOINT
1201 + || ep->bEndpointAddress != desc->bEndpointAddress) {
1202 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1203 + return -EINVAL;
1204 + }
1205 +
1206 + /* xfer types must match, except that interrupt ~= bulk */
1207 + if (ep->bmAttributes != desc->bmAttributes
1208 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1209 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1210 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1211 + return -EINVAL;
1212 + }
1213 +
1214 + dev = ep->dev;
1215 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1216 + DEBUG("%s, bogus device state\n", __FUNCTION__);
1217 + return -ESHUTDOWN;
1218 + }
1219 +
1220 + max = le16_to_cpu(desc->wMaxPacketSize);
1221 +
1222 + spin_lock_irqsave(&ep->dev->lock, flags);
1223 +
1224 + /* Configure the endpoint */
1225 + jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1226 + if (ep_is_in(ep)) {
1227 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1228 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1229 + case USB_ENDPOINT_XFER_BULK:
1230 + case USB_ENDPOINT_XFER_INT:
1231 + csrh &= ~USB_INCSRH_ISO;
1232 + break;
1233 + case USB_ENDPOINT_XFER_ISOC:
1234 + csrh |= USB_INCSRH_ISO;
1235 + break;
1236 + }
1237 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1238 + }
1239 + else {
1240 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1241 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1242 + case USB_ENDPOINT_XFER_BULK:
1243 + csrh &= ~USB_OUTCSRH_ISO;
1244 + break;
1245 + case USB_ENDPOINT_XFER_INT:
1246 + csrh &= ~USB_OUTCSRH_ISO;
1247 + csrh |= USB_OUTCSRH_DNYT;
1248 + break;
1249 + case USB_ENDPOINT_XFER_ISOC:
1250 + csrh |= USB_OUTCSRH_ISO;
1251 + break;
1252 + }
1253 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1254 + }
1255 +
1256 +
1257 + ep->stopped = 0;
1258 + ep->desc = desc;
1259 + ep->pio_irqs = 0;
1260 + ep->ep.maxpacket = max;
1261 +
1262 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1263 +
1264 + /* Reset halt state (does flush) */
1265 + jz4740_set_halt(_ep, 0);
1266 +
1267 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1268 +
1269 + return 0;
1270 +}
1271 +
1272 +/** Disable EP
1273 + * NOTE: Sets INDEX register
1274 + */
1275 +static int jz4740_ep_disable(struct usb_ep *_ep)
1276 +{
1277 + struct jz4740_ep *ep;
1278 + unsigned long flags;
1279 +
1280 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1281 +
1282 + ep = container_of(_ep, struct jz4740_ep, ep);
1283 + if (!_ep || !ep->desc) {
1284 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1285 + _ep ? ep->ep.name : NULL);
1286 + return -EINVAL;
1287 + }
1288 +
1289 + spin_lock_irqsave(&ep->dev->lock, flags);
1290 +
1291 + jz_udc_select_ep(ep);
1292 +
1293 + /* Nuke all pending requests (does flush) */
1294 + nuke(ep, -ESHUTDOWN);
1295 +
1296 + /* Disable ep IRQ */
1297 + pio_irq_disable(ep);
1298 +
1299 + ep->desc = 0;
1300 + ep->stopped = 1;
1301 +
1302 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1303 +
1304 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1305 + return 0;
1306 +}
1307 +
1308 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1309 +{
1310 + struct jz4740_request *req;
1311 +
1312 + DEBUG("%s, %p\n", __FUNCTION__, ep);
1313 +
1314 + req = kzalloc(sizeof(*req), gfp_flags);
1315 + if (!req)
1316 + return 0;
1317 +
1318 + INIT_LIST_HEAD(&req->queue);
1319 +
1320 + return &req->req;
1321 +}
1322 +
1323 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1324 +{
1325 + struct jz4740_request *req;
1326 +
1327 + DEBUG("%s, %p\n", __FUNCTION__, ep);
1328 +
1329 + req = container_of(_req, struct jz4740_request, req);
1330 + WARN_ON(!list_empty(&req->queue));
1331 + kfree(req);
1332 +}
1333 +
1334 +/*--------------------------------------------------------------------*/
1335 +
1336 +/** Queue one request
1337 + * Kickstart transfer if needed
1338 + * NOTE: Sets INDEX register
1339 + */
1340 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1341 + gfp_t gfp_flags)
1342 +{
1343 + struct jz4740_request *req;
1344 + struct jz4740_ep *ep;
1345 + struct jz4740_udc *dev;
1346 +
1347 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1348 +
1349 + req = container_of(_req, struct jz4740_request, req);
1350 + if (unlikely
1351 + (!_req || !_req->complete || !_req->buf
1352 + || !list_empty(&req->queue))) {
1353 + DEBUG("%s, bad params\n", __FUNCTION__);
1354 + return -EINVAL;
1355 + }
1356 +
1357 + ep = container_of(_ep, struct jz4740_ep, ep);
1358 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1359 + DEBUG("%s, bad ep\n", __FUNCTION__);
1360 + return -EINVAL;
1361 + }
1362 +
1363 + dev = ep->dev;
1364 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1365 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1366 + return -ESHUTDOWN;
1367 + }
1368 +
1369 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1370 + _req->buf);
1371 +
1372 + spin_lock_irqsave(&dev->lock, dev->lock_flags);
1373 +
1374 + _req->status = -EINPROGRESS;
1375 + _req->actual = 0;
1376 +
1377 + /* kickstart this i/o queue? */
1378 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1379 + ep->stopped);
1380 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1381 + uint32_t csr;
1382 +
1383 + if (unlikely(ep_index(ep) == 0)) {
1384 + /* EP0 */
1385 + list_add_tail(&req->queue, &ep->queue);
1386 + jz4740_ep0_kick(dev, ep);
1387 + req = 0;
1388 + } else if (use_dma) {
1389 + /* DMA */
1390 + kick_dma(ep, req);
1391 + }
1392 + /* PIO */
1393 + else if (ep_is_in(ep)) {
1394 + /* EP1 & EP2 */
1395 + jz_udc_set_index(dev, ep_index(ep));
1396 + csr = usb_readb(dev, ep->csr);
1397 + pio_irq_enable(ep);
1398 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1399 + if (write_fifo(ep, req) == 1)
1400 + req = 0;
1401 + }
1402 + } else {
1403 + /* EP1 */
1404 + jz_udc_set_index(dev, ep_index(ep));
1405 + csr = usb_readb(dev, ep->csr);
1406 + pio_irq_enable(ep);
1407 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1408 + if (read_fifo(ep, req) == 1)
1409 + req = 0;
1410 + }
1411 + }
1412 + }
1413 +
1414 + /* pio or dma irq handler advances the queue. */
1415 + if (likely(req != 0))
1416 + list_add_tail(&req->queue, &ep->queue);
1417 +
1418 + spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1419 +
1420 + return 0;
1421 +}
1422 +
1423 +/* dequeue JUST ONE request */
1424 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1425 +{
1426 + struct jz4740_ep *ep;
1427 + struct jz4740_request *req;
1428 + unsigned long flags;
1429 +
1430 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1431 +
1432 + ep = container_of(_ep, struct jz4740_ep, ep);
1433 + if (!_ep || ep->type == ep_control)
1434 + return -EINVAL;
1435 +
1436 + spin_lock_irqsave(&ep->dev->lock, flags);
1437 +
1438 + /* make sure it's actually queued on this endpoint */
1439 + list_for_each_entry(req, &ep->queue, queue) {
1440 + if (&req->req == _req)
1441 + break;
1442 + }
1443 + if (&req->req != _req) {
1444 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1445 + return -EINVAL;
1446 + }
1447 + done(ep, req, -ECONNRESET);
1448 +
1449 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1450 + return 0;
1451 +}
1452 +
1453 +/** Return bytes in EP FIFO
1454 + * NOTE: Sets INDEX register to EP
1455 + */
1456 +static int jz4740_fifo_status(struct usb_ep *_ep)
1457 +{
1458 + uint32_t csr;
1459 + int count = 0;
1460 + struct jz4740_ep *ep;
1461 + unsigned long flags;
1462 +
1463 + ep = container_of(_ep, struct jz4740_ep, ep);
1464 + if (!_ep) {
1465 + DEBUG("%s, bad ep\n", __FUNCTION__);
1466 + return -ENODEV;
1467 + }
1468 +
1469 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1470 +
1471 + /* LPD can't report unclaimed bytes from IN fifos */
1472 + if (ep_is_in(ep))
1473 + return -EOPNOTSUPP;
1474 +
1475 + spin_lock_irqsave(&ep->dev->lock, flags);
1476 + jz_udc_set_index(ep->dev, ep_index(ep));
1477 +
1478 + csr = usb_readb(ep->dev, ep->csr);
1479 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1480 + csr & 0x1) {
1481 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1482 + }
1483 +
1484 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1485 +
1486 + return count;
1487 +}
1488 +
1489 +/** Flush EP FIFO
1490 + * NOTE: Sets INDEX register to EP
1491 + */
1492 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1493 +{
1494 + struct jz4740_ep *ep;
1495 + unsigned long flags;
1496 +
1497 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1498 +
1499 + ep = container_of(_ep, struct jz4740_ep, ep);
1500 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1501 + DEBUG("%s, bad ep\n", __FUNCTION__);
1502 + return;
1503 + }
1504 +
1505 + spin_lock_irqsave(&ep->dev->lock, flags);
1506 +
1507 + jz_udc_set_index(ep->dev, ep_index(ep));
1508 + flush(ep);
1509 +
1510 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1511 +}
1512 +
1513 +/****************************************************************/
1514 +/* End Point 0 related functions */
1515 +/****************************************************************/
1516 +
1517 +/* return: 0 = still running, 1 = completed, negative = errno */
1518 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1519 +{
1520 + uint32_t max;
1521 + unsigned count;
1522 + int is_last;
1523 +
1524 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1525 + max = ep_maxpacket(ep);
1526 +
1527 + count = write_packet(ep, req, max);
1528 +
1529 + /* last packet is usually short (or a zlp) */
1530 + if (unlikely(count != max))
1531 + is_last = 1;
1532 + else {
1533 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1534 + is_last = 0;
1535 + else
1536 + is_last = 1;
1537 + }
1538 +
1539 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1540 + ep->ep.name, count,
1541 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1542 +
1543 + /* requests complete when all IN data is in the FIFO */
1544 + if (is_last) {
1545 + done(ep, req, 0);
1546 + return 1;
1547 + }
1548 +
1549 + return 0;
1550 +}
1551 +
1552 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1553 + unsigned char *cp, int max)
1554 +{
1555 + int bytes;
1556 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1557 +
1558 + if (count > max)
1559 + count = max;
1560 + bytes = count;
1561 + while (count--)
1562 + *cp++ = usb_readb(ep->dev, ep->fifo);
1563 +
1564 + return bytes;
1565 +}
1566 +
1567 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1568 + unsigned char *cp, int count)
1569 +{
1570 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1571 + while (count--)
1572 + usb_writeb(ep->dev, ep->fifo, *cp++);
1573 +}
1574 +
1575 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1576 +{
1577 + struct jz4740_udc *dev = ep->dev;
1578 + uint32_t csr;
1579 + uint8_t *buf;
1580 + unsigned bufferspace, count, is_short;
1581 +
1582 + DEBUG_EP0("%s\n", __FUNCTION__);
1583 +
1584 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1585 + if (!(csr & USB_CSR0_OUTPKTRDY))
1586 + return 0;
1587 +
1588 + buf = req->req.buf + req->req.actual;
1589 + prefetchw(buf);
1590 + bufferspace = req->req.length - req->req.actual;
1591 +
1592 + /* read all bytes from this packet */
1593 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1594 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1595 + req->req.actual += min(count, bufferspace);
1596 + } else /* zlp */
1597 + count = 0;
1598 +
1599 + is_short = (count < ep->ep.maxpacket);
1600 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1601 + ep->ep.name, csr, count,
1602 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1603 +
1604 + while (likely(count-- != 0)) {
1605 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1606 +
1607 + if (unlikely(bufferspace == 0)) {
1608 + /* this happens when the driver's buffer
1609 + * is smaller than what the host sent.
1610 + * discard the extra data.
1611 + */
1612 + if (req->req.status != -EOVERFLOW)
1613 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1614 + count);
1615 + req->req.status = -EOVERFLOW;
1616 + } else {
1617 + *buf++ = byte;
1618 + bufferspace--;
1619 + }
1620 + }
1621 +
1622 + /* completion */
1623 + if (is_short || req->req.actual == req->req.length) {
1624 + done(ep, req, 0);
1625 + return 1;
1626 + }
1627 +
1628 + /* finished that packet. the next one may be waiting... */
1629 + return 0;
1630 +}
1631 +
1632 +/**
1633 + * udc_set_address - set the USB address for this device
1634 + * @address:
1635 + *
1636 + * Called from control endpoint function after it decodes a set address setup packet.
1637 + */
1638 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1639 +{
1640 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1641 +
1642 + dev->usb_address = address;
1643 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1644 +}
1645 +
1646 +/*
1647 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1648 + * - if error
1649 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1650 + * - else
1651 + * set USB_CSR0_SVDOUTPKTRDY bit
1652 + if last set USB_CSR0_DATAEND bit
1653 + */
1654 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1655 +{
1656 + struct jz4740_request *req;
1657 + struct jz4740_ep *ep = &dev->ep[0];
1658 + int ret;
1659 +
1660 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1661 +
1662 + if (list_empty(&ep->queue))
1663 + req = 0;
1664 + else
1665 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1666 +
1667 + if (req) {
1668 + if (req->req.length == 0) {
1669 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1670 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1671 + dev->ep0state = WAIT_FOR_SETUP;
1672 + return;
1673 + } else if (kickstart) {
1674 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1675 + return;
1676 + }
1677 + ret = read_fifo_ep0(ep, req);
1678 + if (ret) {
1679 + /* Done! */
1680 + DEBUG_EP0("%s: finished, waiting for status\n",
1681 + __FUNCTION__);
1682 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1683 + dev->ep0state = WAIT_FOR_SETUP;
1684 + } else {
1685 + /* Not done yet.. */
1686 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1687 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1688 + }
1689 + } else {
1690 + DEBUG_EP0("NO REQ??!\n");
1691 + }
1692 +}
1693 +
1694 +/*
1695 + * DATA_STATE_XMIT
1696 + */
1697 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1698 +{
1699 + struct jz4740_request *req;
1700 + struct jz4740_ep *ep = &dev->ep[0];
1701 + int ret, need_zlp = 0;
1702 +
1703 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1704 +
1705 + if (list_empty(&ep->queue))
1706 + req = 0;
1707 + else
1708 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1709 +
1710 + if (!req) {
1711 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1712 + return 0;
1713 + }
1714 +
1715 + if (req->req.length == 0) {
1716 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1717 + dev->ep0state = WAIT_FOR_SETUP;
1718 + return 1;
1719 + }
1720 +
1721 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1722 + /* Next write will end with the packet size, */
1723 + /* so we need zero-length-packet */
1724 + need_zlp = 1;
1725 + }
1726 +
1727 + ret = write_fifo_ep0(ep, req);
1728 +
1729 + if (ret == 1 && !need_zlp) {
1730 + /* Last packet */
1731 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1732 +
1733 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1734 + dev->ep0state = WAIT_FOR_SETUP;
1735 + } else {
1736 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1737 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1738 + }
1739 +
1740 + if (need_zlp) {
1741 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1742 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1743 + dev->ep0state = DATA_STATE_NEED_ZLP;
1744 + }
1745 +
1746 + return 1;
1747 +}
1748 +
1749 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1750 + struct usb_ctrlrequest *ctrl)
1751 +{
1752 + struct jz4740_ep *ep0 = &dev->ep[0];
1753 + struct jz4740_ep *qep;
1754 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1755 + uint16_t val = 0;
1756 +
1757 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1758 +
1759 + if (reqtype == USB_RECIP_INTERFACE) {
1760 + /* This is not supported.
1761 + * And according to the USB spec, this one does nothing..
1762 + * Just return 0
1763 + */
1764 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1765 + } else if (reqtype == USB_RECIP_DEVICE) {
1766 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1767 + val |= (1 << 0); /* Self powered */
1768 + /*val |= (1<<1); *//* Remote wakeup */
1769 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1770 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1771 +
1772 + DEBUG_SETUP
1773 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1774 + ep_num, ctrl->wLength);
1775 +
1776 + if (ctrl->wLength > 2 || ep_num > 3)
1777 + return -EOPNOTSUPP;
1778 +
1779 + qep = &dev->ep[ep_num];
1780 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1781 + && ep_index(qep) != 0) {
1782 + return -EOPNOTSUPP;
1783 + }
1784 +
1785 + jz_udc_set_index(dev, ep_index(qep));
1786 +
1787 + /* Return status on next IN token */
1788 + switch (qep->type) {
1789 + case ep_control:
1790 + val =
1791 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1792 + USB_CSR0_SENDSTALL;
1793 + break;
1794 + case ep_bulk_in:
1795 + case ep_interrupt:
1796 + val =
1797 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1798 + USB_INCSR_SENDSTALL;
1799 + break;
1800 + case ep_bulk_out:
1801 + val =
1802 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1803 + USB_OUTCSR_SENDSTALL;
1804 + break;
1805 + }
1806 +
1807 + /* Back to EP0 index */
1808 + jz_udc_set_index(dev, 0);
1809 +
1810 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1811 + ctrl->wIndex, val);
1812 + } else {
1813 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1814 + return -EOPNOTSUPP;
1815 + }
1816 +
1817 + /* Clear "out packet ready" */
1818 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1819 + /* Put status to FIFO */
1820 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1821 + /* Issue "In packet ready" */
1822 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1823 +
1824 + return 0;
1825 +}
1826 +
1827 +/*
1828 + * WAIT_FOR_SETUP (OUTPKTRDY)
1829 + * - read data packet from EP0 FIFO
1830 + * - decode command
1831 + * - if error
1832 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1833 + * - else
1834 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1835 + */
1836 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1837 +{
1838 + struct jz4740_ep *ep = &dev->ep[0];
1839 + struct usb_ctrlrequest ctrl;
1840 + int i;
1841 +
1842 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1843 +
1844 + /* Nuke all previous transfers */
1845 + nuke(ep, -EPROTO);
1846 +
1847 + /* read control req from fifo (8 bytes) */
1848 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1849 +
1850 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1851 + ctrl.bRequestType, ctrl.bRequest,
1852 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1853 +
1854 + /* Set direction of EP0 */
1855 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1856 + ep->bEndpointAddress |= USB_DIR_IN;
1857 + } else {
1858 + ep->bEndpointAddress &= ~USB_DIR_IN;
1859 + }
1860 +
1861 + /* Handle some SETUP packets ourselves */
1862 + switch (ctrl.bRequest) {
1863 + case USB_REQ_SET_ADDRESS:
1864 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1865 + break;
1866 +
1867 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1868 + udc_set_address(dev, ctrl.wValue);
1869 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1870 + return;
1871 +
1872 + case USB_REQ_SET_CONFIGURATION:
1873 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1874 + break;
1875 +
1876 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1877 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1878 +
1879 + /* Enable RESUME and SUSPEND interrupts */
1880 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1881 + break;
1882 +
1883 + case USB_REQ_SET_INTERFACE:
1884 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1885 + break;
1886 +
1887 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1888 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1889 + break;
1890 +
1891 + case USB_REQ_GET_STATUS:
1892 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1893 + return;
1894 +
1895 + case USB_REQ_CLEAR_FEATURE:
1896 + case USB_REQ_SET_FEATURE:
1897 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1898 + struct jz4740_ep *qep;
1899 + int ep_num = (ctrl.wIndex & 0x0f);
1900 +
1901 + /* Support only HALT feature */
1902 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1903 + || ep_num > 3 || ep_num < 1)
1904 + break;
1905 +
1906 + qep = &dev->ep[ep_num];
1907 + spin_unlock(&dev->lock);
1908 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1909 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1910 + ep_num);
1911 + jz4740_set_halt(&qep->ep, 1);
1912 + } else {
1913 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1914 + ep_num);
1915 + jz4740_set_halt(&qep->ep, 0);
1916 + }
1917 + spin_lock(&dev->lock);
1918 +
1919 + jz_udc_set_index(dev, 0);
1920 +
1921 + /* Reply with a ZLP on next IN token */
1922 + usb_setb(dev, JZ_REG_UDC_CSR0,
1923 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1924 + return;
1925 + }
1926 + break;
1927 +
1928 + default:
1929 + break;
1930 + }
1931 +
1932 + /* gadget drivers see class/vendor specific requests,
1933 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1934 + * and more.
1935 + */
1936 + if (dev->driver) {
1937 + /* device-2-host (IN) or no data setup command, process immediately */
1938 + spin_unlock(&dev->lock);
1939 +
1940 + i = dev->driver->setup(&dev->gadget, &ctrl);
1941 + spin_lock(&dev->lock);
1942 +
1943 + if (unlikely(i < 0)) {
1944 + /* setup processing failed, force stall */
1945 + DEBUG_SETUP
1946 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1947 + i);
1948 + jz_udc_set_index(dev, 0);
1949 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1950 +
1951 + /* ep->stopped = 1; */
1952 + dev->ep0state = WAIT_FOR_SETUP;
1953 + }
1954 + else {
1955 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1956 +/* if (!ctrl.wLength) {
1957 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1958 + }*/
1959 + }
1960 + }
1961 +}
1962 +
1963 +/*
1964 + * DATA_STATE_NEED_ZLP
1965 + */
1966 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1967 +{
1968 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1969 +
1970 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1971 + dev->ep0state = WAIT_FOR_SETUP;
1972 +}
1973 +
1974 +/*
1975 + * handle ep0 interrupt
1976 + */
1977 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1978 +{
1979 + struct jz4740_ep *ep = &dev->ep[0];
1980 + uint32_t csr;
1981 +
1982 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1983 + /* Set index 0 */
1984 + jz_udc_set_index(dev, 0);
1985 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1986 +
1987 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1988 +
1989 + /*
1990 + * if SENT_STALL is set
1991 + * - clear the SENT_STALL bit
1992 + */
1993 + if (csr & USB_CSR0_SENTSTALL) {
1994 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1995 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1996 + nuke(ep, -ECONNABORTED);
1997 + dev->ep0state = WAIT_FOR_SETUP;
1998 + return;
1999 + }
2000 +
2001 + /*
2002 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
2003 + * - fill EP0 FIFO
2004 + * - if last packet
2005 + * - set IN_PKT_RDY | DATA_END
2006 + * - else
2007 + * set IN_PKT_RDY
2008 + */
2009 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
2010 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
2011 + __FUNCTION__);
2012 +
2013 + switch (dev->ep0state) {
2014 + case DATA_STATE_XMIT:
2015 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
2016 + jz4740_ep0_in(dev, csr);
2017 + return;
2018 + case DATA_STATE_NEED_ZLP:
2019 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
2020 + jz4740_ep0_in_zlp(dev, csr);
2021 + return;
2022 + default:
2023 + /* Stall? */
2024 +// DEBUG_EP0("Odd state!! state = %s\n",
2025 +// state_names[dev->ep0state]);
2026 + dev->ep0state = WAIT_FOR_SETUP;
2027 + /* nuke(ep, 0); */
2028 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
2029 +// break;
2030 + return;
2031 + }
2032 + }
2033 +
2034 + /*
2035 + * if SETUPEND is set
2036 + * - abort the last transfer
2037 + * - set SERVICED_SETUP_END_BIT
2038 + */
2039 + if (csr & USB_CSR0_SETUPEND) {
2040 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
2041 +
2042 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
2043 + nuke(ep, 0);
2044 + dev->ep0state = WAIT_FOR_SETUP;
2045 + }
2046 +
2047 + /*
2048 + * if USB_CSR0_OUTPKTRDY is set
2049 + * - read data packet from EP0 FIFO
2050 + * - decode command
2051 + * - if error
2052 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
2053 + * - else
2054 + * set SVDOUTPKTRDY | DATAEND bits
2055 + */
2056 + if (csr & USB_CSR0_OUTPKTRDY) {
2057 +
2058 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
2059 + csr);
2060 +
2061 + switch (dev->ep0state) {
2062 + case WAIT_FOR_SETUP:
2063 + DEBUG_EP0("WAIT_FOR_SETUP\n");
2064 + jz4740_ep0_setup(dev, csr);
2065 + break;
2066 +
2067 + case DATA_STATE_RECV:
2068 + DEBUG_EP0("DATA_STATE_RECV\n");
2069 + jz4740_ep0_out(dev, csr, 0);
2070 + break;
2071 +
2072 + default:
2073 + /* send stall? */
2074 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
2075 + dev->ep0state);
2076 + break;
2077 + }
2078 + }
2079 +}
2080 +
2081 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
2082 +{
2083 + uint32_t csr;
2084 +
2085 + jz_udc_set_index(dev, 0);
2086 +
2087 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
2088 +
2089 + /* Clear "out packet ready" */
2090 +
2091 + if (ep_is_in(ep)) {
2092 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2093 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2094 + dev->ep0state = DATA_STATE_XMIT;
2095 + jz4740_ep0_in(dev, csr);
2096 + } else {
2097 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2098 + dev->ep0state = DATA_STATE_RECV;
2099 + jz4740_ep0_out(dev, csr, 1);
2100 + }
2101 +}
2102 +
2103 +/** Handle USB RESET interrupt
2104 + */
2105 +static void jz4740_reset_irq(struct jz4740_udc *dev)
2106 +{
2107 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2108 + USB_SPEED_HIGH : USB_SPEED_FULL;
2109 +
2110 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
2111 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2112 +}
2113 +
2114 +/*
2115 + * jz4740 usb device interrupt handler.
2116 + */
2117 +static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
2118 +{
2119 + struct jz4740_udc *dev = _dev;
2120 + uint8_t index;
2121 +
2122 + uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2123 + uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN);
2124 + uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
2125 + uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
2126 +
2127 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2128 + return IRQ_HANDLED;
2129 +
2130 +
2131 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2132 + intr_out, intr_in, intr_usb);
2133 +
2134 + spin_lock(&dev->lock);
2135 + index = usb_readb(dev, JZ_REG_UDC_INDEX);
2136 +
2137 + /* Check for resume from suspend mode */
2138 + if ((intr_usb & USB_INTR_RESUME) &&
2139 + (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2140 + DEBUG("USB resume\n");
2141 + dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
2142 + }
2143 +
2144 + /* Check for system interrupts */
2145 + if (intr_usb & USB_INTR_RESET) {
2146 + DEBUG("USB reset\n");
2147 + jz4740_reset_irq(dev);
2148 + }
2149 +
2150 + /* Check for endpoint 0 interrupt */
2151 + if (intr_in & USB_INTR_EP0) {
2152 + DEBUG("USB_INTR_EP0 (control)\n");
2153 + jz4740_handle_ep0(dev, intr_in);
2154 + }
2155 +
2156 + /* Check for Bulk-IN DMA interrupt */
2157 + if (intr_dma & 0x1) {
2158 + int ep_num;
2159 + struct jz4740_ep *ep;
2160 + ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2161 + ep = &dev->ep[ep_num + 1];
2162 + jz_udc_set_index(dev, ep_num);
2163 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2164 +/* jz4740_in_epn(dev, ep_num, intr_in);*/
2165 + }
2166 +
2167 + /* Check for Bulk-OUT DMA interrupt */
2168 + if (intr_dma & 0x2) {
2169 + int ep_num;
2170 + ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2171 + jz4740_out_epn(dev, ep_num, intr_out);
2172 + }
2173 +
2174 + /* Check for each configured endpoint interrupt */
2175 + if (intr_in & USB_INTR_INEP1) {
2176 + DEBUG("USB_INTR_INEP1\n");
2177 + jz4740_in_epn(dev, 1, intr_in);
2178 + }
2179 +
2180 + if (intr_in & USB_INTR_INEP2) {
2181 + DEBUG("USB_INTR_INEP2\n");
2182 + jz4740_in_epn(dev, 2, intr_in);
2183 + }
2184 +
2185 + if (intr_out & USB_INTR_OUTEP1) {
2186 + DEBUG("USB_INTR_OUTEP1\n");
2187 + jz4740_out_epn(dev, 1, intr_out);
2188 + }
2189 +
2190 + /* Check for suspend mode */
2191 + if ((intr_usb & USB_INTR_SUSPEND) &&
2192 + (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2193 + DEBUG("USB suspend\n");
2194 + dev->driver->suspend(&dev->gadget);
2195 + /* Host unloaded from us, can do something, such as flushing
2196 + the NAND block cache etc. */
2197 + }
2198 +
2199 + jz_udc_set_index(dev, index);
2200 +
2201 + spin_unlock(&dev->lock);
2202 +
2203 + return IRQ_HANDLED;
2204 +}
2205 +
2206 +
2207 +
2208 +/*-------------------------------------------------------------------------*/
2209 +
2210 +/* Common functions - Added by River */
2211 +static struct jz4740_udc udc_dev;
2212 +
2213 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2214 +{
2215 + return container_of(gadget, struct jz4740_udc, gadget);
2216 +}
2217 +/* End added */
2218 +
2219 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2220 +{
2221 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2222 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2223 +}
2224 +
2225 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2226 +{
2227 + /* host may not have enabled remote wakeup */
2228 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2229 + return -EHOSTUNREACH;
2230 + udc_set_mask_UDCCR(UDCCR_RSM); */
2231 + return -ENOTSUPP;
2232 +}
2233 +
2234 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2235 +{
2236 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
2237 + unsigned long flags;
2238 +
2239 + local_irq_save(flags);
2240 +
2241 + if (on) {
2242 + udc->state = UDC_STATE_ENABLE;
2243 + udc_enable(udc);
2244 + } else {
2245 + udc->state = UDC_STATE_DISABLE;
2246 + udc_disable(udc);
2247 + }
2248 +
2249 + local_irq_restore(flags);
2250 +
2251 + return 0;
2252 +}
2253 +
2254 +
2255 +static const struct usb_gadget_ops jz4740_udc_ops = {
2256 + .get_frame = jz4740_udc_get_frame,
2257 + .wakeup = jz4740_udc_wakeup,
2258 + .pullup = jz4740_udc_pullup,
2259 + /* current versions must always be self-powered */
2260 +};
2261 +
2262 +static struct usb_ep_ops jz4740_ep_ops = {
2263 + .enable = jz4740_ep_enable,
2264 + .disable = jz4740_ep_disable,
2265 +
2266 + .alloc_request = jz4740_alloc_request,
2267 + .free_request = jz4740_free_request,
2268 +
2269 + .queue = jz4740_queue,
2270 + .dequeue = jz4740_dequeue,
2271 +
2272 + .set_halt = jz4740_set_halt,
2273 + .fifo_status = jz4740_fifo_status,
2274 + .fifo_flush = jz4740_fifo_flush,
2275 +};
2276 +
2277 +
2278 +/*-------------------------------------------------------------------------*/
2279 +
2280 +static struct jz4740_udc udc_dev = {
2281 + .usb_address = 0,
2282 + .gadget = {
2283 + .ops = &jz4740_udc_ops,
2284 + .ep0 = &udc_dev.ep[0].ep,
2285 + .name = "jz-udc",
2286 + .dev = {
2287 + .init_name = "gadget",
2288 + },
2289 + },
2290 +
2291 + /* control endpoint */
2292 + .ep[0] = {
2293 + .ep = {
2294 + .name = "ep0",
2295 + .ops = &jz4740_ep_ops,
2296 + .maxpacket = EP0_MAXPACKETSIZE,
2297 + },
2298 + .dev = &udc_dev,
2299 +
2300 + .bEndpointAddress = 0,
2301 + .bmAttributes = 0,
2302 +
2303 + .type = ep_control,
2304 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2305 + .csr = JZ_REG_UDC_CSR0,
2306 + },
2307 +
2308 + /* bulk out endpoint */
2309 + .ep[1] = {
2310 + .ep = {
2311 + .name = "ep1out-bulk",
2312 + .ops = &jz4740_ep_ops,
2313 + .maxpacket = EPBULK_MAXPACKETSIZE,
2314 + },
2315 + .dev = &udc_dev,
2316 +
2317 + .bEndpointAddress = 1,
2318 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2319 +
2320 + .type = ep_bulk_out,
2321 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2322 + .csr = JZ_REG_UDC_OUTCSR,
2323 + },
2324 +
2325 + /* bulk in endpoint */
2326 + .ep[2] = {
2327 + .ep = {
2328 + .name = "ep1in-bulk",
2329 + .ops = &jz4740_ep_ops,
2330 + .maxpacket = EPBULK_MAXPACKETSIZE,
2331 + },
2332 + .dev = &udc_dev,
2333 +
2334 + .bEndpointAddress = 1 | USB_DIR_IN,
2335 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2336 +
2337 + .type = ep_bulk_in,
2338 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2339 + .csr = JZ_REG_UDC_INCSR,
2340 + },
2341 +
2342 + /* interrupt in endpoint */
2343 + .ep[3] = {
2344 + .ep = {
2345 + .name = "ep2in-int",
2346 + .ops = &jz4740_ep_ops,
2347 + .maxpacket = EPINTR_MAXPACKETSIZE,
2348 + },
2349 + .dev = &udc_dev,
2350 +
2351 + .bEndpointAddress = 2 | USB_DIR_IN,
2352 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2353 +
2354 + .type = ep_interrupt,
2355 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2356 + .csr = JZ_REG_UDC_INCSR,
2357 + },
2358 +};
2359 +
2360 +static void gadget_release(struct device *_dev)
2361 +{
2362 +}
2363 +
2364 +
2365 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2366 +{
2367 + struct jz4740_udc *dev = &udc_dev;
2368 + int ret;
2369 +
2370 + spin_lock_init(&dev->lock);
2371 + the_controller = dev;
2372 +
2373 + dev->dev = &pdev->dev;
2374 + dev_set_name(&dev->gadget.dev, "gadget");
2375 + dev->gadget.dev.parent = &pdev->dev;
2376 + dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2377 + dev->gadget.dev.release = gadget_release;
2378 +
2379 + ret = device_register(&dev->gadget.dev);
2380 + if (ret)
2381 + return ret;
2382 +
2383 + dev->clk = clk_get(&pdev->dev, "udc");
2384 + if (IS_ERR(dev->clk)) {
2385 + ret = PTR_ERR(dev->clk);
2386 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2387 + goto err_device_unregister;
2388 + }
2389 +
2390 + platform_set_drvdata(pdev, dev);
2391 +
2392 + dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2393 +
2394 + if (!dev->mem) {
2395 + ret = -ENOENT;
2396 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2397 + goto err_clk_put;
2398 + }
2399 +
2400 + dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2401 +
2402 + if (!dev->mem) {
2403 + ret = -EBUSY;
2404 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2405 + goto err_device_unregister;
2406 + }
2407 +
2408 + dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2409 +
2410 + if (!dev->base) {
2411 + ret = -EBUSY;
2412 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2413 + goto err_release_mem_region;
2414 + }
2415 +
2416 + dev->irq = platform_get_irq(pdev, 0);
2417 +
2418 + ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2419 + pdev->name, dev);
2420 + if (ret) {
2421 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2422 + goto err_iounmap;
2423 + }
2424 +
2425 + udc_disable(dev);
2426 + udc_reinit(dev);
2427 +
2428 + return 0;
2429 +
2430 +err_iounmap:
2431 + iounmap(dev->base);
2432 +err_release_mem_region:
2433 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2434 +err_clk_put:
2435 + clk_put(dev->clk);
2436 +err_device_unregister:
2437 + device_unregister(&dev->gadget.dev);
2438 + platform_set_drvdata(pdev, NULL);
2439 +
2440 + the_controller = 0;
2441 +
2442 + return ret;
2443 +}
2444 +
2445 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2446 +{
2447 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2448 +
2449 + if (dev->driver)
2450 + return -EBUSY;
2451 +
2452 + udc_disable(dev);
2453 +
2454 + free_irq(dev->irq, dev);
2455 + iounmap(dev->base);
2456 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2457 + clk_put(dev->clk);
2458 +
2459 + platform_set_drvdata(pdev, NULL);
2460 + device_unregister(&dev->gadget.dev);
2461 + the_controller = NULL;
2462 +
2463 + return 0;
2464 +}
2465 +
2466 +#ifdef CONFIG_PM
2467 +
2468 +static int jz4740_udc_suspend(struct device *dev)
2469 +{
2470 + struct jz4740_udc *udc = dev_get_drvdata(dev);
2471 +
2472 + if (udc->state == UDC_STATE_ENABLE)
2473 + udc_disable(udc);
2474 +
2475 + return 0;
2476 +}
2477 +
2478 +static int jz4740_udc_resume(struct device *dev)
2479 +{
2480 + struct jz4740_udc *udc = dev_get_drvdata(dev);
2481 +
2482 + if (udc->state == UDC_STATE_ENABLE)
2483 + udc_enable(udc);
2484 +
2485 + return 0;
2486 +}
2487 +
2488 +static struct dev_pm_ops jz4740_udc_pm_ops = {
2489 + .suspend = jz4740_udc_suspend,
2490 + .resume = jz4740_udc_resume,
2491 +};
2492 +
2493 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2494 +
2495 +#else
2496 +
2497 +#define JZ4740_UDC_PM_OPS NULL
2498 +
2499 +#endif
2500 +
2501 +static struct platform_driver udc_driver = {
2502 + .probe = jz4740_udc_probe,
2503 + .remove = __devexit_p(jz4740_udc_remove),
2504 + .driver = {
2505 + .name = "jz-udc",
2506 + .owner = THIS_MODULE,
2507 + .pm = JZ4740_UDC_PM_OPS,
2508 + },
2509 +};
2510 +
2511 +/*-------------------------------------------------------------------------*/
2512 +
2513 +static int __init udc_init (void)
2514 +{
2515 + return platform_driver_register(&udc_driver);
2516 +}
2517 +module_init(udc_init);
2518 +
2519 +static void __exit udc_exit (void)
2520 +{
2521 + platform_driver_unregister(&udc_driver);
2522 +}
2523 +module_exit(udc_exit);
2524 +
2525 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2526 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2527 +MODULE_LICENSE("GPL");
2528 diff --git a/drivers/usb/gadget/jz4740_udc.h b/drivers/usb/gadget/jz4740_udc.h
2529 new file mode 100644
2530 index 0000000..7156768
2531 --- /dev/null
2532 +++ b/drivers/usb/gadget/jz4740_udc.h
2533 @@ -0,0 +1,100 @@
2534 +/*
2535 + * linux/drivers/usb/gadget/jz4740_udc.h
2536 + *
2537 + * Ingenic JZ4740 on-chip high speed USB device controller
2538 + *
2539 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2540 + * Author: <jlwei@ingenic.cn>
2541 + *
2542 + * This program is free software; you can redistribute it and/or modify
2543 + * it under the terms of the GNU General Public License as published by
2544 + * the Free Software Foundation; either version 2 of the License, or
2545 + * (at your option) any later version.
2546 + */
2547 +
2548 +#ifndef __USB_GADGET_JZ4740_H__
2549 +#define __USB_GADGET_JZ4740_H__
2550 +
2551 +/*-------------------------------------------------------------------------*/
2552 +
2553 +// Max packet size
2554 +#define EP0_MAXPACKETSIZE 64
2555 +#define EPBULK_MAXPACKETSIZE 512
2556 +#define EPINTR_MAXPACKETSIZE 64
2557 +
2558 +#define UDC_MAX_ENDPOINTS 4
2559 +
2560 +/*-------------------------------------------------------------------------*/
2561 +
2562 +typedef enum ep_type {
2563 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2564 +} ep_type_t;
2565 +
2566 +struct jz4740_ep {
2567 + struct usb_ep ep;
2568 + struct jz4740_udc *dev;
2569 +
2570 + const struct usb_endpoint_descriptor *desc;
2571 + unsigned long pio_irqs;
2572 +
2573 + uint8_t stopped;
2574 + uint8_t bEndpointAddress;
2575 + uint8_t bmAttributes;
2576 +
2577 + ep_type_t type;
2578 + size_t fifo;
2579 + u32 csr;
2580 +
2581 + uint32_t reg_addr;
2582 + struct list_head queue;
2583 +};
2584 +
2585 +struct jz4740_request {
2586 + struct usb_request req;
2587 + struct list_head queue;
2588 +};
2589 +
2590 +enum ep0state {
2591 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2592 + DATA_STATE_XMIT, /* data tx stage */
2593 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2594 + WAIT_FOR_OUT_STATUS, /* status stages */
2595 + DATA_STATE_RECV, /* data rx stage */
2596 +};
2597 +
2598 +/* For function binding with UDC Disable - Added by River */
2599 +typedef enum {
2600 + UDC_STATE_ENABLE = 0,
2601 + UDC_STATE_DISABLE,
2602 +}udc_state_t;
2603 +
2604 +struct jz4740_udc {
2605 + struct usb_gadget gadget;
2606 + struct usb_gadget_driver *driver;
2607 + struct device *dev;
2608 + spinlock_t lock;
2609 + unsigned long lock_flags;
2610 +
2611 + enum ep0state ep0state;
2612 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2613 +
2614 + unsigned char usb_address;
2615 +
2616 + udc_state_t state;
2617 +
2618 + struct resource *mem;
2619 + void __iomem *base;
2620 + int irq;
2621 + uint32_t in_mask;
2622 + uint32_t out_mask;
2623 +
2624 + struct clk *clk;
2625 +};
2626 +
2627 +extern struct jz4740_udc *the_controller;
2628 +
2629 +#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
2630 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2631 +#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
2632 +
2633 +#endif /* __USB_GADGET_JZ4740_H__ */
2634 --
2635 1.5.6.5
2636
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