target/linux/brcm63xx/files/arch/mips/pci/pci-bcm63xx.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/pci.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <asm/bootinfo.h>
  14
  15 #include "pci-bcm63xx.h"
  16
  17 /* allow PCI to be disabled at runtime depending on board nvram
  18  * configuration */
  19 int bcm63xx_pci_enabled = 0;
  20
  21 static struct resource bcm_pci_mem_resource = {
  22         .name   = "bcm63xx PCI memory space",
  23         .start  = BCM_PCI_MEM_BASE_PA,
  24         .end    = BCM_PCI_MEM_END_PA,
  25         .flags  = IORESOURCE_MEM
  26 };
  27
  28 static struct resource bcm_pci_io_resource = {
  29         .name   = "bcm63xx PCI IO space",
  30         .start  = BCM_PCI_IO_BASE_PA,
  31         .end    = BCM_PCI_IO_END_PA,
  32         .flags  = IORESOURCE_IO
  33 };
  34
  35 struct pci_controller bcm63xx_controller = {
  36         .pci_ops        = &bcm63xx_pci_ops,
  37         .io_resource    = &bcm_pci_io_resource,
  38         .mem_resource   = &bcm_pci_mem_resource,
  39 };
  40
  41 static u32 bcm63xx_int_cfg_readl(u32 reg)
  42 {
  43         u32 tmp;
  44
  45         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
  46         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
  47         bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
  48         iob();
  49         return bcm_mpi_readl(MPI_PCICFGDATA_REG);
  50 }
  51
  52 static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
  53 {
  54         u32 tmp;
  55
  56         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
  57         tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
  58         bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
  59         bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
  60 }
  61
  62 void __iomem *pci_iospace_start;
  63
  64 static int __init bcm63xx_pci_init(void)
  65 {
  66         unsigned int mem_size;
  67         u32 val;
  68
  69         if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
  70                 return -ENODEV;
  71
  72         if (!bcm63xx_pci_enabled)
  73                 return -ENODEV;
  74
  75         /*
  76          * configuration  access are  done through  IO space,  remap 4
  77          * first bytes to access it from CPU.
  78          *
  79          * this means that  no io access from CPU  should happen while
  80          * we do a configuration cycle,  but there's no way we can add
  81          * a spinlock for each io access, so this is currently kind of
  82          * broken on SMP.
  83          */
  84         pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
  85         if (!pci_iospace_start)
  86                 return -ENOMEM;
  87
  88         /* setup local bus to PCI access (PCI memory) */
  89         val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
  90         bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
  91         bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
  92         bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
  93
  94         /* set Cardbus IDSEL (type 0 cfg access on primary bus for
  95          * this IDSEL will be done on Cardbus instead) */
  96         val = bcm_pcmcia_readl(PCMCIA_C1_REG);
  97         val &= ~PCMCIA_C1_CBIDSEL_MASK;
  98         val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
  99         bcm_pcmcia_writel(val, PCMCIA_C1_REG);
 100
 101         /* disable second access windows */
 102         bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
 103
 104         /* setup local bus  to PCI access (IO memory),  we have only 1
 105          * IO window  for both PCI  and cardbus, but it  cannot handle
 106          * both  at the  same time,  assume standard  PCI for  now, if
 107          * cardbus card has  IO zone, PCI fixup will  change window to
 108          * cardbus */
 109         val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
 110         bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
 111         bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
 112         bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
 113
 114         /* enable PCI related GPIO pins */
 115         bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
 116
 117         /* setup PCI to local bus access, used by PCI device to target
 118          * local RAM while bus mastering */
 119         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 120         if (BCMCPU_IS_6358())
 121                 val = MPI_SP0_REMAP_ENABLE_MASK;
 122         else
 123                 val = 0;
 124         bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
 125
 126         bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
 127         bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
 128
 129         mem_size = bcm63xx_get_memory_size();
 130
 131         /* 6348 before rev b0 exposes only 16 MB of RAM memory through
 132          * PCI, throw a warning if we have more memory */
 133         if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
 134                 if (mem_size > (16 * 1024 * 1024))
 135                         printk(KERN_WARNING "bcm63xx: this CPU "
 136                                "revision cannot handle more than 16MB "
 137                                "of RAM for PCI bus mastering\n");
 138         } else {
 139                 /* setup sp0 range to local RAM size */
 140                 bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
 141                 bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
 142         }
 143
 144         /* change  host bridge  retry  counter to  infinite number  of
 145          * retry,  needed for  some broadcom  wifi cards  with Silicon
 146          * Backplane bus where access to srom seems very slow  */
 147         val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
 148         val &= ~REG_TIMER_RETRY_MASK;
 149         bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 150
 151         /* enable memory decoder and bus mastering */
 152         val = bcm63xx_int_cfg_readl(PCI_COMMAND);
 153         val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 154         bcm63xx_int_cfg_writel(val, PCI_COMMAND);
 155
 156         /* enable read prefetching & disable byte swapping for bus
 157          * mastering transfers */
 158         val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
 159         val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 160         val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 161         val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 162         val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 163         bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
 164
 165         /* enable pci interrupt */
 166         val = bcm_mpi_readl(MPI_LOCINT_REG);
 167         val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 168         bcm_mpi_writel(val, MPI_LOCINT_REG);
 169
 170         register_pci_controller(&bcm63xx_controller);
 171
 172         /* mark memory space used for IO mapping as reserved */
 173         request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
 174                            "bcm63xx PCI IO space");
 175         return 0;
 176 }
 177
 178 arch_initcall(bcm63xx_pci_init);