brcm47xx: add code to generate images for some netgear devices
[openwrt.git] / target / linux / ar71xx / patches-3.3 / 108-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch
1 From db464f2ad82c03f847d8eabbb8251b5c567e6720 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Fri, 18 Nov 2011 11:52:41 +0100
4 Subject: [PATCH 08/35] MIPS: ath79: use io-accessor macros in pci-ar724x.c
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Acked-by: René Bolldorf <xsecute@googlemail.com>
11
12 v4: - add an Acked-by tag from René
13 v3: - no changes
14 v2: - no changes
15 ---
16 arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++--------------
17 1 files changed, 24 insertions(+), 14 deletions(-)
18
19 --- a/arch/mips/pci/pci-ar724x.c
20 +++ b/arch/mips/pci/pci-ar724x.c
21 @@ -11,19 +11,19 @@
22 #include <linux/pci.h>
23 #include <asm/mach-ath79/pci.h>
24
25 -#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
26 -#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
27 -
28 -#define AR724X_PCI_DEV_BASE 0x14000000
29 +#define AR724X_PCI_CFG_BASE 0x14000000
30 +#define AR724X_PCI_CFG_SIZE 0x1000
31 #define AR724X_PCI_MEM_BASE 0x10000000
32 #define AR724X_PCI_MEM_SIZE 0x08000000
33
34 static DEFINE_SPINLOCK(ar724x_pci_lock);
35 +static void __iomem *ar724x_pci_devcfg_base;
36
37 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
38 int size, uint32_t *value)
39 {
40 unsigned long flags, addr, tval, mask;
41 + void __iomem *base;
42
43 if (devfn)
44 return PCIBIOS_DEVICE_NOT_FOUND;
45 @@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu
46 if (where & (size - 1))
47 return PCIBIOS_BAD_REGISTER_NUMBER;
48
49 + base = ar724x_pci_devcfg_base;
50 +
51 spin_lock_irqsave(&ar724x_pci_lock, flags);
52
53 switch (size) {
54 case 1:
55 addr = where & ~3;
56 mask = 0xff000000 >> ((where % 4) * 8);
57 - tval = reg_read(AR724X_PCI_DEV_BASE + addr);
58 + tval = __raw_readl(base + addr);
59 tval = tval & ~mask;
60 *value = (tval >> ((4 - (where % 4))*8));
61 break;
62 case 2:
63 addr = where & ~3;
64 mask = 0xffff0000 >> ((where % 4)*8);
65 - tval = reg_read(AR724X_PCI_DEV_BASE + addr);
66 + tval = __raw_readl(base + addr);
67 tval = tval & ~mask;
68 *value = (tval >> ((4 - (where % 4))*8));
69 break;
70 case 4:
71 - *value = reg_read(AR724X_PCI_DEV_BASE + where);
72 + *value = __raw_readl(base + where);
73 break;
74 default:
75 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
76 @@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b
77 int size, uint32_t value)
78 {
79 unsigned long flags, tval, addr, mask;
80 + void __iomem *base;
81
82 if (devfn)
83 return PCIBIOS_DEVICE_NOT_FOUND;
84 @@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b
85 if (where & (size - 1))
86 return PCIBIOS_BAD_REGISTER_NUMBER;
87
88 + base = ar724x_pci_devcfg_base;
89 +
90 spin_lock_irqsave(&ar724x_pci_lock, flags);
91
92 switch (size) {
93 case 1:
94 - addr = (AR724X_PCI_DEV_BASE + where) & ~3;
95 + addr = where & ~3;
96 mask = 0xff000000 >> ((where % 4)*8);
97 - tval = reg_read(addr);
98 + tval = __raw_readl(base + addr);
99 tval = tval & ~mask;
100 tval |= (value << ((4 - (where % 4))*8)) & mask;
101 - reg_write(addr, tval);
102 + __raw_writel(tval, base + addr);
103 break;
104 case 2:
105 - addr = (AR724X_PCI_DEV_BASE + where) & ~3;
106 + addr = where & ~3;
107 mask = 0xffff0000 >> ((where % 4)*8);
108 - tval = reg_read(addr);
109 + tval = __raw_readl(base + addr);
110 tval = tval & ~mask;
111 tval |= (value << ((4 - (where % 4))*8)) & mask;
112 - reg_write(addr, tval);
113 + __raw_writel(tval, base + addr);
114 break;
115 case 4:
116 - reg_write((AR724X_PCI_DEV_BASE + where), value);
117 + __raw_writel(value, (base + where));
118 break;
119 default:
120 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
121 @@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_
122
123 int __init ar724x_pcibios_init(void)
124 {
125 + ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
126 + AR724X_PCI_CFG_SIZE);
127 + if (ar724x_pci_devcfg_base == NULL)
128 + return -ENOMEM;
129 +
130 register_pci_controller(&ar724x_pci_controller);
131
132 return PCIBIOS_SUCCESSFUL;
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