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ead: fix array overrun
[openwrt.git] / package / mac80211 / patches / 311-rt2x00_implement_support_for_rt2800pci.patch
1 From: Ivo van Doorn <IvDoorn@gmail.com>
2 Date: Sun, 28 Dec 2008 12:48:53 +0000 (+0100)
3 Subject: rt2x00: Implement support for rt2800pci
4 X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fivd%2Frt2x00.git;a=commitdiff_plain;h=0be1744a47e7513f862554273216a8d37d2760e8
5
6 rt2x00: Implement support for rt2800pci
7
8 Add support for the rt2800pci chipset.
9
10 Includes various patches from Mattias, Mark and Felix.
11
12 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
13 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
14 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
15 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
16 ---
17
18 --- a/drivers/net/wireless/rt2x00/Makefile
19 +++ b/drivers/net/wireless/rt2x00/Makefile
20 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
21 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
22 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
23 obj-$(CONFIG_RT61PCI) += rt61pci.o
24 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
25 obj-$(CONFIG_RT2500USB) += rt2500usb.o
26 obj-$(CONFIG_RT73USB) += rt73usb.o
27 --- /dev/null
28 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
29 @@ -0,0 +1,2693 @@
30 +/*
31 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
32 + <http://rt2x00.serialmonkey.com>
33 +
34 + This program is free software; you can redistribute it and/or modify
35 + it under the terms of the GNU General Public License as published by
36 + the Free Software Foundation; either version 2 of the License, or
37 + (at your option) any later version.
38 +
39 + This program is distributed in the hope that it will be useful,
40 + but WITHOUT ANY WARRANTY; without even the implied warranty of
41 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42 + GNU General Public License for more details.
43 +
44 + You should have received a copy of the GNU General Public License
45 + along with this program; if not, write to the
46 + Free Software Foundation, Inc.,
47 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
48 + */
49 +
50 +/*
51 + Module: rt2800pci
52 + Abstract: rt2800pci device specific routines.
53 + Supported chipsets: RT2800E & RT2800ED.
54 + */
55 +
56 +#include <linux/crc-ccitt.h>
57 +#include <linux/delay.h>
58 +#include <linux/etherdevice.h>
59 +#include <linux/init.h>
60 +#include <linux/kernel.h>
61 +#include <linux/module.h>
62 +#include <linux/pci.h>
63 +#include <linux/eeprom_93cx6.h>
64 +
65 +#include "rt2x00.h"
66 +#include "rt2x00pci.h"
67 +#include "rt2800pci.h"
68 +
69 +/*
70 + * Allow hardware encryption to be disabled.
71 + */
72 +static int modparam_nohwcrypt = 0;
73 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
74 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
75 +
76 +/*
77 + * Register access.
78 + * BBP and RF register require indirect register access,
79 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
80 + * These indirect registers work with busy bits,
81 + * and we will try maximal REGISTER_BUSY_COUNT times to access
82 + * the register while taking a REGISTER_BUSY_DELAY us delay
83 + * between each attampt. When the busy bit is still set at that time,
84 + * the access attempt is considered to have failed,
85 + * and we will print an error.
86 + */
87 +#define WAIT_FOR_BBP(__dev, __reg) \
88 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
89 +#define WAIT_FOR_RF(__dev, __reg) \
90 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
91 +#define WAIT_FOR_MCU(__dev, __reg) \
92 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
93 + H2M_MAILBOX_CSR_OWNER, (__reg))
94 +
95 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
96 + const unsigned int word, const u8 value)
97 +{
98 + u32 reg;
99 +
100 + mutex_lock(&rt2x00dev->csr_mutex);
101 +
102 + /*
103 + * Wait until the BBP becomes available, afterwards we
104 + * can safely write the new data into the register.
105 + */
106 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107 + reg = 0;
108 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
109 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
110 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
111 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
112 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
113 +
114 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
115 + }
116 +
117 + mutex_unlock(&rt2x00dev->csr_mutex);
118 +}
119 +
120 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
121 + const unsigned int word, u8 *value)
122 +{
123 + u32 reg;
124 +
125 + mutex_lock(&rt2x00dev->csr_mutex);
126 +
127 + /*
128 + * Wait until the BBP becomes available, afterwards we
129 + * can safely write the read request into the register.
130 + * After the data has been written, we wait until hardware
131 + * returns the correct value, if at any time the register
132 + * doesn't become available in time, reg will be 0xffffffff
133 + * which means we return 0xff to the caller.
134 + */
135 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
136 + reg = 0;
137 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
138 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
139 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
140 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
141 +
142 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
143 +
144 + WAIT_FOR_BBP(rt2x00dev, &reg);
145 + }
146 +
147 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
148 +
149 + mutex_unlock(&rt2x00dev->csr_mutex);
150 +}
151 +
152 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
153 + const unsigned int word, const u32 value)
154 +{
155 + u32 reg;
156 +
157 + if (!word)
158 + return;
159 +
160 + mutex_lock(&rt2x00dev->csr_mutex);
161 +
162 + /*
163 + * Wait until the RF becomes available, afterwards we
164 + * can safely write the new data into the register.
165 + */
166 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
167 + reg = 0;
168 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
169 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
170 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
171 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
172 +
173 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
174 + rt2x00_rf_write(rt2x00dev, word, value);
175 + }
176 +
177 + mutex_unlock(&rt2x00dev->csr_mutex);
178 +}
179 +
180 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
181 + const u8 command, const u8 token,
182 + const u8 arg0, const u8 arg1)
183 +{
184 + u32 reg;
185 +
186 + mutex_lock(&rt2x00dev->csr_mutex);
187 +
188 + /*
189 + * Wait until the MCU becomes available, afterwards we
190 + * can safely write the new data into the register.
191 + */
192 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
193 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
194 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
195 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
196 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
197 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
198 +
199 + reg = 0;
200 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
201 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
202 + }
203 +
204 + mutex_unlock(&rt2x00dev->csr_mutex);
205 +}
206 +
207 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
208 +{
209 + struct rt2x00_dev *rt2x00dev = eeprom->data;
210 + u32 reg;
211 +
212 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
213 +
214 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
215 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
216 + eeprom->reg_data_clock =
217 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
218 + eeprom->reg_chip_select =
219 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
220 +}
221 +
222 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
223 +{
224 + struct rt2x00_dev *rt2x00dev = eeprom->data;
225 + u32 reg = 0;
226 +
227 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
228 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
229 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
230 + !!eeprom->reg_data_clock);
231 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
232 + !!eeprom->reg_chip_select);
233 +
234 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
235 +}
236 +
237 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
238 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
239 + .owner = THIS_MODULE,
240 + .csr = {
241 + .read = rt2x00pci_register_read,
242 + .write = rt2x00pci_register_write,
243 + .flags = RT2X00DEBUGFS_OFFSET,
244 + .word_base = CSR_REG_BASE,
245 + .word_size = sizeof(u32),
246 + .word_count = CSR_REG_SIZE / sizeof(u32),
247 + },
248 + .eeprom = {
249 + .read = rt2x00_eeprom_read,
250 + .write = rt2x00_eeprom_write,
251 + .word_base = EEPROM_BASE,
252 + .word_size = sizeof(u16),
253 + .word_count = EEPROM_SIZE / sizeof(u16),
254 + },
255 + .bbp = {
256 + .read = rt2800pci_bbp_read,
257 + .write = rt2800pci_bbp_write,
258 + .word_base = BBP_BASE,
259 + .word_size = sizeof(u8),
260 + .word_count = BBP_SIZE / sizeof(u8),
261 + },
262 + .rf = {
263 + .read = rt2x00_rf_read,
264 + .write = rt2800pci_rf_write,
265 + .word_base = RF_BASE,
266 + .word_size = sizeof(u32),
267 + .word_count = RF_SIZE / sizeof(u32),
268 + },
269 +};
270 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
271 +
272 +#ifdef CONFIG_RT2X00_LIB_RFKILL
273 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
274 +{
275 + u32 reg;
276 +
277 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
278 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
279 +}
280 +#else
281 +#define rt2800pci_rfkill_poll NULL
282 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
283 +
284 +#ifdef CONFIG_RT2X00_LIB_LEDS
285 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
286 + enum led_brightness brightness)
287 +{
288 + struct rt2x00_led *led =
289 + container_of(led_cdev, struct rt2x00_led, led_dev);
290 + unsigned int enabled = brightness != LED_OFF;
291 + unsigned int bg_mode =
292 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
293 + unsigned int polarity =
294 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
295 + EEPROM_FREQ_LED_POLARITY);
296 + unsigned int ledmode =
297 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
298 + EEPROM_FREQ_LED_MODE);
299 +
300 + if (led->type == LED_TYPE_RADIO) {
301 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
302 + enabled ? 0x20 : 0);
303 + } else if (led->type == LED_TYPE_ASSOC) {
304 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
305 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
306 + } else if (led->type == LED_TYPE_QUALITY) {
307 + /*
308 + * The brightness is divided into 6 levels (0 - 5),
309 + * The specs tell us the following levels:
310 + * 0, 1 ,3, 7, 15, 31
311 + * to determine the level in a simple way we can simply
312 + * work with bitshifting:
313 + * (1 << level) - 1
314 + */
315 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
316 + (1 << brightness / (LED_FULL / 6)) - 1,
317 + polarity);
318 + }
319 +}
320 +
321 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
322 + unsigned long *delay_on,
323 + unsigned long *delay_off)
324 +{
325 + struct rt2x00_led *led =
326 + container_of(led_cdev, struct rt2x00_led, led_dev);
327 + u32 reg;
328 +
329 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
330 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
331 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
332 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
333 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
334 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
335 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
336 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
337 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
338 +
339 + return 0;
340 +}
341 +
342 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
343 + struct rt2x00_led *led,
344 + enum led_type type)
345 +{
346 + led->rt2x00dev = rt2x00dev;
347 + led->type = type;
348 + led->led_dev.brightness_set = rt2800pci_brightness_set;
349 + led->led_dev.blink_set = rt2800pci_blink_set;
350 + led->flags = LED_INITIALIZED;
351 +}
352 +#endif /* CONFIG_RT2X00_LIB_LEDS */
353 +
354 +/*
355 + * Configuration handlers.
356 + */
357 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
358 + struct rt2x00lib_crypto *crypto,
359 + struct ieee80211_key_conf *key)
360 +{
361 + u32 offset;
362 + u32 reg;
363 +
364 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
365 +
366 + reg = 0;
367 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
368 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
369 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
370 + crypto->cipher);
371 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
372 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
373 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
374 + rt2x00pci_register_write(rt2x00dev, offset, reg);
375 +}
376 +
377 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
378 + struct rt2x00lib_crypto *crypto,
379 + struct ieee80211_key_conf *key)
380 +{
381 + struct hw_key_entry key_entry;
382 + struct rt2x00_field32 field;
383 + u32 offset;
384 + u32 mask;
385 + u32 reg;
386 +
387 + if (crypto->cmd == SET_KEY) {
388 + memcpy(key_entry.key, crypto->key,
389 + sizeof(key_entry.key));
390 + memcpy(key_entry.tx_mic, crypto->tx_mic,
391 + sizeof(key_entry.tx_mic));
392 + memcpy(key_entry.rx_mic, crypto->rx_mic,
393 + sizeof(key_entry.rx_mic));
394 +
395 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
396 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
397 + &key_entry, sizeof(key_entry));
398 +
399 + /*
400 + * The driver does not support the IV/EIV generation
401 + * in hardware. However it doesn't support the IV/EIV
402 + * inside the ieee80211 frame either, but requires it
403 + * to be provided seperately for the descriptor.
404 + * rt2x00lib will cut the IV/EIV data out of all frames
405 + * given to us by mac80211, but we must tell mac80211
406 + * to generate the IV/EIV data.
407 + */
408 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
409 + }
410 +
411 + /*
412 + * The cipher types are stored over multiple registers
413 + * starting with SHARED_KEY_MODE_BASE each word will have
414 + * 32 bits and contains the cipher types for 2 modes each.
415 + * Using the correct defines correctly will cause overhead,
416 + * so just calculate the correct offset.
417 + */
418 + mask = key->hw_key_idx % 8;
419 + field.bit_offset = (3 * mask);
420 + field.bit_mask = 0x7 << field.bit_offset;
421 +
422 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
423 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
424 + rt2x00_set_field32(&reg, field,
425 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
426 + rt2x00pci_register_write(rt2x00dev, offset, reg);
427 +
428 + /*
429 + * Update WCID information
430 + */
431 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
432 +
433 + return 0;
434 +}
435 +
436 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
437 + struct rt2x00lib_crypto *crypto,
438 + struct ieee80211_key_conf *key)
439 +{
440 + struct hw_key_entry key_entry;
441 + u32 offset;
442 +
443 + /*
444 + * 1 pairwise key is possible per AID, this means that the AID
445 + * equals our hw_key_idx.
446 + */
447 + key->hw_key_idx = crypto->aid;
448 +
449 + if (crypto->cmd == SET_KEY) {
450 + memcpy(key_entry.key, crypto->key,
451 + sizeof(key_entry.key));
452 + memcpy(key_entry.tx_mic, crypto->tx_mic,
453 + sizeof(key_entry.tx_mic));
454 + memcpy(key_entry.rx_mic, crypto->rx_mic,
455 + sizeof(key_entry.rx_mic));
456 +
457 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
458 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
459 + &key_entry, sizeof(key_entry));
460 +
461 + /*
462 + * The driver does not support the IV/EIV generation
463 + * in hardware. However it doesn't support the IV/EIV
464 + * inside the ieee80211 frame either, but requires it
465 + * to be provided seperately for the descriptor.
466 + * rt2x00lib will cut the IV/EIV data out of all frames
467 + * given to us by mac80211, but we must tell mac80211
468 + * to generate the IV/EIV data.
469 + */
470 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
471 + }
472 +
473 + /*
474 + * Update WCID information
475 + */
476 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
477 +
478 + return 0;
479 +}
480 +
481 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
482 + const unsigned int filter_flags)
483 +{
484 + u32 reg;
485 +
486 + /*
487 + * Start configuration steps.
488 + * Note that the version error will always be dropped
489 + * and broadcast frames will always be accepted since
490 + * there is no filter for it at this time.
491 + */
492 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
493 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
494 + !(filter_flags & FIF_FCSFAIL));
495 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
496 + !(filter_flags & FIF_PLCPFAIL));
497 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
498 + !(filter_flags & FIF_PROMISC_IN_BSS));
499 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
500 + !(filter_flags & FIF_OTHER_BSS));
501 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
502 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
503 + !(filter_flags & FIF_ALLMULTI));
504 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
505 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
506 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
507 + !(filter_flags & FIF_CONTROL));
508 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
509 + !(filter_flags & FIF_CONTROL));
510 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
511 + !(filter_flags & FIF_CONTROL));
512 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
513 + !(filter_flags & FIF_CONTROL));
514 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
515 + !(filter_flags & FIF_CONTROL));
516 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
517 + !(filter_flags & FIF_CONTROL));
518 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
519 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
520 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
521 + !(filter_flags & FIF_CONTROL));
522 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
523 +}
524 +
525 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
526 + struct rt2x00_intf *intf,
527 + struct rt2x00intf_conf *conf,
528 + const unsigned int flags)
529 +{
530 + unsigned int beacon_base;
531 + u32 reg;
532 +
533 + if (flags & CONFIG_UPDATE_TYPE) {
534 + /*
535 + * Clear current synchronisation setup.
536 + * For the Beacon base registers we only need to clear
537 + * the first byte since that byte contains the VALID and OWNER
538 + * bits which (when set to 0) will invalidate the entire beacon.
539 + */
540 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
541 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
542 +
543 + /*
544 + * Enable synchronisation.
545 + */
546 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
547 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
548 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
549 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
550 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
551 + }
552 +
553 + if (flags & CONFIG_UPDATE_MAC) {
554 + reg = le32_to_cpu(conf->mac[1]);
555 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
556 + conf->mac[1] = cpu_to_le32(reg);
557 +
558 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
559 + conf->mac, sizeof(conf->mac));
560 + }
561 +
562 + if (flags & CONFIG_UPDATE_BSSID) {
563 + reg = le32_to_cpu(conf->bssid[1]);
564 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
565 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
566 + conf->bssid[1] = cpu_to_le32(reg);
567 +
568 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
569 + conf->bssid, sizeof(conf->bssid));
570 + }
571 +}
572 +
573 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
574 + struct rt2x00lib_erp *erp)
575 +{
576 + u32 reg;
577 +
578 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
579 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
580 + erp->ack_timeout);
581 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
582 +
583 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
584 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
585 + !!erp->short_preamble);
586 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
587 + !!erp->short_preamble);
588 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
589 +
590 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
591 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
592 + erp->cts_protection ? 2 : 0);
593 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
594 +
595 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
596 + erp->basic_rates);
597 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
598 + erp->basic_rates >> 32);
599 +
600 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
601 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
602 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
603 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
604 +
605 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
606 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
607 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
608 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
609 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
610 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
611 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
612 +}
613 +
614 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
615 + struct antenna_setup *ant)
616 +{
617 + u16 eeprom;
618 + u8 r1;
619 + u8 r3;
620 +
621 + /*
622 + * FIXME: Use requested antenna configuration.
623 + */
624 +
625 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
626 +
627 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
628 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
629 +
630 + /*
631 + * Configure the TX antenna.
632 + */
633 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
634 + case 1:
635 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
636 + break;
637 + case 2:
638 + case 3:
639 + /* Do nothing */
640 + break;
641 + }
642 +
643 + /*
644 + * Configure the RX antenna.
645 + */
646 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
647 + case 1:
648 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
649 + break;
650 + case 2:
651 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
652 + break;
653 + case 3:
654 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
655 + break;
656 + }
657 +
658 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
659 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
660 +}
661 +
662 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
663 + struct rt2x00lib_conf *libconf)
664 +{
665 + u16 eeprom;
666 + short lna_gain;
667 +
668 + if (libconf->rf.channel <= 14) {
669 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
670 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
671 + } else if (libconf->rf.channel <= 64) {
672 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
673 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
674 + } else if (libconf->rf.channel <= 128) {
675 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
676 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
677 + } else {
678 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
679 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
680 + }
681 +
682 + rt2x00dev->lna_gain = lna_gain;
683 +}
684 +
685 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
686 + struct rf_channel *rf,
687 + struct channel_info *info)
688 +{
689 + u32 reg;
690 + unsigned int tx_pin;
691 + u16 eeprom;
692 +
693 + tx_pin = 0;
694 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
695 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
696 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
697 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
698 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
699 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
700 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
701 +
702 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
703 +
704 + /*
705 + * Determine antenna settings from EEPROM
706 + */
707 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
708 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
709 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
710 + /* Turn off unused PA or LNA when only 1T or 1R */
711 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
712 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
713 + }
714 +
715 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
716 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
717 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
718 + /* Turn off unused PA or LNA when only 1T or 1R */
719 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
720 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
721 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
722 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
723 +
724 + if (rf->channel > 14) {
725 + /*
726 + * When TX power is below 0, we should increase it by 7 to
727 + * make it a positive value (Minumum value is -7).
728 + * However this means that values between 0 and 7 have
729 + * double meaning, and we should set a 7DBm boost flag.
730 + */
731 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
732 + (info->tx_power1 >= 0));
733 +
734 + if (info->tx_power1 < 0)
735 + info->tx_power1 += 7;
736 +
737 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
738 + TXPOWER_A_TO_DEV(info->tx_power1));
739 +
740 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
741 + (info->tx_power2 >= 0));
742 +
743 + if (info->tx_power2 < 0)
744 + info->tx_power2 += 7;
745 +
746 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
747 + TXPOWER_A_TO_DEV(info->tx_power2));
748 +
749 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
750 + } else {
751 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
752 + TXPOWER_G_TO_DEV(info->tx_power1));
753 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
754 + TXPOWER_G_TO_DEV(info->tx_power2));
755 +
756 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
757 + }
758 +
759 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
760 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
761 +
762 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
763 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
764 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
765 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
766 +
767 + udelay(200);
768 +
769 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
770 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
771 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
772 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
773 +
774 + udelay(200);
775 +
776 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
777 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
778 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
779 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
780 +
781 + /*
782 + * Change BBP settings
783 + */
784 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
785 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
786 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
787 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
788 +
789 + if (rf->channel <= 14) {
790 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
791 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
792 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
793 + } else {
794 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
795 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
796 + }
797 +
798 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
799 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
800 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
801 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
802 + } else {
803 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
804 +
805 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
806 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
807 + else
808 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
809 +
810 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
811 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
812 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
813 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
814 + }
815 +
816 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
817 +
818 + msleep(1);
819 +}
820 +
821 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
822 + const int txpower)
823 +{
824 + u32 reg;
825 + u32 value = TXPOWER_G_TO_DEV(txpower);
826 + u8 r1;
827 +
828 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
829 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
830 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
831 +
832 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
833 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
834 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
835 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
836 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
837 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
840 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
841 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
842 +
843 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
845 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
846 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
847 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
848 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
851 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
852 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
853 +
854 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
856 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
857 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
858 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
859 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
860 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
861 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
862 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
863 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
864 +
865 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
866 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
867 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
868 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
869 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
870 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
871 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
872 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
873 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
874 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
875 +
876 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
877 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
878 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
879 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
880 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
881 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
882 +}
883 +
884 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
885 + struct rt2x00lib_conf *libconf)
886 +{
887 + u32 reg;
888 +
889 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
890 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
891 + libconf->conf->short_frame_max_tx_count);
892 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
893 + libconf->conf->long_frame_max_tx_count);
894 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
895 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
896 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
897 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
898 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
899 +}
900 +
901 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
902 + struct rt2x00lib_conf *libconf)
903 +{
904 + u32 reg;
905 +
906 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
907 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
908 + libconf->conf->beacon_int * 16);
909 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
910 +}
911 +
912 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
913 + struct rt2x00lib_conf *libconf,
914 + const unsigned int flags)
915 +{
916 + /* Always recalculate LNA gain before changing configuration */
917 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
918 +
919 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
920 + rt2800pci_config_channel(rt2x00dev, &libconf->rf,
921 + &libconf->channel);
922 + if (flags & IEEE80211_CONF_CHANGE_POWER)
923 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
924 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
925 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
926 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
927 + rt2800pci_config_duration(rt2x00dev, libconf);
928 +}
929 +
930 +/*
931 + * Link tuning
932 + */
933 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
934 + struct link_qual *qual)
935 +{
936 + u32 reg;
937 +
938 + /*
939 + * Update FCS error count from register.
940 + */
941 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
942 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
943 +
944 + /*
945 + * Update False CCA count from register.
946 + */
947 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
948 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
949 +}
950 +
951 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
952 +{
953 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
954 + return 0x2e + rt2x00dev->lna_gain;
955 +
956 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
957 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
958 + else
959 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
960 +}
961 +
962 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
963 + struct link_qual *qual, u8 vgc_level)
964 +{
965 + if (qual->vgc_level != vgc_level) {
966 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
967 + qual->vgc_level = vgc_level;
968 + qual->vgc_level_reg = vgc_level;
969 + }
970 +}
971 +
972 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
973 + struct link_qual *qual)
974 +{
975 + rt2800pci_set_vgc(rt2x00dev, qual,
976 + rt2800pci_get_default_vgc(rt2x00dev));
977 +}
978 +
979 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
980 + struct link_qual *qual, const u32 count)
981 +{
982 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
983 + return;
984 +
985 + /*
986 + * When RSSI is better then -80 increase VGC level with 0x10
987 + */
988 + rt2800pci_set_vgc(rt2x00dev, qual,
989 + rt2800pci_get_default_vgc(rt2x00dev) +
990 + ((qual->rssi > -80) * 0x10));
991 +}
992 +
993 +/*
994 + * Firmware functions
995 + */
996 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
997 +{
998 + return FIRMWARE_RT2860;
999 +}
1000 +
1001 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1002 +{
1003 + u16 crc;
1004 +
1005 + /*
1006 + * Use the crc ccitt algorithm.
1007 + * This will return the same value as the legacy driver which
1008 + * used bit ordering reversion on the both the firmware bytes
1009 + * before input input as well as on the final output.
1010 + * Obviously using crc ccitt directly is much more efficient.
1011 + * The last 2 bytes in the firmware array are the crc checksum itself,
1012 + * this means that we should never pass those 2 bytes to the crc
1013 + * algorithm.
1014 + */
1015 + crc = crc_ccitt(~0, data, len - 2);
1016 +
1017 + /*
1018 + * There is a small difference between the crc-itu-t + bitrev and
1019 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1020 + * will be swapped, use swab16 to convert the crc to the correct
1021 + * value.
1022 + */
1023 + return swab16(crc);
1024 +}
1025 +
1026 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1027 + const void *data, const size_t len)
1028 +{
1029 + unsigned int i;
1030 + u32 reg;
1031 +
1032 + /*
1033 + * Wait for stable hardware.
1034 + */
1035 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1036 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1037 + if (reg && reg != ~0)
1038 + break;
1039 + msleep(1);
1040 + }
1041 +
1042 + if (i == REGISTER_BUSY_COUNT) {
1043 + ERROR(rt2x00dev, "Unstable hardware.\n");
1044 + return -EBUSY;
1045 + }
1046 +
1047 + /*
1048 + * Disable DMA, will be reenabled later when enabling
1049 + * the radio.
1050 + */
1051 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1052 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1053 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1054 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1055 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1056 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1057 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1058 +
1059 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, ~0);
1060 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e1f);
1061 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e00);
1062 +
1063 + /*
1064 + * enable Host program ram write selection
1065 + */
1066 + reg = 0;
1067 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1068 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1069 +
1070 + /*
1071 + * Write firmware to device.
1072 + */
1073 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1074 + data, len);
1075 +
1076 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1077 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1078 +
1079 + /*
1080 + * Wait for device to stabilize.
1081 + */
1082 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1083 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1084 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1085 + break;
1086 + msleep(1);
1087 + }
1088 +
1089 + if (i == REGISTER_BUSY_COUNT) {
1090 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1091 + return -EBUSY;
1092 + }
1093 +
1094 + /*
1095 + * Initialize BBP R/W access agent
1096 + */
1097 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1098 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1099 +
1100 + return 0;
1101 +}
1102 +
1103 +/*
1104 + * Initialization functions.
1105 + */
1106 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1107 +{
1108 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1109 + u32 word;
1110 +
1111 + if (entry->queue->qid == QID_RX) {
1112 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1113 +
1114 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1115 + } else {
1116 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1117 +
1118 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1119 + }
1120 +}
1121 +
1122 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1123 +{
1124 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1125 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1126 + u32 word;
1127 +
1128 + if (entry->queue->qid == QID_RX) {
1129 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1130 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1131 + rt2x00_desc_write(entry_priv->desc, 0, word);
1132 +
1133 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1134 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1135 + rt2x00_desc_write(entry_priv->desc, 1, word);
1136 + } else {
1137 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1138 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1139 + rt2x00_desc_write(entry_priv->desc, 1, word);
1140 + }
1141 +}
1142 +
1143 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1144 +{
1145 + struct queue_entry_priv_pci *entry_priv;
1146 + u32 reg;
1147 +
1148 + /*
1149 + * Initialize registers.
1150 + */
1151 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1152 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1153 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1154 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1155 +
1156 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1157 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1158 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1159 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1160 +
1161 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1162 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1163 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1164 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1165 +
1166 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1167 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1168 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1169 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1170 +
1171 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1172 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1173 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1174 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1175 +
1176 + /*
1177 + * Enable global DMA configuration
1178 + */
1179 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1180 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1181 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1182 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1183 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1184 +
1185 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1186 +
1187 + return 0;
1188 +}
1189 +
1190 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1191 +{
1192 + u32 reg;
1193 + unsigned int i;
1194 +
1195 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1196 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1197 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1198 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1199 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1200 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1201 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1202 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1203 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1204 +
1205 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1206 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000000);
1207 +
1208 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1209 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1210 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1211 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1212 +
1213 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1214 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1215 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1216 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1217 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1218 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1219 +
1220 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1221 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1222 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1223 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1224 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1225 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1226 +
1227 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1228 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1229 +
1230 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1231 +
1232 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1233 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1234 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1235 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1236 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1237 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1238 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1239 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1240 +
1241 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1242 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1243 +
1244 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1245 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1246 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1247 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1248 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1249 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1250 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1251 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1252 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1253 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1254 +
1255 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1256 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1257 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1258 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1259 +
1260 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1261 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1262 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1263 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1264 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1265 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1266 +
1267 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1268 +
1269 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1270 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1271 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1272 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1273 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1274 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1275 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1276 +
1277 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1278 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1279 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1280 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1281 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1282 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1283 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1284 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1285 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1286 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1287 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1288 +
1289 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1290 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1291 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1292 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1293 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1294 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1295 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1296 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1297 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1298 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1299 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1300 +
1301 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1302 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1303 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1304 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1305 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1306 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1307 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1308 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1309 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1310 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1311 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1312 +
1313 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1314 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1315 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1316 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1317 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1318 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1319 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1320 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1321 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1322 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1323 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1324 +
1325 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1326 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1327 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1328 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1329 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1330 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1331 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1332 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1333 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1334 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1335 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1336 +
1337 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1338 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1339 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1340 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1341 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1342 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1343 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1344 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1345 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1346 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1347 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1348 +
1349 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1350 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1351 +
1352 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1353 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1354 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1355 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1356 +
1357 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1358 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1359 +
1360 + /*
1361 + * ASIC will keep garbage value after boot, clear encryption keys.
1362 + */
1363 + for (i = 0; i < 254; i++) {
1364 + u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1365 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1366 + wcid, sizeof(wcid));
1367 + }
1368 +
1369 + for (i = 0; i < 4; i++)
1370 + rt2x00pci_register_write(rt2x00dev,
1371 + SHARED_KEY_MODE_ENTRY(i), 0);
1372 +
1373 + for (i = 0; i < 256; i++)
1374 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1375 +
1376 + /*
1377 + * Clear all beacons
1378 + * For the Beacon base registers we only need to clear
1379 + * the first byte since that byte contains the VALID and OWNER
1380 + * bits which (when set to 0) will invalidate the entire beacon.
1381 + */
1382 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1383 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1384 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1385 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1386 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1387 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1388 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1389 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1390 +
1391 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1392 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1393 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1394 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1395 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1396 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1397 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1398 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1399 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1400 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1401 +
1402 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1403 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1404 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1405 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1406 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1407 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1408 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1409 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1410 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1411 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1412 +
1413 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1414 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1415 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1416 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1417 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1418 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1419 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1420 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1421 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1422 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1423 +
1424 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1425 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1426 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1427 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1428 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1429 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1430 +
1431 + /*
1432 + * We must clear the error counters.
1433 + * These registers are cleared on read,
1434 + * so we may pass a useless variable to store the value.
1435 + */
1436 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1437 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1438 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1439 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1440 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1441 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1442 +
1443 + return 0;
1444 +}
1445 +
1446 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1447 +{
1448 + unsigned int i;
1449 + u32 reg;
1450 +
1451 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1452 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1453 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1454 + return 0;
1455 +
1456 + udelay(REGISTER_BUSY_DELAY);
1457 + }
1458 +
1459 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1460 + return -EACCES;
1461 +}
1462 +
1463 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1464 +{
1465 + unsigned int i;
1466 + u8 value;
1467 +
1468 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1469 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1470 + if ((value != 0xff) && (value != 0x00))
1471 + return 0;
1472 + udelay(REGISTER_BUSY_DELAY);
1473 + }
1474 +
1475 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1476 + return -EACCES;
1477 +}
1478 +
1479 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1480 +{
1481 + unsigned int i;
1482 + u16 eeprom;
1483 + u8 reg_id;
1484 + u8 value;
1485 +
1486 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1487 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1488 + return -EACCES;
1489 +
1490 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1491 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1492 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1493 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1494 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1495 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1496 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1497 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1498 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1499 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1500 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1501 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1502 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1503 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1504 +
1505 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1506 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1507 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1508 + }
1509 +
1510 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1511 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1512 +
1513 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1514 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1515 +
1516 + if (eeprom != 0xffff && eeprom != 0x0000) {
1517 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1518 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1519 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1520 + }
1521 + }
1522 +
1523 + return 0;
1524 +}
1525 +
1526 +/*
1527 + * Device state switch handlers.
1528 + */
1529 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1530 + enum dev_state state)
1531 +{
1532 + u32 reg;
1533 +
1534 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1535 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1536 + (state == STATE_RADIO_RX_ON) ||
1537 + (state == STATE_RADIO_RX_ON_LINK));
1538 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1539 +}
1540 +
1541 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1542 + enum dev_state state)
1543 +{
1544 + int mask = (state == STATE_RADIO_IRQ_ON);
1545 + u32 reg;
1546 +
1547 + /*
1548 + * When interrupts are being enabled, the interrupt registers
1549 + * should clear the register to assure a clean state.
1550 + */
1551 + if (state == STATE_RADIO_IRQ_ON) {
1552 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1553 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1554 + }
1555 +
1556 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1557 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1558 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1559 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1560 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1561 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1562 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1563 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1564 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1565 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1566 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1567 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1568 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1569 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1570 +}
1571 +
1572 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1573 +{
1574 + unsigned int i;
1575 + u32 reg;
1576 +
1577 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1578 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1579 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1580 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1581 + return 0;
1582 +
1583 + msleep(1);
1584 + }
1585 +
1586 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1587 + return -EACCES;
1588 +}
1589 +
1590 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1591 +{
1592 + u32 reg;
1593 + u16 word;
1594 +
1595 + /*
1596 + * Initialize all registers.
1597 + */
1598 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1599 + rt2800pci_init_queues(rt2x00dev) ||
1600 + rt2800pci_init_registers(rt2x00dev) ||
1601 + rt2800pci_init_bbp(rt2x00dev)))
1602 + return -EIO;
1603 +
1604 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001a80);
1605 +
1606 + /* Wait for DMA, ignore error */
1607 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1608 +
1609 + /*
1610 + * Enable RX.
1611 + */
1612 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1613 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1614 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1615 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1616 +
1617 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1618 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1619 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1620 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1621 +
1622 + /*
1623 + * Initialize LED control
1624 + */
1625 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1626 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1627 + word & 0xff, (word >> 8) & 0xff);
1628 +
1629 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1630 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1631 + word & 0xff, (word >> 8) & 0xff);
1632 +
1633 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1634 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1635 + word & 0xff, (word >> 8) & 0xff);
1636 +
1637 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1638 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1639 +
1640 + /*
1641 + * Send signal to firmware during boot time.
1642 + */
1643 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1644 +
1645 + return 0;
1646 +}
1647 +
1648 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1649 +{
1650 + u32 reg;
1651 +
1652 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1653 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1654 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1655 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1656 +
1657 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1658 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1659 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1660 +
1661 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1662 +
1663 + /* Wait for DMA, ignore error */
1664 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1665 +}
1666 +
1667 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1668 + enum dev_state state)
1669 +{
1670 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1671 +
1672 + if (state == STATE_AWAKE)
1673 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1674 + else
1675 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1676 +
1677 + return 0;
1678 +}
1679 +
1680 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1681 + enum dev_state state)
1682 +{
1683 + int retval = 0;
1684 +
1685 + switch (state) {
1686 + case STATE_RADIO_ON:
1687 + /*
1688 + * Before the radio can be enabled, the device first has
1689 + * to be woken up. After that it needs a bit of time
1690 + * to be fully awake and the radio can be enabled.
1691 + */
1692 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1693 + msleep(1);
1694 + retval = rt2800pci_enable_radio(rt2x00dev);
1695 + break;
1696 + case STATE_RADIO_OFF:
1697 + /*
1698 + * After the radio has been disablee, the device should
1699 + * be put to sleep for powersaving.
1700 + */
1701 + rt2800pci_disable_radio(rt2x00dev);
1702 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1703 + break;
1704 + case STATE_RADIO_RX_ON:
1705 + case STATE_RADIO_RX_ON_LINK:
1706 + case STATE_RADIO_RX_OFF:
1707 + case STATE_RADIO_RX_OFF_LINK:
1708 + rt2800pci_toggle_rx(rt2x00dev, state);
1709 + break;
1710 + case STATE_RADIO_IRQ_ON:
1711 + case STATE_RADIO_IRQ_OFF:
1712 + rt2800pci_toggle_irq(rt2x00dev, state);
1713 + break;
1714 + case STATE_DEEP_SLEEP:
1715 + case STATE_SLEEP:
1716 + case STATE_STANDBY:
1717 + case STATE_AWAKE:
1718 + retval = rt2800pci_set_state(rt2x00dev, state);
1719 + break;
1720 + default:
1721 + retval = -ENOTSUPP;
1722 + break;
1723 + }
1724 +
1725 + if (unlikely(retval))
1726 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1727 + state, retval);
1728 +
1729 + return retval;
1730 +}
1731 +
1732 +/*
1733 + * TX descriptor initialization
1734 + */
1735 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1736 + struct sk_buff *skb,
1737 + struct txentry_desc *txdesc)
1738 +{
1739 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1740 + __le32 *txd = skbdesc->desc;
1741 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1742 + u32 word;
1743 +
1744 + /*
1745 + * Initialize TX Info descriptor
1746 + */
1747 + rt2x00_desc_read(txwi, 0, &word);
1748 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1749 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1750 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1751 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1752 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1753 + rt2x00_set_field32(&word, TXWI_W0_TS,
1754 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1755 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1756 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1757 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1758 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1759 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1760 + rt2x00_set_field32(&word, TXWI_W0_BW,
1761 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1762 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1763 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1764 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1765 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1766 + rt2x00_desc_write(txwi, 0, word);
1767 +
1768 + rt2x00_desc_read(txwi, 1, &word);
1769 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1770 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1771 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1772 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1773 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1774 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1775 + skbdesc->entry->entry_idx);
1776 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1777 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1778 + skbdesc->entry->queue->qid);
1779 + rt2x00_desc_write(txwi, 1, word);
1780 +
1781 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1782 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1783 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1784 + }
1785 +
1786 + /*
1787 + * Initialize TX descriptor
1788 + */
1789 + rt2x00_desc_read(txd, 0, &word);
1790 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1791 + rt2x00_desc_write(txd, 0, word);
1792 +
1793 + rt2x00_desc_read(txd, 1, &word);
1794 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1795 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1796 + rt2x00_set_field32(&word, TXD_W1_BURST,
1797 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1798 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1799 + rt2x00dev->hw->extra_tx_headroom);
1800 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1801 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1802 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1803 + rt2x00_desc_write(txd, 1, word);
1804 +
1805 + rt2x00_desc_read(txd, 2, &word);
1806 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1807 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1808 + rt2x00_desc_write(txd, 2, word);
1809 +
1810 + rt2x00_desc_read(txd, 3, &word);
1811 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1812 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1813 + rt2x00_desc_write(txd, 3, word);
1814 +}
1815 +
1816 +/*
1817 + * TX data initialization
1818 + */
1819 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1820 +{
1821 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1822 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1823 + unsigned int beacon_base;
1824 + u32 reg;
1825 +
1826 + /*
1827 + * Disable beaconing while we are reloading the beacon data,
1828 + * otherwise we might be sending out invalid data.
1829 + */
1830 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1831 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1832 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1833 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1834 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1835 +
1836 + /*
1837 + * Write entire beacon with descriptor to register.
1838 + */
1839 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1840 + rt2x00pci_register_multiwrite(rt2x00dev,
1841 + beacon_base,
1842 + skbdesc->desc, skbdesc->desc_len);
1843 + rt2x00pci_register_multiwrite(rt2x00dev,
1844 + beacon_base + skbdesc->desc_len,
1845 + entry->skb->data, entry->skb->len);
1846 +
1847 + /*
1848 + * Clean up beacon skb.
1849 + */
1850 + dev_kfree_skb_any(entry->skb);
1851 + entry->skb = NULL;
1852 +}
1853 +
1854 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1855 + const enum data_queue_qid queue_idx)
1856 +{
1857 + struct data_queue *queue;
1858 + unsigned int idx, qidx = 0;
1859 + u32 reg;
1860 +
1861 + if (queue_idx == QID_BEACON) {
1862 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1863 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1864 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1865 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1866 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1867 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1868 + }
1869 + return;
1870 + }
1871 +
1872 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1873 + return;
1874 +
1875 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1876 + idx = queue->index[Q_INDEX];
1877 +
1878 + if (queue_idx == QID_MGMT)
1879 + qidx = 5;
1880 + else
1881 + qidx = queue_idx;
1882 +
1883 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1884 +}
1885 +
1886 +/*
1887 + * RX control handlers
1888 + */
1889 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1890 + struct rxdone_entry_desc *rxdesc)
1891 +{
1892 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1893 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1894 + __le32 *rxd = entry_priv->desc;
1895 + __le32 *rxwi = (__le32 *)entry->skb->data;
1896 + u32 rxd3;
1897 + u32 rxwi0;
1898 + u32 rxwi1;
1899 + u32 rxwi2;
1900 + u32 rxwi3;
1901 +
1902 + rt2x00_desc_read(rxd, 3, &rxd3);
1903 + rt2x00_desc_read(rxwi, 0, &rxwi0);
1904 + rt2x00_desc_read(rxwi, 1, &rxwi1);
1905 + rt2x00_desc_read(rxwi, 2, &rxwi2);
1906 + rt2x00_desc_read(rxwi, 3, &rxwi3);
1907 +
1908 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1909 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1910 +
1911 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1912 + /*
1913 + * Unfortunately we don't know the cipher type used during
1914 + * decryption. This prevents us from correct providing
1915 + * correct statistics through debugfs.
1916 + */
1917 + rxdesc->cipher = CIPHER_NONE;
1918 + rxdesc->cipher_status =
1919 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1920 + }
1921 +
1922 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
1923 + /*
1924 + * Hardware has stripped IV/EIV data from 802.11 frame during
1925 + * decryption. Unfortunately the descriptor doesn't contain
1926 + * any fields with the EIV/IV data either, so they can't
1927 + * be restored by rt2x00lib.
1928 + */
1929 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1930 +
1931 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1932 + rxdesc->flags |= RX_FLAG_DECRYPTED;
1933 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1934 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1935 + }
1936 +
1937 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
1938 + rxdesc->dev_flags |= RXDONE_MY_BSS;
1939 +
1940 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
1941 + rxdesc->flags |= RX_FLAG_SHORT_GI;
1942 +
1943 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
1944 + rxdesc->flags |= RX_FLAG_40MHZ;
1945 +
1946 + switch (rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE)) {
1947 + case RATE_MODE_CCK:
1948 + /*
1949 + * Mask of 0x8 bit to remove the short preamble flag.
1950 + */
1951 + rxdesc->signal =
1952 + (RATE_MODE_CCK << 8) |
1953 + (rt2x00_get_field32(rxwi1, RXWI_W1_MCS) & ~0x8);
1954 + break;
1955 + case RATE_MODE_OFDM:
1956 + rxdesc->signal =
1957 + (RATE_MODE_OFDM << 8) |
1958 + rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1959 + break;
1960 + case RATE_MODE_HT_MIX:
1961 + case RATE_MODE_HT_GREENFIELD:
1962 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1963 + rxdesc->flags |= RX_FLAG_HT;
1964 + break;
1965 + }
1966 +
1967 + rxdesc->rssi =
1968 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1969 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1970 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1971 +
1972 + rxdesc->noise =
1973 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1974 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1975 +
1976 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1977 +
1978 + /*
1979 + * Remove TXWI descriptor from start of buffer.
1980 + */
1981 + skb_pull(entry->skb, TXWI_DESC_SIZE);
1982 + skb_trim(entry->skb, rxdesc->size);
1983 +}
1984 +
1985 +/*
1986 + * Interrupt functions.
1987 + */
1988 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
1989 +{
1990 + struct data_queue *queue;
1991 + struct queue_entry *entry;
1992 + struct queue_entry *entry_done;
1993 + struct queue_entry_priv_pci *entry_priv;
1994 + struct txdone_entry_desc txdesc;
1995 + u32 word;
1996 + u32 reg;
1997 + u32 old_reg;
1998 + int type;
1999 + int index;
2000 +
2001 + /*
2002 + * During each loop we will compare the freshly read
2003 + * TX_STA_FIFO register value with the value read from
2004 + * the previous loop. If the 2 values are equal then
2005 + * we should stop processing because the chance it
2006 + * quite big that the device has been unplugged and
2007 + * we risk going into an endless loop.
2008 + */
2009 + old_reg = 0;
2010 +
2011 + while (1) {
2012 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2013 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2014 + break;
2015 +
2016 + if (old_reg == reg)
2017 + break;
2018 + old_reg = reg;
2019 +
2020 + /*
2021 + * Skip this entry when it contains an invalid
2022 + * queue identication number.
2023 + */
2024 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2025 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2026 + if (unlikely(!queue))
2027 + continue;
2028 +
2029 + /*
2030 + * Skip this entry when it contains an invalid
2031 + * index number.
2032 + */
2033 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2034 + if (unlikely(index >= queue->limit))
2035 + continue;
2036 +
2037 + entry = &queue->entries[index];
2038 + entry_priv = entry->priv_data;
2039 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2040 +
2041 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2042 + while (entry != entry_done) {
2043 + /*
2044 + * Catch up.
2045 + * Just report any entries we missed as failed.
2046 + */
2047 + WARNING(rt2x00dev,
2048 + "TX status report missed for entry %d\n",
2049 + entry_done->entry_idx);
2050 +
2051 + txdesc.flags = 0;
2052 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2053 + txdesc.retry = 0;
2054 +
2055 + rt2x00lib_txdone(entry_done, &txdesc);
2056 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2057 + }
2058 +
2059 + /*
2060 + * Obtain the status about this packet.
2061 + */
2062 + txdesc.flags = 0;
2063 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2064 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2065 + else
2066 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2067 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2068 +
2069 + rt2x00lib_txdone(entry, &txdesc);
2070 + }
2071 +}
2072 +
2073 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2074 +{
2075 + struct rt2x00_dev *rt2x00dev = dev_instance;
2076 + u32 reg;
2077 +
2078 + /* Read status and ACK all interrupts */
2079 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2080 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2081 +
2082 + if (!reg)
2083 + return IRQ_NONE;
2084 +
2085 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2086 + return IRQ_HANDLED;
2087 +
2088 + /*
2089 + * 1 - Rx ring done interrupt.
2090 + */
2091 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2092 + rt2x00pci_rxdone(rt2x00dev);
2093 +
2094 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2095 + rt2800pci_txdone(rt2x00dev);
2096 +
2097 + return IRQ_HANDLED;
2098 +}
2099 +
2100 +/*
2101 + * Device probe functions.
2102 + */
2103 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2104 +{
2105 + struct eeprom_93cx6 eeprom;
2106 + u32 reg;
2107 + u16 word;
2108 + u8 *mac;
2109 + u8 default_lna_gain;
2110 +
2111 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2112 +
2113 + eeprom.data = rt2x00dev;
2114 + eeprom.register_read = rt2800pci_eepromregister_read;
2115 + eeprom.register_write = rt2800pci_eepromregister_write;
2116 + eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2117 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2118 + eeprom.reg_data_in = 0;
2119 + eeprom.reg_data_out = 0;
2120 + eeprom.reg_data_clock = 0;
2121 + eeprom.reg_chip_select = 0;
2122 +
2123 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2124 + EEPROM_SIZE / sizeof(u16));
2125 +
2126 + /*
2127 + * Start validation of the data that has been read.
2128 + */
2129 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2130 + if (!is_valid_ether_addr(mac)) {
2131 + DECLARE_MAC_BUF(macbuf);
2132 +
2133 + random_ether_addr(mac);
2134 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2135 + }
2136 +
2137 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2138 + if (word == 0xffff) {
2139 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2140 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2141 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2142 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2143 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2144 + }
2145 +
2146 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2147 + if (word != 0) {
2148 + /* NIC configuration must always be 0. */
2149 + word = 0;
2150 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2151 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2152 + }
2153 +
2154 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2155 + if ((word & 0x00ff) == 0x00ff) {
2156 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2157 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2158 + LED_MODE_TXRX_ACTIVITY);
2159 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2160 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2161 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2162 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2163 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2164 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2165 + }
2166 +
2167 + /*
2168 + * During the LNA validation we are going to use
2169 + * lna0 as correct value. Note that EEPROM_LNA
2170 + * is never validated.
2171 + */
2172 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2173 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2174 +
2175 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2176 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2177 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2178 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2179 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2180 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2181 +
2182 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2183 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2184 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2185 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2186 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2187 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2188 + default_lna_gain);
2189 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2190 +
2191 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2192 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2193 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2194 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2195 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2196 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2197 +
2198 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2199 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2200 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2201 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2202 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2203 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2204 + default_lna_gain);
2205 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2206 +
2207 + return 0;
2208 +}
2209 +
2210 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2211 +{
2212 + u32 reg;
2213 + u16 value;
2214 + u16 eeprom;
2215 + u16 device;
2216 +
2217 + /*
2218 + * Read EEPROM word for configuration.
2219 + */
2220 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2221 +
2222 + /*
2223 + * Identify RF chipset.
2224 + * To determine the RT chip we have to read the
2225 + * PCI header of the device.
2226 + */
2227 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2228 + PCI_CONFIG_HEADER_DEVICE, &device);
2229 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2230 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2231 + reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2232 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2233 +
2234 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2235 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2236 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2237 + !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2238 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2239 + return -ENODEV;
2240 + }
2241 +
2242 + /*
2243 + * Read frequency offset and RF programming sequence.
2244 + */
2245 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2246 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2247 +
2248 + /*
2249 + * Read external LNA informations.
2250 + */
2251 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2252 +
2253 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2254 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2255 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2256 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2257 +
2258 + /*
2259 + * Detect if this device has an hardware controlled radio.
2260 + */
2261 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2262 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2263 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2264 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2265 +
2266 + /*
2267 + * Store led settings, for correct led behaviour.
2268 + */
2269 +#ifdef CONFIG_RT2X00_LIB_LEDS
2270 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2271 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2272 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2273 +
2274 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2275 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2276 +
2277 + return 0;
2278 +}
2279 +
2280 +/*
2281 + * RF value list for rt2860
2282 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2283 + */
2284 +static const struct rf_channel rf_vals[] = {
2285 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2286 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2287 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2288 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2289 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2290 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2291 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2292 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2293 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2294 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2295 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2296 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2297 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2298 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2299 +
2300 + /* 802.11 UNI / HyperLan 2 */
2301 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2302 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2303 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2304 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2305 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2306 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2307 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2308 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2309 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2310 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2311 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2312 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2313 +
2314 + /* 802.11 HyperLan 2 */
2315 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2316 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2317 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2318 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2319 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2320 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2321 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2322 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2323 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2324 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2325 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2326 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2327 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2328 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2329 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2330 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2331 +
2332 + /* 802.11 UNII */
2333 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2334 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2335 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2336 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2337 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2338 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2339 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2340 +
2341 + /* 802.11 Japan */
2342 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2343 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2344 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2345 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2346 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2347 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2348 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2349 +};
2350 +
2351 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2352 +{
2353 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2354 + struct channel_info *info;
2355 + char *tx_power1;
2356 + char *tx_power2;
2357 + unsigned int i;
2358 +
2359 + /*
2360 + * Initialize all hw fields.
2361 + */
2362 + rt2x00dev->hw->flags =
2363 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2364 + IEEE80211_HW_SIGNAL_DBM;
2365 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2366 +
2367 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2368 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2369 + rt2x00_eeprom_addr(rt2x00dev,
2370 + EEPROM_MAC_ADDR_0));
2371 +
2372 + /*
2373 + * Initialize hw_mode information.
2374 + */
2375 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2376 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2377 +
2378 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2379 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2380 + spec->num_channels = 14;
2381 + spec->channels = rf_vals;
2382 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2383 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2384 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2385 + spec->num_channels = ARRAY_SIZE(rf_vals);
2386 + spec->channels = rf_vals;
2387 + }
2388 +
2389 + /*
2390 + * Initialize HT information.
2391 + */
2392 + spec->ht.ht_supported = true;
2393 + spec->ht.cap =
2394 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2395 + IEEE80211_HT_CAP_GRN_FLD |
2396 + IEEE80211_HT_CAP_SGI_20 |
2397 + IEEE80211_HT_CAP_SGI_40 |
2398 + IEEE80211_HT_CAP_TX_STBC |
2399 + IEEE80211_HT_CAP_RX_STBC |
2400 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2401 + spec->ht.ampdu_factor = 3;
2402 + spec->ht.ampdu_density = 4;
2403 + spec->ht.mcs.rx_mask[0] = 0xff;
2404 + spec->ht.mcs.rx_mask[1] = 0xff;
2405 + spec->ht.mcs.tx_params =
2406 + IEEE80211_HT_MCS_TX_DEFINED;
2407 +
2408 + /*
2409 + * Create channel information array
2410 + */
2411 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2412 + if (!info)
2413 + return -ENOMEM;
2414 +
2415 + spec->channels_info = info;
2416 +
2417 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2418 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2419 +
2420 + for (i = 0; i < 14; i++) {
2421 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2422 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2423 + }
2424 +
2425 + if (spec->num_channels > 14) {
2426 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2427 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2428 +
2429 + for (i = 14; i < spec->num_channels; i++) {
2430 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2431 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2432 + }
2433 + }
2434 +
2435 + return 0;
2436 +}
2437 +
2438 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2439 +{
2440 + int retval;
2441 +
2442 + /*
2443 + * Allocate eeprom data.
2444 + */
2445 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2446 + if (retval)
2447 + return retval;
2448 +
2449 + retval = rt2800pci_init_eeprom(rt2x00dev);
2450 + if (retval)
2451 + return retval;
2452 +
2453 + /*
2454 + * Initialize hw specifications.
2455 + */
2456 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2457 + if (retval)
2458 + return retval;
2459 +
2460 + /*
2461 + * This device requires firmware.
2462 + */
2463 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2464 + if (!modparam_nohwcrypt)
2465 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2466 +
2467 + /*
2468 + * Set the rssi offset.
2469 + */
2470 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2471 +
2472 + return 0;
2473 +}
2474 +
2475 +/*
2476 + * IEEE80211 stack callback functions.
2477 + */
2478 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2479 +{
2480 + struct rt2x00_dev *rt2x00dev = hw->priv;
2481 + u32 reg;
2482 +
2483 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2484 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2485 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2486 +
2487 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2488 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2489 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2490 +
2491 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2492 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2493 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2494 +
2495 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2496 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2497 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2498 +
2499 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2500 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2501 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2502 +
2503 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2504 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2505 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2506 +
2507 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2508 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2509 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2510 +
2511 + return 0;
2512 +}
2513 +
2514 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2515 + const struct ieee80211_tx_queue_params *params)
2516 +{
2517 + struct rt2x00_dev *rt2x00dev = hw->priv;
2518 + struct data_queue *queue;
2519 + struct rt2x00_field32 field;
2520 + int retval;
2521 + u32 reg;
2522 + u32 offset;
2523 +
2524 + /*
2525 + * First pass the configuration through rt2x00lib, that will
2526 + * update the queue settings and validate the input. After that
2527 + * we are free to update the registers based on the value
2528 + * in the queue parameter.
2529 + */
2530 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2531 + if (retval)
2532 + return retval;
2533 +
2534 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2535 +
2536 + /* Update WMM TXOP register */
2537 + if (queue_idx < 2) {
2538 + field.bit_offset = queue_idx * 16;
2539 + field.bit_mask = 0xffff << field.bit_offset;
2540 +
2541 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2542 + rt2x00_set_field32(&reg, field, queue->txop);
2543 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2544 + } else if (queue_idx < 4) {
2545 + field.bit_offset = (queue_idx - 2) * 16;
2546 + field.bit_mask = 0xffff << field.bit_offset;
2547 +
2548 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2549 + rt2x00_set_field32(&reg, field, queue->txop);
2550 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2551 + }
2552 +
2553 + /* Update WMM registers */
2554 + field.bit_offset = queue_idx * 4;
2555 + field.bit_mask = 0xf << field.bit_offset;
2556 +
2557 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2558 + rt2x00_set_field32(&reg, field, queue->aifs);
2559 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2560 +
2561 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2562 + rt2x00_set_field32(&reg, field, queue->cw_min);
2563 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2564 +
2565 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2566 + rt2x00_set_field32(&reg, field, queue->cw_max);
2567 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2568 +
2569 + /* Update EDCA registers */
2570 + if (queue_idx < 4) {
2571 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2572 +
2573 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2574 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2575 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2576 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2577 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2578 + }
2579 +
2580 + return 0;
2581 +}
2582 +
2583 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2584 +{
2585 + struct rt2x00_dev *rt2x00dev = hw->priv;
2586 + u64 tsf;
2587 + u32 reg;
2588 +
2589 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2590 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2591 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2592 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2593 +
2594 + return tsf;
2595 +}
2596 +
2597 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2598 + .tx = rt2x00mac_tx,
2599 + .start = rt2x00mac_start,
2600 + .stop = rt2x00mac_stop,
2601 + .add_interface = rt2x00mac_add_interface,
2602 + .remove_interface = rt2x00mac_remove_interface,
2603 + .config = rt2x00mac_config,
2604 + .config_interface = rt2x00mac_config_interface,
2605 + .configure_filter = rt2x00mac_configure_filter,
2606 + .set_key = rt2x00mac_set_key,
2607 + .get_stats = rt2x00mac_get_stats,
2608 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2609 + .bss_info_changed = rt2x00mac_bss_info_changed,
2610 + .conf_tx = rt2800pci_conf_tx,
2611 + .get_tx_stats = rt2x00mac_get_tx_stats,
2612 + .get_tsf = rt2800pci_get_tsf,
2613 +};
2614 +
2615 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2616 + .irq_handler = rt2800pci_interrupt,
2617 + .probe_hw = rt2800pci_probe_hw,
2618 + .get_firmware_name = rt2800pci_get_firmware_name,
2619 + .get_firmware_crc = rt2800pci_get_firmware_crc,
2620 + .load_firmware = rt2800pci_load_firmware,
2621 + .initialize = rt2x00pci_initialize,
2622 + .uninitialize = rt2x00pci_uninitialize,
2623 + .get_entry_state = rt2800pci_get_entry_state,
2624 + .clear_entry = rt2800pci_clear_entry,
2625 + .set_device_state = rt2800pci_set_device_state,
2626 + .rfkill_poll = rt2800pci_rfkill_poll,
2627 + .link_stats = rt2800pci_link_stats,
2628 + .reset_tuner = rt2800pci_reset_tuner,
2629 + .link_tuner = rt2800pci_link_tuner,
2630 + .write_tx_desc = rt2800pci_write_tx_desc,
2631 + .write_tx_data = rt2x00pci_write_tx_data,
2632 + .write_beacon = rt2800pci_write_beacon,
2633 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2634 + .fill_rxdone = rt2800pci_fill_rxdone,
2635 + .config_shared_key = rt2800pci_config_shared_key,
2636 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2637 + .config_filter = rt2800pci_config_filter,
2638 + .config_intf = rt2800pci_config_intf,
2639 + .config_erp = rt2800pci_config_erp,
2640 + .config_ant = rt2800pci_config_ant,
2641 + .config = rt2800pci_config,
2642 +};
2643 +
2644 +static const struct data_queue_desc rt2800pci_queue_rx = {
2645 + .entry_num = RX_ENTRIES,
2646 + .data_size = DATA_FRAME_SIZE,
2647 + .desc_size = RXD_DESC_SIZE,
2648 + .priv_size = sizeof(struct queue_entry_priv_pci),
2649 +};
2650 +
2651 +static const struct data_queue_desc rt2800pci_queue_tx = {
2652 + .entry_num = TX_ENTRIES,
2653 + .data_size = DATA_FRAME_SIZE,
2654 + .desc_size = TXD_DESC_SIZE,
2655 + .priv_size = sizeof(struct queue_entry_priv_pci),
2656 +};
2657 +
2658 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2659 + .entry_num = 8 * BEACON_ENTRIES,
2660 + .data_size = 0, /* No DMA required for beacons */
2661 + .desc_size = TXWI_DESC_SIZE,
2662 + .priv_size = sizeof(struct queue_entry_priv_pci),
2663 +};
2664 +
2665 +static const struct rt2x00_ops rt2800pci_ops = {
2666 + .name = KBUILD_MODNAME,
2667 + .max_sta_intf = 1,
2668 + .max_ap_intf = 8,
2669 + .eeprom_size = EEPROM_SIZE,
2670 + .rf_size = RF_SIZE,
2671 + .tx_queues = NUM_TX_QUEUES,
2672 + .rx = &rt2800pci_queue_rx,
2673 + .tx = &rt2800pci_queue_tx,
2674 + .bcn = &rt2800pci_queue_bcn,
2675 + .lib = &rt2800pci_rt2x00_ops,
2676 + .hw = &rt2800pci_mac80211_ops,
2677 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2678 + .debugfs = &rt2800pci_rt2x00debug,
2679 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2680 +};
2681 +
2682 +/*
2683 + * RT2800pci module information.
2684 + */
2685 +static struct pci_device_id rt2800pci_device_table[] = {
2686 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2687 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2688 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2689 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2690 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2691 + { 0, }
2692 +};
2693 +
2694 +MODULE_AUTHOR(DRV_PROJECT);
2695 +MODULE_VERSION(DRV_VERSION);
2696 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2697 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2698 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2699 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2700 +MODULE_LICENSE("GPL");
2701 +
2702 +static struct pci_driver rt2800pci_driver = {
2703 + .name = KBUILD_MODNAME,
2704 + .id_table = rt2800pci_device_table,
2705 + .probe = rt2x00pci_probe,
2706 + .remove = __devexit_p(rt2x00pci_remove),
2707 + .suspend = rt2x00pci_suspend,
2708 + .resume = rt2x00pci_resume,
2709 +};
2710 +
2711 +static int __init rt2800pci_init(void)
2712 +{
2713 + return pci_register_driver(&rt2800pci_driver);
2714 +}
2715 +
2716 +static void __exit rt2800pci_exit(void)
2717 +{
2718 + pci_unregister_driver(&rt2800pci_driver);
2719 +}
2720 +
2721 +module_init(rt2800pci_init);
2722 +module_exit(rt2800pci_exit);
2723 --- /dev/null
2724 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2725 @@ -0,0 +1,1873 @@
2726 +/*
2727 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2728 + <http://rt2x00.serialmonkey.com>
2729 +
2730 + This program is free software; you can redistribute it and/or modify
2731 + it under the terms of the GNU General Public License as published by
2732 + the Free Software Foundation; either version 2 of the License, or
2733 + (at your option) any later version.
2734 +
2735 + This program is distributed in the hope that it will be useful,
2736 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2737 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2738 + GNU General Public License for more details.
2739 +
2740 + You should have received a copy of the GNU General Public License
2741 + along with this program; if not, write to the
2742 + Free Software Foundation, Inc.,
2743 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2744 + */
2745 +
2746 +/*
2747 + Module: rt2800pci
2748 + Abstract: Data structures and registers for the rt2800pci module.
2749 + Supported chipsets: RT2800E & RT2800ED.
2750 + */
2751 +
2752 +#ifndef RT2800PCI_H
2753 +#define RT2800PCI_H
2754 +
2755 +/*
2756 + * RF chip defines.
2757 + *
2758 + * RF2820 2.4G 2T3R
2759 + * RF2850 2.4G/5G 2T3R
2760 + * RF2720 2.4G 1T2R
2761 + * RF2750 2.4G/5G 1T2R
2762 + * RF3020 2.4G 1T1R
2763 + * RF2020 2.4G B/G
2764 + */
2765 +#define RF2820 0x0001
2766 +#define RF2850 0x0002
2767 +#define RF2720 0x0003
2768 +#define RF2750 0x0004
2769 +#define RF3020 0x0005
2770 +#define RF2020 0x0006
2771 +
2772 +/*
2773 + * RT2860 version
2774 + */
2775 +#define RT2860_VERSION_C 0x0100
2776 +#define RT2860_VERSION_D 0x0101
2777 +#define RT2860_VERSION_E 0x0200
2778 +
2779 +/*
2780 + * Signal information.
2781 + * Defaul offset is required for RSSI <-> dBm conversion.
2782 + */
2783 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2784 +
2785 +/*
2786 + * Register layout information.
2787 + */
2788 +#define CSR_REG_BASE 0x1000
2789 +#define CSR_REG_SIZE 0x0800
2790 +#define EEPROM_BASE 0x0000
2791 +#define EEPROM_SIZE 0x0110
2792 +#define BBP_BASE 0x0000
2793 +#define BBP_SIZE 0x0080
2794 +#define RF_BASE 0x0000
2795 +#define RF_SIZE 0x0014
2796 +
2797 +/*
2798 + * Number of TX queues.
2799 + */
2800 +#define NUM_TX_QUEUES 4
2801 +
2802 +/*
2803 + * PCI registers.
2804 + */
2805 +
2806 +/*
2807 + * PCI Configuration Header
2808 + */
2809 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2810 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2811 +
2812 +/*
2813 + * E2PROM_CSR: EEPROM control register.
2814 + * RELOAD: Write 1 to reload eeprom content.
2815 + * TYPE_93C46: 1: 93c46, 0:93c66.
2816 + * LOAD_STATUS: 1:loading, 0:done.
2817 + */
2818 +#define E2PROM_CSR 0x0004
2819 +#define E2PROM_CSR_RELOAD FIELD32(0x00000001)
2820 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
2821 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
2822 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
2823 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
2824 +#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
2825 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2826 +
2827 +/*
2828 + * HOST-MCU shared memory
2829 + */
2830 +#define HOST_CMD_CSR 0x0404
2831 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2832 +
2833 +/*
2834 + * INT_SOURCE_CSR: Interrupt source register.
2835 + * Write one to clear corresponding bit.
2836 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2837 + */
2838 +#define INT_SOURCE_CSR 0x0200
2839 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2840 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2841 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2842 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2843 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2844 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2845 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2846 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2847 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2848 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2849 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2850 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2851 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2852 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2853 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2854 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2855 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2856 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2857 +
2858 +/*
2859 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2860 + */
2861 +#define INT_MASK_CSR 0x0204
2862 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2863 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2864 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2865 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2866 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2867 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2868 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2869 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2870 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2871 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2872 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x40000000)
2873 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x80000000)
2874 +
2875 +/*
2876 + * WPDMA_GLO_CFG
2877 + */
2878 +#define WPDMA_GLO_CFG 0x0208
2879 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2880 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2881 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2882 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2883 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2884 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2885 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2886 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2887 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2888 +
2889 +/*
2890 + * WPDMA_RST_IDX
2891 + */
2892 +#define WPDMA_RST_IDX 0x020c
2893 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2894 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2895 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2896 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2897 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2898 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2899 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2900 +
2901 +/*
2902 + * DELAY_INT_CFG
2903 + */
2904 +#define DELAY_INT_CFG 0x0210
2905 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2906 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2907 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2908 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2909 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2910 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2911 +
2912 +/*
2913 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2914 + * AIFSN0: AC_BE
2915 + * AIFSN1: AC_BK
2916 + * AIFSN1: AC_VI
2917 + * AIFSN1: AC_VO
2918 + */
2919 +#define WMM_AIFSN_CFG 0x0214
2920 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
2921 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
2922 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
2923 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
2924 +
2925 +/*
2926 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2927 + * CWMIN0: AC_BE
2928 + * CWMIN1: AC_BK
2929 + * CWMIN1: AC_VI
2930 + * CWMIN1: AC_VO
2931 + */
2932 +#define WMM_CWMIN_CFG 0x0218
2933 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
2934 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
2935 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
2936 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
2937 +
2938 +/*
2939 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2940 + * CWMAX0: AC_BE
2941 + * CWMAX1: AC_BK
2942 + * CWMAX1: AC_VI
2943 + * CWMAX1: AC_VO
2944 + */
2945 +#define WMM_CWMAX_CFG 0x021c
2946 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
2947 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
2948 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
2949 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
2950 +
2951 +/*
2952 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2953 + * AC0TXOP: AC_BK in unit of 32us
2954 + * AC1TXOP: AC_BE in unit of 32us
2955 + */
2956 +#define WMM_TXOP0_CFG 0x0220
2957 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
2958 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
2959 +
2960 +/*
2961 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2962 + * AC2TXOP: AC_VI in unit of 32us
2963 + * AC3TXOP: AC_VO in unit of 32us
2964 + */
2965 +#define WMM_TXOP1_CFG 0x0224
2966 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
2967 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
2968 +
2969 +/*
2970 + * RINGREG_DIFF
2971 + */
2972 +#define RINGREG_DIFF 0x0010
2973 +
2974 +/*
2975 + * GPIO_CTRL_CFG:
2976 + */
2977 +#define GPIO_CTRL_CFG 0x0228
2978 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
2979 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
2980 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
2981 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
2982 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
2983 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
2984 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
2985 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
2986 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
2987 +
2988 +/*
2989 + * MCU_CMD_CFG
2990 + */
2991 +#define MCU_CMD_CFG 0x022c
2992 +
2993 +/*
2994 + * AC_BK register offsets
2995 + */
2996 +#define TX_BASE_PTR0 0x0230
2997 +#define TX_MAX_CNT0 0x0234
2998 +#define TX_CTX_IDX0 0x0238
2999 +#define TX_DTX_IDX0 0x023c
3000 +
3001 +/*
3002 + * AC_BE register offsets
3003 + */
3004 +#define TX_BASE_PTR1 0x0240
3005 +#define TX_MAX_CNT1 0x0244
3006 +#define TX_CTX_IDX1 0x0248
3007 +#define TX_DTX_IDX1 0x024c
3008 +
3009 +/*
3010 + * AC_VI register offsets
3011 + */
3012 +#define TX_BASE_PTR2 0x0250
3013 +#define TX_MAX_CNT2 0x0254
3014 +#define TX_CTX_IDX2 0x0258
3015 +#define TX_DTX_IDX2 0x025c
3016 +
3017 +/*
3018 + * AC_VO register offsets
3019 + */
3020 +#define TX_BASE_PTR3 0x0260
3021 +#define TX_MAX_CNT3 0x0264
3022 +#define TX_CTX_IDX3 0x0268
3023 +#define TX_DTX_IDX3 0x026c
3024 +
3025 +/*
3026 + * HCCA register offsets
3027 + */
3028 +#define TX_BASE_PTR4 0x0270
3029 +#define TX_MAX_CNT4 0x0274
3030 +#define TX_CTX_IDX4 0x0278
3031 +#define TX_DTX_IDX4 0x027c
3032 +
3033 +/*
3034 + * MGMT register offsets
3035 + */
3036 +#define TX_BASE_PTR5 0x0280
3037 +#define TX_MAX_CNT5 0x0284
3038 +#define TX_CTX_IDX5 0x0288
3039 +#define TX_DTX_IDX5 0x028c
3040 +
3041 +/*
3042 + * Queue register offset macros
3043 + */
3044 +#define TX_QUEUE_REG_OFFSET 0x10
3045 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3046 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3047 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3048 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3049 +
3050 +/*
3051 + * RX register offsets
3052 + */
3053 +#define RX_BASE_PTR 0x0290
3054 +#define RX_MAX_CNT 0x0294
3055 +#define RX_CRX_IDX 0x0298
3056 +#define RX_DRX_IDX 0x029c
3057 +
3058 +/*
3059 + * PBF_SYS_CTRL
3060 + * HOST_RAM_WRITE: enable Host program ram write selection
3061 + */
3062 +#define PBF_SYS_CTRL 0x0400
3063 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3064 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3065 +
3066 +/*
3067 + * PBF registers
3068 + * Most are for debug. Driver doesn't touch PBF register.
3069 + */
3070 +#define PBF_CFG 0x0408
3071 +#define PBF_MAX_PCNT 0x040c
3072 +#define PBF_CTRL 0x0410
3073 +#define PBF_INT_STA 0x0414
3074 +#define PBF_INT_ENA 0x0418
3075 +
3076 +/*
3077 + * BCN_OFFSET0:
3078 + */
3079 +#define BCN_OFFSET0 0x042c
3080 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3081 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3082 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3083 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3084 +
3085 +/*
3086 + * BCN_OFFSET1:
3087 + */
3088 +#define BCN_OFFSET1 0x0430
3089 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3090 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3091 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3092 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3093 +
3094 +/*
3095 + * PBF registers
3096 + * Most are for debug. Driver doesn't touch PBF register.
3097 + */
3098 +#define TXRXQ_PCNT 0x0438
3099 +#define PBF_DBG 0x043c
3100 +
3101 +/*
3102 + * MAC Control/Status Registers(CSR).
3103 + * Some values are set in TU, whereas 1 TU == 1024 us.
3104 + */
3105 +
3106 +/*
3107 + * MAC_CSR0: ASIC revision number.
3108 + * ASIC_REV: 0
3109 + * ASIC_VER: 2860
3110 + */
3111 +#define MAC_CSR0 0x1000
3112 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3113 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3114 +
3115 +/*
3116 + * MAC_SYS_CTRL:
3117 + */
3118 +#define MAC_SYS_CTRL 0x1004
3119 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3120 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3121 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3122 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3123 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3124 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3125 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3126 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3127 +
3128 +/*
3129 + * MAC_ADDR_DW0: STA MAC register 0
3130 + */
3131 +#define MAC_ADDR_DW0 0x1008
3132 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3133 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3134 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3135 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3136 +
3137 +/*
3138 + * MAC_ADDR_DW1: STA MAC register 1
3139 + * UNICAST_TO_ME_MASK:
3140 + * Used to mask off bits from byte 5 of the MAC address
3141 + * to determine the UNICAST_TO_ME bit for RX frames.
3142 + * The full mask is complemented by BSS_ID_MASK:
3143 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3144 + */
3145 +#define MAC_ADDR_DW1 0x100c
3146 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3147 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3148 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3149 +
3150 +/*
3151 + * MAC_BSSID_DW0: BSSID register 0
3152 + */
3153 +#define MAC_BSSID_DW0 0x1010
3154 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3155 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3156 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3157 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3158 +
3159 +/*
3160 + * MAC_BSSID_DW1: BSSID register 1
3161 + * BSS_ID_MASK:
3162 + * 0: 1-BSSID mode (BSS index = 0)
3163 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3164 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3165 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3166 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3167 + * BSSID. This will make sure that those bits will be ignored
3168 + * when determining the MY_BSS of RX frames.
3169 + */
3170 +#define MAC_BSSID_DW1 0x1014
3171 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3172 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3173 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3174 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3175 +
3176 +/*
3177 + * MAX_LEN_CFG: Maximum frame length register.
3178 + * MAX_MPDU: rt2860b max 16k bytes
3179 + * MAX_PSDU: Maximum PSDU length
3180 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3181 + */
3182 +#define MAX_LEN_CFG 0x1018
3183 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3184 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3185 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3186 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3187 +
3188 +/*
3189 + * BBP_CSR_CFG: BBP serial control register
3190 + * VALUE: Register value to program into BBP
3191 + * REG_NUM: Selected BBP register
3192 + * READ_CONTROL: 0 write BBP, 1 read BBP
3193 + * BUSY: ASIC is busy executing BBP commands
3194 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3195 + * BBP_RW_MODE: 0 serial, 1 paralell
3196 + */
3197 +#define BBP_CSR_CFG 0x101c
3198 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3199 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3200 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3201 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3202 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3203 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3204 +
3205 +/*
3206 + * RF_CSR_CFG0: RF control register
3207 + * REGID_AND_VALUE: Register value to program into RF
3208 + * BITWIDTH: Selected RF register
3209 + * STANDBYMODE: 0 high when standby, 1 low when standby
3210 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3211 + * BUSY: ASIC is busy executing RF commands
3212 + */
3213 +#define RF_CSR_CFG0 0x1020
3214 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3215 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3216 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3217 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3218 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3219 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3220 +
3221 +/*
3222 + * RF_CSR_CFG1: RF control register
3223 + * REGID_AND_VALUE: Register value to program into RF
3224 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3225 + * 0: 3 system clock cycle (37.5usec)
3226 + * 1: 5 system clock cycle (62.5usec)
3227 + */
3228 +#define RF_CSR_CFG1 0x1024
3229 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3230 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3231 +
3232 +/*
3233 + * RF_CSR_CFG2: RF control register
3234 + * VALUE: Register value to program into RF
3235 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3236 + * 0: 3 system clock cycle (37.5usec)
3237 + * 1: 5 system clock cycle (62.5usec)
3238 + */
3239 +#define RF_CSR_CFG2 0x1028
3240 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3241 +
3242 +/*
3243 + * LED_CFG: LED control
3244 + * color LED's:
3245 + * 0: off
3246 + * 1: blinking upon TX2
3247 + * 2: periodic slow blinking
3248 + * 3: always on
3249 + * LED polarity:
3250 + * 0: active low
3251 + * 1: active high
3252 + */
3253 +#define LED_CFG 0x102c
3254 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3255 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3256 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3257 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3258 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3259 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3260 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3261 +
3262 +/*
3263 + * XIFS_TIME_CFG: MAC timing
3264 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3265 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3266 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3267 + * when MAC doesn't reference BBP signal BBRXEND
3268 + * EIFS: unit 1us
3269 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3270 + *
3271 + */
3272 +#define XIFS_TIME_CFG 0x1100
3273 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3274 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3275 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3276 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3277 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3278 +
3279 +/*
3280 + * BKOFF_SLOT_CFG:
3281 + */
3282 +#define BKOFF_SLOT_CFG 0x1104
3283 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3284 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3285 +
3286 +/*
3287 + * NAV_TIME_CFG:
3288 + */
3289 +#define NAV_TIME_CFG 0x1108
3290 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3291 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3292 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3293 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3294 +
3295 +/*
3296 + * CH_TIME_CFG: count as channel busy
3297 + */
3298 +#define CH_TIME_CFG 0x110c
3299 +
3300 +/*
3301 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3302 + */
3303 +#define PBF_LIFE_TIMER 0x1110
3304 +
3305 +/*
3306 + * BCN_TIME_CFG:
3307 + * BEACON_INTERVAL: in unit of 1/16 TU
3308 + * TSF_TICKING: Enable TSF auto counting
3309 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3310 + * BEACON_GEN: Enable beacon generator
3311 + */
3312 +#define BCN_TIME_CFG 0x1114
3313 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3314 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3315 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3316 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3317 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3318 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3319 +
3320 +/*
3321 + * TBTT_SYNC_CFG:
3322 + */
3323 +#define TBTT_SYNC_CFG 0x1118
3324 +
3325 +/*
3326 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3327 + */
3328 +#define TSF_TIMER_DW0 0x111c
3329 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3330 +
3331 +/*
3332 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3333 + */
3334 +#define TSF_TIMER_DW1 0x1120
3335 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3336 +
3337 +/*
3338 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3339 + */
3340 +#define TBTT_TIMER 0x1124
3341 +
3342 +/*
3343 + * INT_TIMER_CFG:
3344 + */
3345 +#define INT_TIMER_CFG 0x1128
3346 +
3347 +/*
3348 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3349 + */
3350 +#define INT_TIMER_EN 0x112c
3351 +
3352 +/*
3353 + * CH_IDLE_STA: channel idle time
3354 + */
3355 +#define CH_IDLE_STA 0x1130
3356 +
3357 +/*
3358 + * CH_BUSY_STA: channel busy time
3359 + */
3360 +#define CH_BUSY_STA 0x1134
3361 +
3362 +/*
3363 + * MAC_STATUS_CFG:
3364 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3365 + * if 1 or higher one of the 2 registers is busy.
3366 + */
3367 +#define MAC_STATUS_CFG 0x1200
3368 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3369 +
3370 +/*
3371 + * PWR_PIN_CFG:
3372 + */
3373 +#define PWR_PIN_CFG 0x1204
3374 +
3375 +/*
3376 + * AUTOWAKEUP_CFG: Manual power control / status register
3377 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3378 + * AUTOWAKE: 0:sleep, 1:awake
3379 + */
3380 +#define AUTOWAKEUP_CFG 0x1208
3381 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3382 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3383 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3384 +
3385 +/*
3386 + * EDCA_AC0_CFG:
3387 + */
3388 +#define EDCA_AC0_CFG 0x1300
3389 +#define EDCA_AC0_CFG_AC_TX_OP FIELD32(0x000000ff)
3390 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3391 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3392 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3393 +
3394 +/*
3395 + * EDCA_AC1_CFG:
3396 + */
3397 +#define EDCA_AC1_CFG 0x1304
3398 +#define EDCA_AC1_CFG_AC_TX_OP FIELD32(0x000000ff)
3399 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3400 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3401 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3402 +
3403 +/*
3404 + * EDCA_AC2_CFG:
3405 + */
3406 +#define EDCA_AC2_CFG 0x1308
3407 +#define EDCA_AC2_CFG_AC_TX_OP FIELD32(0x000000ff)
3408 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3409 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3410 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3411 +
3412 +/*
3413 + * EDCA_AC3_CFG:
3414 + */
3415 +#define EDCA_AC3_CFG 0x130c
3416 +#define EDCA_AC3_CFG_AC_TX_OP FIELD32(0x000000ff)
3417 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3418 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3419 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3420 +
3421 +/*
3422 + * EDCA_TID_AC_MAP:
3423 + */
3424 +#define EDCA_TID_AC_MAP 0x1310
3425 +
3426 +/*
3427 + * TX_PWR_CFG_0:
3428 + */
3429 +#define TX_PWR_CFG_0 0x1314
3430 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3431 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3432 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3433 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3434 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3435 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3436 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3437 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3438 +
3439 +/*
3440 + * TX_PWR_CFG_1:
3441 + */
3442 +#define TX_PWR_CFG_1 0x1318
3443 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3444 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3445 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3446 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3447 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3448 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3449 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3450 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3451 +
3452 +/*
3453 + * TX_PWR_CFG_2:
3454 + */
3455 +#define TX_PWR_CFG_2 0x131c
3456 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3457 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3458 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3459 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3460 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3461 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3462 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3463 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3464 +
3465 +/*
3466 + * TX_PWR_CFG_3:
3467 + */
3468 +#define TX_PWR_CFG_3 0x1320
3469 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3470 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3471 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3472 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3473 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3474 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3475 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3476 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3477 +
3478 +/*
3479 + * TX_PWR_CFG_4:
3480 + */
3481 +#define TX_PWR_CFG_4 0x1324
3482 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3483 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3484 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3485 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3486 +
3487 +/*
3488 + * TX_PIN_CFG:
3489 + */
3490 +#define TX_PIN_CFG 0x1328
3491 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3492 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3493 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3494 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3495 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3496 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3497 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3498 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3499 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3500 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3501 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3502 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3503 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3504 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3505 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3506 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3507 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3508 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3509 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3510 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3511 +
3512 +/*
3513 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3514 + */
3515 +#define TX_BAND_CFG 0x132c
3516 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3517 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3518 +
3519 +/*
3520 + * TX_SW_CFG0:
3521 + */
3522 +#define TX_SW_CFG0 0x1330
3523 +
3524 +/*
3525 + * TX_SW_CFG1:
3526 + */
3527 +#define TX_SW_CFG1 0x1334
3528 +
3529 +/*
3530 + * TX_SW_CFG2:
3531 + */
3532 +#define TX_SW_CFG2 0x1338
3533 +
3534 +/*
3535 + * TXOP_THRES_CFG:
3536 + */
3537 +#define TXOP_THRES_CFG 0x133c
3538 +
3539 +/*
3540 + * TXOP_CTRL_CFG:
3541 + */
3542 +#define TXOP_CTRL_CFG 0x1340
3543 +
3544 +/*
3545 + * TX_RTS_CFG:
3546 + * RTS_THRES: unit:byte
3547 + * RTS_FBK_EN: enable rts rate fallback
3548 + */
3549 +#define TX_RTS_CFG 0x1344
3550 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3551 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3552 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3553 +
3554 +/*
3555 + * TX_TIMEOUT_CFG:
3556 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3557 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3558 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3559 + * it is recommended that:
3560 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3561 + */
3562 +#define TX_TIMEOUT_CFG 0x1348
3563 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3564 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3565 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3566 +
3567 +/*
3568 + * TX_RTY_CFG:
3569 + * SHORT_RTY_LIMIT: short retry limit
3570 + * LONG_RTY_LIMIT: long retry limit
3571 + * LONG_RTY_THRE: Long retry threshoold
3572 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3573 + * 0:expired by retry limit, 1: expired by mpdu life timer
3574 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3575 + * 0:expired by retry limit, 1: expired by mpdu life timer
3576 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3577 + */
3578 +#define TX_RTY_CFG 0x134c
3579 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3580 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3581 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3582 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3583 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3584 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3585 +
3586 +/*
3587 + * TX_LINK_CFG:
3588 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3589 + * MFB_ENABLE: TX apply remote MFB 1:enable
3590 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3591 + * 0: not apply remote remote unsolicit (MFS=7)
3592 + * TX_MRQ_EN: MCS request TX enable
3593 + * TX_RDG_EN: RDG TX enable
3594 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3595 + * REMOTE_MFB: remote MCS feedback
3596 + * REMOTE_MFS: remote MCS feedback sequence number
3597 + */
3598 +#define TX_LINK_CFG 0x1350
3599 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3600 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3601 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3602 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3603 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3604 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3605 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3606 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3607 +
3608 +/*
3609 + * HT_FBK_CFG0:
3610 + */
3611 +#define HT_FBK_CFG0 0x1354
3612 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3613 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3614 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3615 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3616 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3617 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3618 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3619 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3620 +
3621 +/*
3622 + * HT_FBK_CFG1:
3623 + */
3624 +#define HT_FBK_CFG1 0x1358
3625 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3626 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3627 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3628 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3629 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3630 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3631 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3632 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3633 +
3634 +/*
3635 + * LG_FBK_CFG0:
3636 + */
3637 +#define LG_FBK_CFG0 0x135c
3638 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3639 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3640 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3641 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3642 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3643 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3644 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3645 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3646 +
3647 +/*
3648 + * LG_FBK_CFG1:
3649 + */
3650 +#define LG_FBK_CFG1 0x1360
3651 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3652 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3653 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3654 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3655 +
3656 +/*
3657 + * CCK_PROT_CFG: CCK Protection
3658 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3659 + * PROTECT_CTRL: Protection control frame type for CCK TX
3660 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3661 + * PROTECT_NAV: TXOP protection type for CCK TX
3662 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3663 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3664 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3665 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3666 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3667 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3668 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3669 + * RTS_TH_EN: RTS threshold enable on CCK TX
3670 + */
3671 +#define CCK_PROT_CFG 0x1364
3672 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3673 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3674 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3675 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3676 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3677 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3678 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3679 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3680 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3681 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3682 +
3683 +/*
3684 + * OFDM_PROT_CFG: OFDM Protection
3685 + */
3686 +#define OFDM_PROT_CFG 0x1368
3687 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3688 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3689 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3690 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3691 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3692 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3693 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3694 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3695 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3696 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3697 +
3698 +/*
3699 + * MM20_PROT_CFG: MM20 Protection
3700 + */
3701 +#define MM20_PROT_CFG 0x136c
3702 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3703 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3704 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3705 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3706 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3707 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3708 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3709 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3710 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3711 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3712 +
3713 +/*
3714 + * MM40_PROT_CFG: MM40 Protection
3715 + */
3716 +#define MM40_PROT_CFG 0x1370
3717 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3718 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3719 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3720 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3721 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3722 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3723 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3724 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3725 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3726 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3727 +
3728 +/*
3729 + * GF20_PROT_CFG: GF20 Protection
3730 + */
3731 +#define GF20_PROT_CFG 0x1374
3732 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3733 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3734 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3735 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3736 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3737 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3738 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3739 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3740 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3741 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3742 +
3743 +/*
3744 + * GF40_PROT_CFG: GF40 Protection
3745 + */
3746 +#define GF40_PROT_CFG 0x1378
3747 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3748 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3749 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3750 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3751 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3752 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3753 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3754 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3755 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3756 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3757 +
3758 +/*
3759 + * EXP_CTS_TIME:
3760 + */
3761 +#define EXP_CTS_TIME 0x137c
3762 +
3763 +/*
3764 + * EXP_ACK_TIME:
3765 + */
3766 +#define EXP_ACK_TIME 0x1380
3767 +
3768 +/*
3769 + * RX_FILTER_CFG: RX configuration register.
3770 + */
3771 +#define RX_FILTER_CFG 0x1400
3772 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3773 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3774 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3775 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3776 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3777 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3778 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3779 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3780 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3781 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3782 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3783 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3784 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3785 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3786 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3787 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3788 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3789 +
3790 +/*
3791 + * AUTO_RSP_CFG:
3792 + * AUTORESPONDER: 0: disable, 1: enable
3793 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3794 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3795 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3796 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3797 + * DUAL_CTS_EN: Power bit value in control frame
3798 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3799 + */
3800 +#define AUTO_RSP_CFG 0x1404
3801 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3802 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3803 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3804 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3805 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3806 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3807 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3808 +
3809 +/*
3810 + * LEGACY_BASIC_RATE:
3811 + */
3812 +#define LEGACY_BASIC_RATE 0x1408
3813 +
3814 +/*
3815 + * HT_BASIC_RATE:
3816 + */
3817 +#define HT_BASIC_RATE 0x140c
3818 +
3819 +/*
3820 + * HT_CTRL_CFG:
3821 + */
3822 +#define HT_CTRL_CFG 0x1410
3823 +
3824 +/*
3825 + * SIFS_COST_CFG:
3826 + */
3827 +#define SIFS_COST_CFG 0x1414
3828 +
3829 +/*
3830 + * RX_PARSER_CFG:
3831 + * Set NAV for all received frames
3832 + */
3833 +#define RX_PARSER_CFG 0x1418
3834 +
3835 +/*
3836 + * TX_SEC_CNT0:
3837 + */
3838 +#define TX_SEC_CNT0 0x1500
3839 +
3840 +/*
3841 + * RX_SEC_CNT0:
3842 + */
3843 +#define RX_SEC_CNT0 0x1504
3844 +
3845 +/*
3846 + * CCMP_FC_MUTE:
3847 + */
3848 +#define CCMP_FC_MUTE 0x1508
3849 +
3850 +/*
3851 + * TXOP_HLDR_ADDR0:
3852 + */
3853 +#define TXOP_HLDR_ADDR0 0x1600
3854 +
3855 +/*
3856 + * TXOP_HLDR_ADDR1:
3857 + */
3858 +#define TXOP_HLDR_ADDR1 0x1604
3859 +
3860 +/*
3861 + * TXOP_HLDR_ET:
3862 + */
3863 +#define TXOP_HLDR_ET 0x1608
3864 +
3865 +/*
3866 + * QOS_CFPOLL_RA_DW0:
3867 + */
3868 +#define QOS_CFPOLL_RA_DW0 0x160c
3869 +
3870 +/*
3871 + * QOS_CFPOLL_RA_DW1:
3872 + */
3873 +#define QOS_CFPOLL_RA_DW1 0x1610
3874 +
3875 +/*
3876 + * QOS_CFPOLL_QC:
3877 + */
3878 +#define QOS_CFPOLL_QC 0x1614
3879 +
3880 +/*
3881 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3882 + */
3883 +#define RX_STA_CNT0 0x1700
3884 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
3885 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
3886 +
3887 +/*
3888 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3889 + */
3890 +#define RX_STA_CNT1 0x1704
3891 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
3892 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
3893 +
3894 +/*
3895 + * RX_STA_CNT2:
3896 + */
3897 +#define RX_STA_CNT2 0x1708
3898 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
3899 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
3900 +
3901 +/*
3902 + * TX_STA_CNT0: TX Beacon count
3903 + */
3904 +#define TX_STA_CNT0 0x170c
3905 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
3906 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
3907 +
3908 +/*
3909 + * TX_STA_CNT1: TX tx count
3910 + */
3911 +#define TX_STA_CNT1 0x1710
3912 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
3913 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
3914 +
3915 +/*
3916 + * TX_STA_CNT2: TX tx count
3917 + */
3918 +#define TX_STA_CNT2 0x1714
3919 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
3920 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
3921 +
3922 +/*
3923 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3924 + */
3925 +#define TX_STA_FIFO 0x1718
3926 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
3927 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
3928 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
3929 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
3930 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
3931 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
3932 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
3933 +
3934 +/*
3935 + * TX_AGG_CNT: Debug counter
3936 + */
3937 +#define TX_AGG_CNT 0x171c
3938 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
3939 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
3940 +
3941 +/*
3942 + * TX_AGG_CNT0:
3943 + */
3944 +#define TX_AGG_CNT0 0x1720
3945 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
3946 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
3947 +
3948 +/*
3949 + * TX_AGG_CNT1:
3950 + */
3951 +#define TX_AGG_CNT1 0x1724
3952 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
3953 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
3954 +
3955 +/*
3956 + * TX_AGG_CNT2:
3957 + */
3958 +#define TX_AGG_CNT2 0x1728
3959 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
3960 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
3961 +
3962 +/*
3963 + * TX_AGG_CNT3:
3964 + */
3965 +#define TX_AGG_CNT3 0x172c
3966 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
3967 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
3968 +
3969 +/*
3970 + * TX_AGG_CNT4:
3971 + */
3972 +#define TX_AGG_CNT4 0x1730
3973 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
3974 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
3975 +
3976 +/*
3977 + * TX_AGG_CNT5:
3978 + */
3979 +#define TX_AGG_CNT5 0x1734
3980 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
3981 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
3982 +
3983 +/*
3984 + * TX_AGG_CNT6:
3985 + */
3986 +#define TX_AGG_CNT6 0x1738
3987 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
3988 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
3989 +
3990 +/*
3991 + * TX_AGG_CNT7:
3992 + */
3993 +#define TX_AGG_CNT7 0x173c
3994 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
3995 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
3996 +
3997 +/*
3998 + * MPDU_DENSITY_CNT:
3999 + * TX_ZERO_DEL: TX zero length delimiter count
4000 + * RX_ZERO_DEL: RX zero length delimiter count
4001 + */
4002 +#define MPDU_DENSITY_CNT 0x1740
4003 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4004 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4005 +
4006 +/*
4007 + * Security key table memory, base address = 0x1800
4008 + */
4009 +struct hw_pairwise_ta_entry {
4010 + u8 address[6];
4011 + u8 reserved[2];
4012 +} __attribute__ ((packed));
4013 +
4014 +struct wcid_entry {
4015 + u8 rx_ba_bitmat7;
4016 + u8 rx_ba_bitmat0;
4017 + u8 mac[6];
4018 +} __attribute__ ((packed));
4019 +
4020 +struct hw_key_entry {
4021 + u8 key[16];
4022 + u8 tx_mic[8];
4023 + u8 rx_mic[8];
4024 +} __attribute__ ((packed));
4025 +
4026 +/*
4027 + * Security key table memory.
4028 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4029 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4030 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
4031 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4032 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4033 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4034 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
4035 + */
4036 +#define MAC_WCID_BASE 0x1800
4037 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4038 +#define PAIRWISE_IVEIV_TABLE_BASE 0x6000
4039 +#define MAC_IVEIV_TABLE_BASE 0x6000
4040 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4041 +#define SHARED_KEY_TABLE_BASE 0x6c00
4042 +#define SHARED_KEY_MODE_BASE 0x7000
4043 +
4044 +#define SHARED_KEY_ENTRY(__idx) \
4045 + ( SHARED_KEY_TABLE_BASE + \
4046 + ((__idx) * sizeof(struct hw_key_entry)) )
4047 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4048 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4049 +#define PAIRWISE_KEY_ENTRY(__idx) \
4050 + ( PAIRWISE_KEY_TABLE_BASE + \
4051 + ((__idx) * sizeof(struct hw_key_entry)) )
4052 +
4053 +#define MAC_WCID_ENTRY(__idx) \
4054 + ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
4055 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4056 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4057 +
4058 +/*
4059 + * MAC_WCID_ATTRIBUTE:
4060 + * KEYTAB: 0: shared key table, 1: pairwise key table
4061 + * BSS_IDX: multipleBSS index for the WCID
4062 + */
4063 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4064 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE FIELD32(0x0000000e)
4065 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4066 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4067 +
4068 +/*
4069 + * SHARED_KEY_MODE:
4070 + */
4071 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4072 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4073 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4074 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4075 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4076 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4077 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4078 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4079 +
4080 +/*
4081 + * HOST-MCU communication
4082 + */
4083 +
4084 +/*
4085 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4086 + */
4087 +#define H2M_MAILBOX_CSR 0x7010
4088 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4089 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4090 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4091 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4092 +
4093 +/*
4094 + * H2M_MAILBOX_CID:
4095 + */
4096 +#define H2M_MAILBOX_CID 0x7014
4097 +
4098 +/*
4099 + * H2M_MAILBOX_STATUS:
4100 + */
4101 +#define H2M_MAILBOX_STATUS 0x701c
4102 +
4103 +/*
4104 + * H2M_INT_SRC:
4105 + */
4106 +#define H2M_INT_SRC 0x7024
4107 +
4108 +/*
4109 + * H2M_BBP_AGENT:
4110 + */
4111 +#define H2M_BBP_AGENT 0x7028
4112 +
4113 +/*
4114 + * MCU_LEDCS: LED control for MCU Mailbox.
4115 + */
4116 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4117 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4118 +
4119 +/*
4120 + * HW_CS_CTS_BASE:
4121 + * Carrier-sense CTS frame base address.
4122 + * It's where mac stores carrier-sense frame for carrier-sense function.
4123 + */
4124 +#define HW_CS_CTS_BASE 0x7700
4125 +
4126 +/*
4127 + * HW_DFS_CTS_BASE:
4128 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4129 + */
4130 +#define HW_DFS_CTS_BASE 0x7780
4131 +
4132 +/*
4133 + * TXRX control registers - base address 0x3000
4134 + */
4135 +
4136 +/*
4137 + * TXRX_CSR1:
4138 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4139 + */
4140 +#define TXRX_CSR1 0x77d0
4141 +
4142 +/*
4143 + * HW_DEBUG_SETTING_BASE:
4144 + * since NULL frame won't be that long (256 byte)
4145 + * We steal 16 tail bytes to save debugging settings
4146 + */
4147 +#define HW_DEBUG_SETTING_BASE 0x77f0
4148 +#define HW_DEBUG_SETTING_BASE2 0x7770
4149 +
4150 +/*
4151 + * HW_BEACON_BASE
4152 + * In order to support maximum 8 MBSS and its maximum length
4153 + * is 512 bytes for each beacon
4154 + * Three section discontinue memory segments will be used.
4155 + * 1. The original region for BCN 0~3
4156 + * 2. Extract memory from FCE table for BCN 4~5
4157 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4158 + * It occupied those memory of wcid 238~253 for BCN 6
4159 + * and wcid 222~237 for BCN 7
4160 + *
4161 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4162 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4163 + */
4164 +#define HW_BEACON_BASE0 0x7800
4165 +#define HW_BEACON_BASE1 0x7a00
4166 +#define HW_BEACON_BASE2 0x7c00
4167 +#define HW_BEACON_BASE3 0x7e00
4168 +#define HW_BEACON_BASE4 0x7200
4169 +#define HW_BEACON_BASE5 0x7400
4170 +#define HW_BEACON_BASE6 0x5dc0
4171 +#define HW_BEACON_BASE7 0x5bc0
4172 +
4173 +#define HW_BEACON_OFFSET(__index) \
4174 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4175 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4176 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4177 +
4178 +/*
4179 + * 8051 firmware image.
4180 + */
4181 +#define FIRMWARE_RT2860 "rt2860.bin"
4182 +#define FIRMWARE_IMAGE_BASE 0x2000
4183 +
4184 +/*
4185 + * BBP registers.
4186 + * The wordsize of the BBP is 8 bits.
4187 + */
4188 +
4189 +/*
4190 + * BBP 1: TX Antenna
4191 + */
4192 +#define BBP1_TX_POWER FIELD8(0x07)
4193 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4194 +
4195 +/*
4196 + * BBP 3: RX Antenna
4197 + */
4198 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4199 +
4200 +/*
4201 + * RF registers
4202 + */
4203 +
4204 +/*
4205 + * RF 2
4206 + */
4207 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4208 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4209 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4210 +
4211 +/*
4212 + * RF 3
4213 + */
4214 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4215 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4216 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4217 +
4218 +/*
4219 + * RF 4
4220 + */
4221 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4222 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4223 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4224 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4225 +#define RF4_BW40 FIELD32(0x00200000)
4226 +
4227 +/*
4228 + * EEPROM content.
4229 + * The wordsize of the EEPROM is 16 bits.
4230 + */
4231 +
4232 +/*
4233 + * EEPROM Version
4234 + */
4235 +#define EEPROM_VERSION 0x0001
4236 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4237 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4238 +
4239 +/*
4240 + * HW MAC address.
4241 + */
4242 +#define EEPROM_MAC_ADDR_0 0x0002
4243 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4244 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4245 +#define EEPROM_MAC_ADDR1 0x0003
4246 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4247 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4248 +#define EEPROM_MAC_ADDR_2 0x0004
4249 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4250 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4251 +
4252 +/*
4253 + * EEPROM ANTENNA config
4254 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4255 + * TXPATH: 1: 1T, 2: 2T
4256 + */
4257 +#define EEPROM_ANTENNA 0x001a
4258 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4259 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4260 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4261 +
4262 +/*
4263 + * EEPROM NIC config
4264 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4265 + */
4266 +#define EEPROM_NIC 0x001b
4267 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4268 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4269 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4270 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4271 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4272 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4273 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4274 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4275 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4276 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4277 +
4278 +/*
4279 + * EEPROM frequency
4280 + */
4281 +#define EEPROM_FREQ 0x001d
4282 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4283 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4284 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4285 +
4286 +/*
4287 + * EEPROM LED
4288 + * POLARITY_RDY_G: Polarity RDY_G setting.
4289 + * POLARITY_RDY_A: Polarity RDY_A setting.
4290 + * POLARITY_ACT: Polarity ACT setting.
4291 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4292 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4293 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4294 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4295 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4296 + * LED_MODE: Led mode.
4297 + */
4298 +#define EEPROM_LED1 0x001e
4299 +#define EEPROM_LED2 0x001f
4300 +#define EEPROM_LED3 0x0020
4301 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4302 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4303 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4304 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4305 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4306 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4307 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4308 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4309 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4310 +
4311 +/*
4312 + * EEPROM LNA
4313 + */
4314 +#define EEPROM_LNA 0x0022
4315 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4316 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4317 +
4318 +/*
4319 + * EEPROM RSSI BG offset
4320 + */
4321 +#define EEPROM_RSSI_BG 0x0023
4322 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4323 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4324 +
4325 +/*
4326 + * EEPROM RSSI BG2 offset
4327 + */
4328 +#define EEPROM_RSSI_BG2 0x0024
4329 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4330 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4331 +
4332 +/*
4333 + * EEPROM RSSI A offset
4334 + */
4335 +#define EEPROM_RSSI_A 0x0025
4336 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4337 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4338 +
4339 +/*
4340 + * EEPROM RSSI A2 offset
4341 + */
4342 +#define EEPROM_RSSI_A2 0x0026
4343 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4344 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4345 +
4346 +/*
4347 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4348 + * This is delta in 40MHZ.
4349 + * VALUE: Tx Power dalta value (MAX=4)
4350 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4351 + * TXPOWER: Enable:
4352 + */
4353 +#define EEPROM_TXPOWER_DELTA 0x0028
4354 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4355 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4356 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4357 +
4358 +/*
4359 + * EEPROM TXPOWER 802.11G
4360 + */
4361 +#define EEPROM_TXPOWER_BG1 0x0029
4362 +#define EEPROM_TXPOWER_BG2 0x0030
4363 +#define EEPROM_TXPOWER_BG_SIZE 7
4364 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4365 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4366 +
4367 +/*
4368 + * EEPROM TXPOWER 802.11A
4369 + */
4370 +#define EEPROM_TXPOWER_A1 0x003c
4371 +#define EEPROM_TXPOWER_A2 0x0053
4372 +#define EEPROM_TXPOWER_A_SIZE 6
4373 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4374 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4375 +
4376 +/*
4377 + * EEPROM TXpower byrate: 20MHZ power
4378 + */
4379 +#define EEPROM_TXPOWER_BYRATE 0x006f
4380 +
4381 +/*
4382 + * EEPROM BBP.
4383 + */
4384 +#define EEPROM_BBP_START 0x0078
4385 +#define EEPROM_BBP_SIZE 16
4386 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4387 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4388 +
4389 +/*
4390 + * MCU mailbox commands.
4391 + */
4392 +#define MCU_SLEEP 0x30
4393 +#define MCU_WAKEUP 0x31
4394 +#define MCU_LED 0x50
4395 +#define MCU_LED_STRENGTH 0x51
4396 +#define MCU_LED_1 0x52
4397 +#define MCU_LED_2 0x53
4398 +#define MCU_LED_3 0x54
4399 +#define MCU_RADAR 0x60
4400 +#define MCU_BOOT_SIGNAL 0x72
4401 +
4402 +/*
4403 + * DMA descriptor defines.
4404 + */
4405 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4406 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4407 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
4408 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4409 +
4410 +/*
4411 + * TX descriptor format for TX, PRIO and Beacon Ring.
4412 + */
4413 +
4414 +/*
4415 + * Word0
4416 + */
4417 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4418 +
4419 +/*
4420 + * Word1
4421 + */
4422 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4423 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4424 +#define TXD_W1_BURST FIELD32(0x00008000)
4425 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4426 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4427 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4428 +
4429 +/*
4430 + * Word2
4431 + */
4432 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4433 +
4434 +/*
4435 + * Word3
4436 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4437 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4438 + * 0:MGMT, 1:HCCA 2:EDCA
4439 + */
4440 +#define TXD_W3_WIV FIELD32(0x01000000)
4441 +#define TXD_W3_QSEL FIELD32(0x06000000)
4442 +#define TXD_W3_TCO FIELD32(0x20000000)
4443 +#define TXD_W3_UCO FIELD32(0x40000000)
4444 +#define TXD_W3_ICO FIELD32(0x80000000)
4445 +
4446 +/*
4447 + * TX WI structure
4448 + */
4449 +
4450 +/*
4451 + * Word0
4452 + * FRAG: 1 To inform TKIP engine this is a fragment.
4453 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4454 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4455 + * BW: Channel bandwidth 20MHz or 40 MHz
4456 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4457 + */
4458 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4459 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4460 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4461 +#define TXWI_W0_TS FIELD32(0x00000008)
4462 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4463 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4464 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4465 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4466 +#define TXWI_W0_BW FIELD32(0x00800000)
4467 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4468 +#define TXWI_W0_STBC FIELD32(0x06000000)
4469 +#define TXWI_W0_IFS FIELD32(0x08000000)
4470 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4471 +
4472 +/*
4473 + * Word1
4474 + */
4475 +#define TXWI_W1_ACK FIELD32(0x00000001)
4476 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4477 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4478 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4479 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4480 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4481 +
4482 +/*
4483 + * Word2
4484 + */
4485 +#define TXWI_W2_IV FIELD32(0xffffffff)
4486 +
4487 +/*
4488 + * Word3
4489 + */
4490 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4491 +
4492 +/*
4493 + * RX descriptor format for RX Ring.
4494 + */
4495 +
4496 +/*
4497 + * Word0
4498 + */
4499 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
4500 +
4501 +/*
4502 + * Word1
4503 + */
4504 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
4505 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
4506 +#define RXD_W1_LS0 FIELD32(0x40000000)
4507 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
4508 +
4509 +/*
4510 + * Word2
4511 + */
4512 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
4513 +
4514 +/*
4515 + * Word3
4516 + * AMSDU: RX with 802.3 header, not 802.11 header.
4517 + * DECRYPTED: This frame is being decrypted.
4518 + */
4519 +#define RXD_W3_BA FIELD32(0x00000001)
4520 +#define RXD_W3_DATA FIELD32(0x00000002)
4521 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
4522 +#define RXD_W3_FRAG FIELD32(0x00000008)
4523 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
4524 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
4525 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
4526 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
4527 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
4528 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
4529 +#define RXD_W3_AMSDU FIELD32(0x00000800)
4530 +#define RXD_W3_HTC FIELD32(0x00001000)
4531 +#define RXD_W3_RSSI FIELD32(0x00002000)
4532 +#define RXD_W3_L2PAD FIELD32(0x00004000)
4533 +#define RXD_W3_AMPDU FIELD32(0x00008000)
4534 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
4535 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
4536 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
4537 +
4538 +/*
4539 + * RX WI structure
4540 + */
4541 +
4542 +/*
4543 + * Word0
4544 + */
4545 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4546 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4547 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4548 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4549 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4550 +#define RXWI_W0_TID FIELD32(0xf0000000)
4551 +
4552 +/*
4553 + * Word1
4554 + */
4555 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4556 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4557 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4558 +#define RXWI_W1_BW FIELD32(0x00800000)
4559 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4560 +#define RXWI_W1_STBC FIELD32(0x06000000)
4561 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4562 +
4563 +/*
4564 + * Word2
4565 + */
4566 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4567 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4568 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4569 +
4570 +/*
4571 + * Word3
4572 + */
4573 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4574 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4575 +
4576 +/*
4577 + * Macro's for converting txpower from EEPROM to mac80211 value
4578 + * and from mac80211 value to register value.
4579 + */
4580 +#define MIN_G_TXPOWER 0
4581 +#define MIN_A_TXPOWER -7
4582 +#define MAX_G_TXPOWER 31
4583 +#define MAX_A_TXPOWER 15
4584 +#define DEFAULT_TXPOWER 5
4585 +
4586 +#define TXPOWER_G_FROM_DEV(__txpower) \
4587 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4588 +
4589 +#define TXPOWER_G_TO_DEV(__txpower) \
4590 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4591 +
4592 +#define TXPOWER_A_FROM_DEV(__txpower) \
4593 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4594 +
4595 +#define TXPOWER_A_TO_DEV(__txpower) \
4596 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4597 +
4598 +#endif /* RT2800PCI_H */
4599 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4600 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4601 @@ -138,6 +138,10 @@ struct rt2x00_chip {
4602 #define RT2561 0x0302
4603 #define RT2661 0x0401
4604 #define RT2571 0x1300
4605 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
4606 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4607 +#define RT2890 0x0701 /* 2.4GHz PCIe */
4608 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4609
4610 u16 rf;
4611 u32 rev;
Personal OpenWRT clone
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