target/linux/ar71xx/files/drivers/mtd/wrt160nl_part.c

   1 /*
   2  * Copyright (C) 2009 Christian Daniel <cd@maintech.de>
   3  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  *
  19  * TRX flash partition table.
  20  * Based on ar7 map by Felix Fietkau <nbd@openwrt.org>
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/partitions.h>
  30
  31 struct cybertan_header {
  32         char    magic[4];
  33         u8      res1[4];
  34         char    fw_date[3];
  35         char    fw_ver[3];
  36         char    id[4];
  37         char    hw_ver;
  38         char    unused;
  39         u8      flags[2];
  40         u8      res2[10];
  41 };
  42
  43 #define TRX_PARTS       6
  44 #define TRX_MAGIC       0x30524448
  45 #define TRX_MAX_OFFSET  3
  46
  47 struct trx_header {
  48         uint32_t magic;           /* "HDR0" */
  49         uint32_t len;             /* Length of file including header */
  50         uint32_t crc32;           /* 32-bit CRC from flag_version to end of file */
  51         uint32_t flag_version;    /* 0:15 flags, 16:31 version */
  52         uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
  53 };
  54
  55 #define IH_MAGIC        0x27051956      /* Image Magic Number */
  56 #define IH_NMLEN        32              /* Image Name Length */
  57
  58 struct uimage_header {
  59         uint32_t        ih_magic;       /* Image Header Magic Number */
  60         uint32_t        ih_hcrc;        /* Image Header CRC Checksum */
  61         uint32_t        ih_time;        /* Image Creation Timestamp */
  62         uint32_t        ih_size;        /* Image Data Size */
  63         uint32_t        ih_load;        /* Data» Load  Address */
  64         uint32_t        ih_ep;          /* Entry Point Address */
  65         uint32_t        ih_dcrc;        /* Image Data CRC Checksum */
  66         uint8_t         ih_os;          /* Operating System */
  67         uint8_t         ih_arch;        /* CPU architecture */
  68         uint8_t         ih_type;        /* Image Type */
  69         uint8_t         ih_comp;        /* Compression Type */
  70         uint8_t         ih_name[IH_NMLEN];      /* Image Name */
  71 };
  72
  73 struct wrt160nl_header {
  74         struct cybertan_header  cybertan;
  75         struct trx_header       trx;
  76         struct uimage_header    uimage;
  77 } __attribute__ ((packed));
  78
  79 static struct mtd_partition trx_parts[TRX_PARTS];
  80
  81 #define WRT160NL_UBOOT_LEN      0x40000
  82 #define WRT160NL_ART_LEN        0x10000
  83 #define WRT160NL_NVRAM_LEN      0x10000
  84
  85 static int wrt160nl_parse_partitions(struct mtd_info *master,
  86                                      struct mtd_partition **pparts,
  87                                      unsigned long origin)
  88 {
  89         struct wrt160nl_header *header;
  90         struct trx_header *theader;
  91         struct uimage_header *uheader;
  92         size_t retlen;
  93         unsigned int kernel_len;
  94         unsigned int uboot_len = max(master->erasesize, WRT160NL_UBOOT_LEN);
  95         unsigned int nvram_len = max(master->erasesize, WRT160NL_NVRAM_LEN);
  96         unsigned int art_len = max(master->erasesize, WRT160NL_ART_LEN);
  97         int ret;
  98
  99         header = vmalloc(sizeof(*header));
 100         if (!header) {
 101                 return -ENOMEM;
 102                 goto out;
 103         }
 104
 105         ret = master->read(master, uboot_len, sizeof(*header),
 106                            &retlen, (void *) header);
 107         if (ret)
 108                 goto free_hdr;
 109
 110         if (retlen != sizeof(*header)) {
 111                 ret = -EIO;
 112                 goto free_hdr;
 113         }
 114
 115         if (strncmp(header->cybertan.magic, "NL16", 4) != 0) {
 116                 printk(KERN_NOTICE "%s: no WRT160NL signature found\n",
 117                         master->name);
 118                 goto free_hdr;
 119         }
 120
 121         theader = &header->trx;
 122         if (le32_to_cpu(theader->magic) != TRX_MAGIC) {
 123                 printk(KERN_NOTICE "%s: no TRX header found\n", master->name);
 124                 goto free_hdr;
 125         }
 126
 127         uheader = &header->uimage;
 128         if (uheader->ih_magic != IH_MAGIC) {
 129                 printk(KERN_NOTICE "%s: no uImage found\n", master->name);
 130                 goto free_hdr;
 131         }
 132
 133         kernel_len = le32_to_cpu(theader->offsets[1]) +
 134                 sizeof(struct cybertan_header);
 135
 136         trx_parts[0].name = "u-boot";
 137         trx_parts[0].offset = 0;
 138         trx_parts[0].size = uboot_len;
 139         trx_parts[0].mask_flags = MTD_WRITEABLE;
 140
 141         trx_parts[1].name = "kernel";
 142         trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
 143         trx_parts[1].size = kernel_len;
 144         trx_parts[1].mask_flags = 0;
 145
 146         trx_parts[2].name = "rootfs";
 147         trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
 148         trx_parts[2].size = master->size - uboot_len - nvram_len - art_len -
 149                 trx_parts[1].size;
 150         trx_parts[2].mask_flags = 0;
 151
 152         trx_parts[3].name = "nvram";
 153         trx_parts[3].offset = master->size - nvram_len - art_len;
 154         trx_parts[3].size = nvram_len;
 155         trx_parts[3].mask_flags = MTD_WRITEABLE;
 156
 157         trx_parts[4].name = "art";
 158         trx_parts[4].offset = master->size - art_len;
 159         trx_parts[4].size = art_len;
 160         trx_parts[4].mask_flags = MTD_WRITEABLE;
 161
 162         trx_parts[5].name = "firmware";
 163         trx_parts[5].offset = uboot_len;
 164         trx_parts[5].size = master->size - uboot_len - nvram_len - art_len;
 165         trx_parts[5].mask_flags = 0;
 166
 167         *pparts = trx_parts;
 168         ret = TRX_PARTS;
 169
 170 free_hdr:
 171         vfree(header);
 172 out:
 173         return ret;
 174 }
 175
 176 static struct mtd_part_parser wrt160nl_parser = {
 177         .owner          = THIS_MODULE,
 178         .parse_fn       = wrt160nl_parse_partitions,
 179         .name           = "wrt160nl",
 180 };
 181
 182 static int __init wrt160nl_parser_init(void)
 183 {
 184         return register_mtd_parser(&wrt160nl_parser);
 185 }
 186
 187 module_init(wrt160nl_parser_init);
 188
 189 MODULE_LICENSE("GPL");
 190 MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");