target/linux/lantiq/patches-2.6.39/410-spi2.patch

   1 From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
   2 Date: Thu, 3 Mar 2011 17:15:30 +0000 (+0100)
   3 Subject: SPI: lantiq: Add driver for Lantiq SoC SPI controller
   4 X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90;hp=3d21b04682ae8eb1c1965aba39d1796e8c5ad84b
   5
   6 SPI: lantiq: Add driver for Lantiq SoC SPI controller
   7
   8 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
   9 ---
  10
  11 --- a/drivers/spi/Kconfig
  12 +++ b/drivers/spi/Kconfig
  13 @@ -193,6 +193,14 @@ config SPI_IMX
  14           This enables using the Freescale i.MX SPI controllers in master
  15           mode.
  16
  17 +config SPI_LANTIQ
  18 +       tristate "Lantiq SoC SPI controller"
  19 +       depends on SOC_LANTIQ_XWAY
  20 +       select SPI_BITBANG
  21 +       help
  22 +         This driver supports the Lantiq SoC SPI controller in master
  23 +         mode.
  24 +
  25  config SPI_LM70_LLP
  26         tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
  27         depends on PARPORT && EXPERIMENTAL
  28 --- a/drivers/spi/Makefile
  29 +++ b/drivers/spi/Makefile
  30 @@ -26,6 +26,7 @@ obj-$(CONFIG_SPI_EP93XX)              += ep93xx_spi.
  31  obj-$(CONFIG_SPI_GPIO)                 += spi_gpio.o
  32  obj-$(CONFIG_SPI_GPIO_OLD)             += spi_gpio_old.o
  33  obj-$(CONFIG_SPI_IMX)                  += spi_imx.o
  34 +obj-$(CONFIG_SPI_LANTIQ)               += spi_lantiq.o
  35  obj-$(CONFIG_SPI_LM70_LLP)             += spi_lm70llp.o
  36  obj-$(CONFIG_SPI_PXA2XX)               += pxa2xx_spi.o
  37  obj-$(CONFIG_SPI_PXA2XX_PCI)           += pxa2xx_spi_pci.o
  38 --- /dev/null
  39 +++ b/drivers/spi/spi_lantiq.c
  40 @@ -0,0 +1,1063 @@
  41 +/*
  42 + * Lantiq SoC SPI controller
  43 + *
  44 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  45 + *
  46 + * This program is free software; you can distribute it and/or modify it
  47 + * under the terms of the GNU General Public License (Version 2) as
  48 + * published by the Free Software Foundation.
  49 + */
  50 +
  51 +#include <linux/init.h>
  52 +#include <linux/module.h>
  53 +#include <linux/workqueue.h>
  54 +#include <linux/platform_device.h>
  55 +#include <linux/io.h>
  56 +#include <linux/sched.h>
  57 +#include <linux/delay.h>
  58 +#include <linux/interrupt.h>
  59 +#include <linux/completion.h>
  60 +#include <linux/spinlock.h>
  61 +#include <linux/err.h>
  62 +#include <linux/clk.h>
  63 +#include <linux/gpio.h>
  64 +#include <linux/spi/spi.h>
  65 +#include <linux/spi/spi_bitbang.h>
  66 +
  67 +#include <xway.h>
  68 +#include <xway_irq.h>
  69 +#include <lantiq_platform.h>
  70 +
  71 +#define LTQ_SPI_CLC            0x00    /* Clock control */
  72 +#define LTQ_SPI_PISEL          0x04    /* Port input select */
  73 +#define LTQ_SPI_ID             0x08    /* Identification */
  74 +#define LTQ_SPI_CON            0x10    /* Control */
  75 +#define LTQ_SPI_STAT           0x14    /* Status */
  76 +#define LTQ_SPI_WHBSTATE       0x18    /* Write HW modified state */
  77 +#define LTQ_SPI_TB             0x20    /* Transmit buffer */
  78 +#define LTQ_SPI_RB             0x24    /* Receive buffer */
  79 +#define LTQ_SPI_RXFCON         0x30    /* Receive FIFO control */
  80 +#define LTQ_SPI_TXFCON         0x34    /* Transmit FIFO control */
  81 +#define LTQ_SPI_FSTAT          0x38    /* FIFO status */
  82 +#define LTQ_SPI_BRT            0x40    /* Baudrate timer */
  83 +#define LTQ_SPI_BRSTAT         0x44    /* Baudrate timer status */
  84 +#define LTQ_SPI_SFCON          0x60    /* Serial frame control */
  85 +#define LTQ_SPI_SFSTAT         0x64    /* Serial frame status */
  86 +#define LTQ_SPI_GPOCON         0x70    /* General purpose output control */
  87 +#define LTQ_SPI_GPOSTAT                0x74    /* General purpose output status */
  88 +#define LTQ_SPI_FGPO           0x78    /* Forced general purpose output */
  89 +#define LTQ_SPI_RXREQ          0x80    /* Receive request */
  90 +#define LTQ_SPI_RXCNT          0x84    /* Receive count */
  91 +#define LTQ_SPI_DMACON         0xEC    /* DMA control */
  92 +#define LTQ_SPI_IRNEN          0xF4    /* Interrupt node enable */
  93 +#define LTQ_SPI_IRNICR         0xF8    /* Interrupt node interrupt capture */
  94 +#define LTQ_SPI_IRNCR          0xFC    /* Interrupt node control */
  95 +
  96 +#define LTQ_SPI_CLC_SMC_SHIFT  16      /* Clock divider for sleep mode */
  97 +#define LTQ_SPI_CLC_SMC_MASK   0xFF
  98 +#define LTQ_SPI_CLC_RMC_SHIFT  8       /* Clock divider for normal run mode */
  99 +#define LTQ_SPI_CLC_RMC_MASK   0xFF
 100 +#define LTQ_SPI_CLC_DISS       BIT(1)  /* Disable status bit */
 101 +#define LTQ_SPI_CLC_DISR       BIT(0)  /* Disable request bit */
 102 +
 103 +#define LTQ_SPI_ID_TXFS_SHIFT  24      /* Implemented TX FIFO size */
 104 +#define LTQ_SPI_ID_TXFS_MASK   0x3F
 105 +#define LTQ_SPI_ID_RXFS_SHIFT  16      /* Implemented RX FIFO size */
 106 +#define LTQ_SPI_ID_RXFS_MASK   0x3F
 107 +#define LTQ_SPI_ID_REV_MASK    0x1F    /* Hardware revision number */
 108 +#define LTQ_SPI_ID_CFG         BIT(5)  /* DMA interface support */
 109 +
 110 +#define LTQ_SPI_CON_BM_SHIFT   16      /* Data width selection */
 111 +#define LTQ_SPI_CON_BM_MASK    0x1F
 112 +#define LTQ_SPI_CON_EM         BIT(24) /* Echo mode */
 113 +#define LTQ_SPI_CON_IDLE       BIT(23) /* Idle bit value */
 114 +#define LTQ_SPI_CON_ENBV       BIT(22) /* Enable byte valid control */
 115 +#define LTQ_SPI_CON_RUEN       BIT(12) /* Receive underflow error enable */
 116 +#define LTQ_SPI_CON_TUEN       BIT(11) /* Transmit underflow error enable */
 117 +#define LTQ_SPI_CON_AEN                BIT(10) /* Abort error enable */
 118 +#define LTQ_SPI_CON_REN                BIT(9)  /* Receive overflow error enable */
 119 +#define LTQ_SPI_CON_TEN                BIT(8)  /* Transmit overflow error enable */
 120 +#define LTQ_SPI_CON_LB         BIT(7)  /* Loopback control */
 121 +#define LTQ_SPI_CON_PO         BIT(6)  /* Clock polarity control */
 122 +#define LTQ_SPI_CON_PH         BIT(5)  /* Clock phase control */
 123 +#define LTQ_SPI_CON_HB         BIT(4)  /* Heading control */
 124 +#define LTQ_SPI_CON_RXOFF      BIT(1)  /* Switch receiver off */
 125 +#define LTQ_SPI_CON_TXOFF      BIT(0)  /* Switch transmitter off */
 126 +
 127 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
 128 +#define LTQ_SPI_STAT_RXBV_SHIFT        28
 129 +#define LTQ_SPI_STAT_BSY       BIT(13) /* Busy flag */
 130 +#define LTQ_SPI_STAT_RUE       BIT(12) /* Receive underflow error flag */
 131 +#define LTQ_SPI_STAT_TUE       BIT(11) /* Transmit underflow error flag */
 132 +#define LTQ_SPI_STAT_AE                BIT(10) /* Abort error flag */
 133 +#define LTQ_SPI_STAT_RE                BIT(9)  /* Receive error flag */
 134 +#define LTQ_SPI_STAT_TE                BIT(8)  /* Transmit error flag */
 135 +#define LTQ_SPI_STAT_MS                BIT(1)  /* Master/slave select bit */
 136 +#define LTQ_SPI_STAT_EN                BIT(0)  /* Enable bit */
 137 +
 138 +#define LTQ_SPI_WHBSTATE_SETTUE        BIT(15) /* Set transmit underflow error flag */
 139 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
 140 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
 141 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
 142 +#define LTQ_SPI_WHBSTATE_CLRTUE        BIT(11) /* Clear transmit underflow error flag */
 143 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
 144 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9)  /* Clear receive error flag */
 145 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8)  /* Clear transmit error flag */
 146 +#define LTQ_SPI_WHBSTATE_SETME BIT(7)  /* Set mode error flag */
 147 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6)  /* Clear mode error flag */
 148 +#define LTQ_SPI_WHBSTATE_SETRUE        BIT(5)  /* Set receive underflow error flag */
 149 +#define LTQ_SPI_WHBSTATE_CLRRUE        BIT(4)  /* Clear receive underflow error flag */
 150 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3)  /* Set master select bit */
 151 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2)  /* Clear master select bit */
 152 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1)  /* Set enable bit (operational mode) */
 153 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0)  /* Clear enable bit (config mode */
 154 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS    0x0F50
 155 +
 156 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT    8       /* FIFO interrupt trigger level */
 157 +#define LTQ_SPI_RXFCON_RXFITL_MASK     0x3F
 158 +#define LTQ_SPI_RXFCON_RXFLU           BIT(1)  /* FIFO flush */
 159 +#define LTQ_SPI_RXFCON_RXFEN           BIT(0)  /* FIFO enable */
 160 +
 161 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT    8       /* FIFO interrupt trigger level */
 162 +#define LTQ_SPI_TXFCON_TXFITL_MASK     0x3F
 163 +#define LTQ_SPI_TXFCON_TXFLU           BIT(1)  /* FIFO flush */
 164 +#define LTQ_SPI_TXFCON_TXFEN           BIT(0)  /* FIFO enable */
 165 +
 166 +#define LTQ_SPI_FSTAT_RXFFL_MASK       0x3f
 167 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT      0
 168 +#define LTQ_SPI_FSTAT_TXFFL_MASK       0x3f
 169 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT      8
 170 +
 171 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT    8
 172 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT   0
 173 +
 174 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT     8
 175 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT     0
 176 +
 177 +#define LTQ_SPI_RXREQ_RXCNT_MASK       0xFFFF  /* Receive count value */
 178 +#define LTQ_SPI_RXCNT_TODO_MASK                0xFFFF  /* Recevie to-do value */
 179 +
 180 +#define LTQ_SPI_IRNEN_F                BIT(3)  /* Frame end interrupt request */
 181 +#define LTQ_SPI_IRNEN_E                BIT(2)  /* Error end interrupt request */
 182 +#define LTQ_SPI_IRNEN_T                BIT(1)  /* Transmit end interrupt request */
 183 +#define LTQ_SPI_IRNEN_R                BIT(0)  /* Receive end interrupt request */
 184 +#define LTQ_SPI_IRNEN_ALL      0xF
 185 +
 186 +/* Hard-wired GPIOs used by SPI controller */
 187 +#define LTQ_SPI_GPIO_DI        16
 188 +#define LTQ_SPI_GPIO_DO                17
 189 +#define LTQ_SPI_GPIO_CLK       18
 190 +
 191 +struct ltq_spi {
 192 +       struct spi_bitbang      bitbang;
 193 +       struct completion       done;
 194 +       spinlock_t              lock;
 195 +
 196 +       struct device           *dev;
 197 +       void __iomem            *base;
 198 +       struct clk              *clk;
 199 +
 200 +       int                     status;
 201 +       int                     irq[3];
 202 +
 203 +       const u8                *tx;
 204 +       u8                      *rx;
 205 +       u32                     tx_cnt;
 206 +       u32                     rx_cnt;
 207 +       u32                     len;
 208 +       struct spi_transfer     *curr_transfer;
 209 +
 210 +       u32 (*get_tx) (struct ltq_spi *);
 211 +
 212 +       u16                     txfs;
 213 +       u16                     rxfs;
 214 +       unsigned                dma_support:1;
 215 +       unsigned                cfg_mode:1;
 216 +
 217 +};
 218 +
 219 +struct ltq_spi_controller_state {
 220 +       void (*cs_activate) (struct spi_device *);
 221 +       void (*cs_deactivate) (struct spi_device *);
 222 +};
 223 +
 224 +struct ltq_spi_irq_map {
 225 +       char            *name;
 226 +       irq_handler_t   handler;
 227 +};
 228 +
 229 +struct ltq_spi_cs_gpio_map {
 230 +       unsigned        gpio;
 231 +       unsigned        altsel0;
 232 +       unsigned        altsel1;
 233 +};
 234 +
 235 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
 236 +{
 237 +       return spi_master_get_devdata(spi->master);
 238 +}
 239 +
 240 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
 241 +{
 242 +       return ioread32be(hw->base + reg);
 243 +}
 244 +
 245 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
 246 +{
 247 +       iowrite32be(val, hw->base + reg);
 248 +}
 249 +
 250 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
 251 +{
 252 +       u32 val;
 253 +
 254 +       val = ltq_spi_reg_read(hw, reg);
 255 +       val |= bits;
 256 +       ltq_spi_reg_write(hw, val, reg);
 257 +}
 258 +
 259 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
 260 +{
 261 +       u32 val;
 262 +
 263 +       val = ltq_spi_reg_read(hw, reg);
 264 +       val &= ~bits;
 265 +       ltq_spi_reg_write(hw, val, reg);
 266 +}
 267 +
 268 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
 269 +{
 270 +       u32 clc;
 271 +
 272 +       /* Power-up mdule */
 273 +       ltq_pmu_enable(PMU_SPI);
 274 +
 275 +       /*
 276 +        * Set clock divider for run mode to 1 to
 277 +        * run at same frequency as FPI bus
 278 +        */
 279 +       clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
 280 +       ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
 281 +}
 282 +
 283 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
 284 +{
 285 +       /* Set clock divider to 0 and set module disable bit */
 286 +       ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
 287 +
 288 +       /* Power-down mdule */
 289 +       ltq_pmu_disable(PMU_SPI);
 290 +}
 291 +
 292 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
 293 +{
 294 +       u32 val;
 295 +
 296 +       /*
 297 +        * Enable and flush FIFOs. Set interrupt trigger level to
 298 +        * half of FIFO count implemented in hardware.
 299 +        */
 300 +       if (hw->txfs > 1) {
 301 +               val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
 302 +               val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
 303 +               ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
 304 +       }
 305 +
 306 +       if (hw->rxfs > 1) {
 307 +               val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
 308 +               val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
 309 +               ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
 310 +       }
 311 +}
 312 +
 313 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
 314 +{
 315 +       u32 stat;
 316 +       unsigned long timeout;
 317 +
 318 +       timeout = jiffies + msecs_to_jiffies(200);
 319 +
 320 +       do {
 321 +               stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
 322 +               if (!(stat & LTQ_SPI_STAT_BSY))
 323 +                       return 0;
 324 +
 325 +               cond_resched();
 326 +       } while (!time_after_eq(jiffies, timeout));
 327 +
 328 +       dev_err(hw->dev, "SPI wait ready timed out\n");
 329 +
 330 +       return -ETIMEDOUT;
 331 +}
 332 +
 333 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
 334 +{
 335 +       if (hw->cfg_mode)
 336 +               return;
 337 +
 338 +       /*
 339 +        * Putting the SPI module in config mode is only safe if no
 340 +        * transfer is in progress as indicated by busy flag STATE.BSY.
 341 +        */
 342 +       if (ltq_spi_wait_ready(hw)) {
 343 +               ltq_spi_reset_fifos(hw);
 344 +               hw->status = -ETIMEDOUT;
 345 +       }
 346 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
 347 +
 348 +       hw->cfg_mode = 1;
 349 +}
 350 +
 351 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
 352 +{
 353 +       if (!hw->cfg_mode)
 354 +               return;
 355 +
 356 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
 357 +
 358 +       hw->cfg_mode = 0;
 359 +}
 360 +
 361 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
 362 +{
 363 +       const u8 *tx = hw->tx;
 364 +       u32 data = *tx++;
 365 +
 366 +       hw->tx_cnt++;
 367 +       hw->tx++;
 368 +
 369 +       return data;
 370 +}
 371 +
 372 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
 373 +{
 374 +       const u16 *tx = (u16 *) hw->tx;
 375 +       u32 data = *tx++;
 376 +
 377 +       hw->tx_cnt += 2;
 378 +       hw->tx += 2;
 379 +
 380 +       return data;
 381 +}
 382 +
 383 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
 384 +{
 385 +       const u32 *tx = (u32 *) hw->tx;
 386 +       u32 data = *tx++;
 387 +
 388 +       hw->tx_cnt += 4;
 389 +       hw->tx += 4;
 390 +
 391 +       return data;
 392 +}
 393 +
 394 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
 395 +{
 396 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 397 +       u32 bm;
 398 +       u8 bits_per_word = spi->bits_per_word;
 399 +
 400 +       /*
 401 +        * Use either default value of SPI device or value
 402 +        * from current transfer.
 403 +        */
 404 +       if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
 405 +               bits_per_word = hw->curr_transfer->bits_per_word;
 406 +
 407 +       if (bits_per_word <= 8)
 408 +               hw->get_tx = ltq_spi_tx_word_u8;
 409 +       else if (bits_per_word <= 16)
 410 +               hw->get_tx = ltq_spi_tx_word_u16;
 411 +       else if (bits_per_word <= 32)
 412 +               hw->get_tx = ltq_spi_tx_word_u32;
 413 +
 414 +       /* CON.BM value = bits_per_word - 1 */
 415 +       bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
 416 +
 417 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
 418 +                            LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
 419 +       ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
 420 +}
 421 +
 422 +static void ltq_spi_speed_set(struct spi_device *spi)
 423 +{
 424 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 425 +       u32 br, max_speed_hz, spi_clk;
 426 +       u32 speed_hz = spi->max_speed_hz;
 427 +
 428 +       /*
 429 +        * Use either default value of SPI device or value
 430 +        * from current transfer.
 431 +        */
 432 +       if (hw->curr_transfer && hw->curr_transfer->speed_hz)
 433 +               speed_hz = hw->curr_transfer->speed_hz;
 434 +
 435 +       /*
 436 +        * SPI module clock is derived from FPI bus clock dependent on
 437 +        * divider value in CLC.RMS which is always set to 1.
 438 +        */
 439 +       spi_clk = clk_get_rate(hw->clk);
 440 +
 441 +       /*
 442 +        * Maximum SPI clock frequency in master mode is half of
 443 +        * SPI module clock frequency. Maximum reload value of
 444 +        * baudrate generator BR is 2^16.
 445 +        */
 446 +       max_speed_hz = spi_clk / 2;
 447 +       if (speed_hz >= max_speed_hz)
 448 +               br = 0;
 449 +       else
 450 +               br = (max_speed_hz / speed_hz) - 1;
 451 +
 452 +       if (br > 0xFFFF)
 453 +               br = 0xFFFF;
 454 +
 455 +       ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
 456 +}
 457 +
 458 +static void ltq_spi_clockmode_set(struct spi_device *spi)
 459 +{
 460 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 461 +       u32 con;
 462 +
 463 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 464 +
 465 +       /*
 466 +        * SPI mode mapping in CON register:
 467 +        * Mode CPOL CPHA CON.PO CON.PH
 468 +        *  0    0    0      0      1
 469 +        *  1    0    1      0      0
 470 +        *  2    1    0      1      1
 471 +        *  3    1    1      1      0
 472 +        */
 473 +       if (spi->mode & SPI_CPHA)
 474 +               con &= ~LTQ_SPI_CON_PH;
 475 +       else
 476 +               con |= LTQ_SPI_CON_PH;
 477 +
 478 +       if (spi->mode & SPI_CPOL)
 479 +               con |= LTQ_SPI_CON_PO;
 480 +       else
 481 +               con &= ~LTQ_SPI_CON_PO;
 482 +
 483 +       /* Set heading control */
 484 +       if (spi->mode & SPI_LSB_FIRST)
 485 +               con &= ~LTQ_SPI_CON_HB;
 486 +       else
 487 +               con |= LTQ_SPI_CON_HB;
 488 +
 489 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 490 +}
 491 +
 492 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
 493 +{
 494 +       u32 con;
 495 +
 496 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 497 +
 498 +       if (t) {
 499 +               if (t->tx_buf && t->rx_buf) {
 500 +                       con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 501 +               } else if (t->rx_buf) {
 502 +                       con &= ~LTQ_SPI_CON_RXOFF;
 503 +                       con |= LTQ_SPI_CON_TXOFF;
 504 +               } else if (t->tx_buf) {
 505 +                       con &= ~LTQ_SPI_CON_TXOFF;
 506 +                       con |= LTQ_SPI_CON_RXOFF;
 507 +               }
 508 +       } else
 509 +               con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 510 +
 511 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 512 +}
 513 +
 514 +static void ltq_spi_gpio_cs_activate(struct spi_device *spi)
 515 +{
 516 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 517 +       int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
 518 +
 519 +       gpio_set_value(cdata->gpio, val);
 520 +}
 521 +
 522 +static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi)
 523 +{
 524 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 525 +       int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
 526 +
 527 +       gpio_set_value(cdata->gpio, val);
 528 +}
 529 +
 530 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
 531 +{
 532 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 533 +       u32 fgpo;
 534 +
 535 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
 536 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 537 +}
 538 +
 539 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
 540 +{
 541 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 542 +       u32 fgpo;
 543 +
 544 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 545 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 546 +}
 547 +
 548 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
 549 +{
 550 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 551 +       struct ltq_spi_controller_state *cstate = spi->controller_state;
 552 +
 553 +       switch (cs) {
 554 +       case BITBANG_CS_ACTIVE:
 555 +               ltq_spi_bits_per_word_set(spi);
 556 +               ltq_spi_speed_set(spi);
 557 +               ltq_spi_clockmode_set(spi);
 558 +               ltq_spi_run_mode_set(hw);
 559 +
 560 +               cstate->cs_activate(spi);
 561 +               break;
 562 +
 563 +       case BITBANG_CS_INACTIVE:
 564 +               cstate->cs_deactivate(spi);
 565 +
 566 +               ltq_spi_config_mode_set(hw);
 567 +
 568 +               break;
 569 +       }
 570 +}
 571 +
 572 +static int ltq_spi_setup_transfer(struct spi_device *spi,
 573 +                                 struct spi_transfer *t)
 574 +{
 575 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 576 +       u8 bits_per_word = spi->bits_per_word;
 577 +
 578 +       hw->curr_transfer = t;
 579 +
 580 +       if (t && t->bits_per_word)
 581 +               bits_per_word = t->bits_per_word;
 582 +
 583 +       if (bits_per_word > 32)
 584 +               return -EINVAL;
 585 +
 586 +       ltq_spi_config_mode_set(hw);
 587 +
 588 +       return 0;
 589 +}
 590 +
 591 +static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
 592 +       { 15, 1, 0 },
 593 +       { 22, 1, 0 },
 594 +       { 13, 0, 1 },
 595 +       { 10, 0, 1 },
 596 +       {  9, 0, 1 },
 597 +       { 11, 1, 1 },
 598 +};
 599 +
 600 +static int ltq_spi_setup(struct spi_device *spi)
 601 +{
 602 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 603 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 604 +       struct ltq_spi_controller_state *cstate;
 605 +       u32 gpocon, fgpo;
 606 +       int ret;
 607 +
 608 +       /* Set default word length to 8 if not set */
 609 +       if (!spi->bits_per_word)
 610 +               spi->bits_per_word = 8;
 611 +
 612 +       if (spi->bits_per_word > 32)
 613 +               return -EINVAL;
 614 +
 615 +       if (!spi->controller_state) {
 616 +               cstate = kzalloc(sizeof(struct ltq_spi_controller_state),
 617 +                                GFP_KERNEL);
 618 +               if (!cstate)
 619 +                       return -ENOMEM;
 620 +
 621 +               spi->controller_state = cstate;
 622 +       } else
 623 +               return 0;
 624 +
 625 +       /*
 626 +        * Up to six GPIOs can be connected to the SPI module
 627 +        * via GPIO alternate function to control the chip select lines.
 628 +        * For more flexibility in board layout this driver can also control
 629 +        * the CS lines via GPIO API. If GPIOs should be used, board setup code
 630 +        * have to register the SPI device with struct ltq_spi_controller_data
 631 +        * attached.
 632 +        */
 633 +       if (cdata && cdata->gpio) {
 634 +               ret = gpio_request(cdata->gpio, "spi-cs");
 635 +               if (ret)
 636 +                       return -EBUSY;
 637 +
 638 +               ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
 639 +               gpio_direction_output(cdata->gpio, ret);
 640 +
 641 +               cstate->cs_activate = ltq_spi_gpio_cs_activate;
 642 +               cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
 643 +       } else {
 644 +               ret = ltq_gpio_request(ltq_spi_cs[spi->chip_select].gpio,
 645 +                               ltq_spi_cs[spi->chip_select].altsel0,
 646 +                               ltq_spi_cs[spi->chip_select].altsel1,
 647 +                               1, "spi-cs");
 648 +               if (ret)
 649 +                       return -EBUSY;
 650 +
 651 +               gpocon = (1 << (spi->chip_select +
 652 +                               LTQ_SPI_GPOCON_ISCSBN_SHIFT));
 653 +
 654 +               if (spi->mode & SPI_CS_HIGH)
 655 +                       gpocon |= (1 << spi->chip_select);
 656 +
 657 +               fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 658 +
 659 +               ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
 660 +               ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 661 +
 662 +               cstate->cs_activate = ltq_spi_internal_cs_activate;
 663 +               cstate->cs_deactivate = ltq_spi_internal_cs_deactivate;
 664 +       }
 665 +
 666 +       return 0;
 667 +}
 668 +
 669 +static void ltq_spi_cleanup(struct spi_device *spi)
 670 +{
 671 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 672 +       struct ltq_spi_controller_state *cstate = spi->controller_state;
 673 +       unsigned gpio;
 674 +
 675 +       if (cdata && cdata->gpio)
 676 +               gpio = cdata->gpio;
 677 +       else
 678 +               gpio = ltq_spi_cs[spi->chip_select].gpio;
 679 +
 680 +       gpio_free(gpio);
 681 +       kfree(cstate);
 682 +}
 683 +
 684 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
 685 +{
 686 +       u32 fstat, data;
 687 +       u16 fifo_space;
 688 +
 689 +       /* Determine how much FIFOs are free for TX data */
 690 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 691 +       fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
 692 +                                       LTQ_SPI_FSTAT_TXFFL_MASK);
 693 +
 694 +       if (!fifo_space)
 695 +               return;
 696 +
 697 +       while (hw->tx_cnt < hw->len && fifo_space) {
 698 +               data = hw->get_tx(hw);
 699 +               ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
 700 +               fifo_space--;
 701 +       }
 702 +}
 703 +
 704 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
 705 +{
 706 +       u32 fstat, data, *rx32;
 707 +       u16 fifo_fill;
 708 +       u8 rxbv, shift, *rx8;
 709 +
 710 +       /* Determine how much FIFOs are filled with RX data */
 711 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 712 +       fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
 713 +                       & LTQ_SPI_FSTAT_RXFFL_MASK);
 714 +
 715 +       if (!fifo_fill)
 716 +               return;
 717 +
 718 +       /*
 719 +        * The 32 bit FIFO is always used completely independent from the
 720 +        * bits_per_word value. Thus four bytes have to be read at once
 721 +        * per FIFO.
 722 +        */
 723 +       rx32 = (u32 *) hw->rx;
 724 +       while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
 725 +               *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 726 +               hw->rx_cnt += 4;
 727 +               hw->rx += 4;
 728 +               fifo_fill--;
 729 +       }
 730 +
 731 +       /*
 732 +        * If there are remaining bytes, read byte count from STAT.RXBV
 733 +        * register and read the data byte-wise.
 734 +        */
 735 +       while (fifo_fill && hw->rx_cnt < hw->len) {
 736 +               rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
 737 +                       LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
 738 +               data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 739 +
 740 +               shift = (rxbv - 1) * 8;
 741 +               rx8 = hw->rx;
 742 +
 743 +               while (rxbv) {
 744 +                       *rx8++ = (data >> shift) & 0xFF;
 745 +                       rxbv--;
 746 +                       shift -= 8;
 747 +                       hw->rx_cnt++;
 748 +                       hw->rx++;
 749 +               }
 750 +
 751 +               fifo_fill--;
 752 +       }
 753 +}
 754 +
 755 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
 756 +{
 757 +       u32 rxreq, rxreq_max, rxtodo;
 758 +
 759 +       rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
 760 +
 761 +       /*
 762 +        * In RX-only mode the serial clock is activated only after writing
 763 +        * the expected amount of RX bytes into RXREQ register.
 764 +        * To avoid receive overflows at high clocks it is better to request
 765 +        * only the amount of bytes that fits into all FIFOs. This value
 766 +        * depends on the FIFO size implemented in hardware.
 767 +        */
 768 +       rxreq = hw->len - hw->rx_cnt;
 769 +       rxreq_max = hw->rxfs << 2;
 770 +       rxreq = min(rxreq_max, rxreq);
 771 +
 772 +       if (!rxtodo && rxreq)
 773 +               ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
 774 +}
 775 +
 776 +static inline void ltq_spi_complete(struct ltq_spi *hw)
 777 +{
 778 +       complete(&hw->done);
 779 +}
 780 +
 781 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
 782 +{
 783 +       struct ltq_spi *hw = data;
 784 +       unsigned long flags;
 785 +       int completed = 0;
 786 +
 787 +       spin_lock_irqsave(&hw->lock, flags);
 788 +
 789 +       if (hw->tx_cnt < hw->len)
 790 +               ltq_spi_txfifo_write(hw);
 791 +
 792 +       if (hw->tx_cnt == hw->len)
 793 +               completed = 1;
 794 +
 795 +       spin_unlock_irqrestore(&hw->lock, flags);
 796 +
 797 +       if (completed)
 798 +               ltq_spi_complete(hw);
 799 +
 800 +       return IRQ_HANDLED;
 801 +}
 802 +
 803 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
 804 +{
 805 +       struct ltq_spi *hw = data;
 806 +       unsigned long flags;
 807 +       int completed = 0;
 808 +
 809 +       spin_lock_irqsave(&hw->lock, flags);
 810 +
 811 +       if (hw->rx_cnt < hw->len) {
 812 +               ltq_spi_rxfifo_read(hw);
 813 +
 814 +               if (hw->tx && hw->tx_cnt < hw->len)
 815 +                       ltq_spi_txfifo_write(hw);
 816 +       }
 817 +
 818 +       if (hw->rx_cnt == hw->len)
 819 +               completed = 1;
 820 +       else if (!hw->tx)
 821 +               ltq_spi_rxreq_set(hw);
 822 +
 823 +       spin_unlock_irqrestore(&hw->lock, flags);
 824 +
 825 +       if (completed)
 826 +               ltq_spi_complete(hw);
 827 +
 828 +       return IRQ_HANDLED;
 829 +}
 830 +
 831 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
 832 +{
 833 +       struct ltq_spi *hw = data;
 834 +       unsigned long flags;
 835 +
 836 +       spin_lock_irqsave(&hw->lock, flags);
 837 +
 838 +       /* Disable all interrupts */
 839 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 840 +
 841 +       /* Clear all error flags */
 842 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 843 +
 844 +       /* Flush FIFOs */
 845 +       ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
 846 +       ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
 847 +
 848 +       hw->status = -EIO;
 849 +       spin_unlock_irqrestore(&hw->lock, flags);
 850 +
 851 +       ltq_spi_complete(hw);
 852 +
 853 +       return IRQ_HANDLED;
 854 +}
 855 +
 856 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 857 +{
 858 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 859 +       u32 irq_flags = 0;
 860 +
 861 +       hw->tx = t->tx_buf;
 862 +       hw->rx = t->rx_buf;
 863 +       hw->len = t->len;
 864 +       hw->tx_cnt = 0;
 865 +       hw->rx_cnt = 0;
 866 +       hw->status = 0;
 867 +       INIT_COMPLETION(hw->done);
 868 +
 869 +       ltq_spi_xmit_set(hw, t);
 870 +
 871 +       /* Enable error interrupts */
 872 +       ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
 873 +
 874 +       if (hw->tx) {
 875 +               /* Initially fill TX FIFO with as much data as possible */
 876 +               ltq_spi_txfifo_write(hw);
 877 +               irq_flags |= LTQ_SPI_IRNEN_T;
 878 +
 879 +               /* Always enable RX interrupt in Full Duplex mode */
 880 +               if (hw->rx)
 881 +                       irq_flags |= LTQ_SPI_IRNEN_R;
 882 +       } else if (hw->rx) {
 883 +               /* Start RX clock */
 884 +               ltq_spi_rxreq_set(hw);
 885 +
 886 +               /* Enable RX interrupt to receive data from RX FIFOs */
 887 +               irq_flags |= LTQ_SPI_IRNEN_R;
 888 +       }
 889 +
 890 +       /* Enable TX or RX interrupts */
 891 +       ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
 892 +       wait_for_completion_interruptible(&hw->done);
 893 +
 894 +       /* Disable all interrupts */
 895 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 896 +
 897 +       /*
 898 +        * Return length of current transfer for bitbang utility code if
 899 +        * no errors occured during transmission.
 900 +        */
 901 +       if (!hw->status)
 902 +               hw->status = hw->len;
 903 +
 904 +       return hw->status;
 905 +}
 906 +
 907 +static const struct ltq_spi_irq_map ltq_spi_irqs[] = {
 908 +       { "spi_tx", ltq_spi_tx_irq },
 909 +       { "spi_rx", ltq_spi_rx_irq },
 910 +       { "spi_err", ltq_spi_err_irq },
 911 +};
 912 +
 913 +static int __init ltq_spi_probe(struct platform_device *pdev)
 914 +{
 915 +       struct spi_master *master;
 916 +       struct resource *r;
 917 +       struct ltq_spi *hw;
 918 +       struct ltq_spi_platform_data *pdata = pdev->dev.platform_data;
 919 +       int ret, i;
 920 +       u32 data, id;
 921 +
 922 +       master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
 923 +       if (!master) {
 924 +               dev_err(&pdev->dev, "spi_alloc_master\n");
 925 +               ret = -ENOMEM;
 926 +               goto err;
 927 +       }
 928 +
 929 +       hw = spi_master_get_devdata(master);
 930 +
 931 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 932 +       if (r == NULL) {
 933 +               dev_err(&pdev->dev, "platform_get_resource\n");
 934 +               ret = -ENOENT;
 935 +               goto err_master;
 936 +       }
 937 +
 938 +       r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 939 +                       pdev->name);
 940 +       if (!r) {
 941 +               dev_err(&pdev->dev, "devm_request_mem_region\n");
 942 +               ret = -ENXIO;
 943 +               goto err_master;
 944 +       }
 945 +
 946 +       hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
 947 +       if (!hw->base) {
 948 +               dev_err(&pdev->dev, "devm_ioremap_nocache\n");
 949 +               ret = -ENXIO;
 950 +               goto err_master;
 951 +       }
 952 +
 953 +       hw->clk = clk_get(&pdev->dev, "fpi");
 954 +       if (IS_ERR(hw->clk)) {
 955 +               dev_err(&pdev->dev, "clk_get\n");
 956 +               ret = PTR_ERR(hw->clk);
 957 +               goto err_master;
 958 +       }
 959 +
 960 +       memset(hw->irq, 0, sizeof(hw->irq));
 961 +       for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
 962 +               ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name);
 963 +               if (0 > ret) {
 964 +                       dev_err(&pdev->dev, "platform_get_irq_byname\n");
 965 +                       goto err_irq;
 966 +               }
 967 +
 968 +               hw->irq[i] = ret;
 969 +               ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
 970 +                                 0, ltq_spi_irqs[i].name, hw);
 971 +               if (ret) {
 972 +                       dev_err(&pdev->dev, "request_irq\n");
 973 +                       goto err_irq;
 974 +               }
 975 +       }
 976 +
 977 +       hw->bitbang.master = spi_master_get(master);
 978 +       hw->bitbang.chipselect = ltq_spi_chipselect;
 979 +       hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
 980 +       hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
 981 +
 982 +       master->bus_num = pdev->id;
 983 +       master->num_chipselect = pdata->num_chipselect;
 984 +       master->setup = ltq_spi_setup;
 985 +       master->cleanup = ltq_spi_cleanup;
 986 +
 987 +       hw->dev = &pdev->dev;
 988 +       init_completion(&hw->done);
 989 +       spin_lock_init(&hw->lock);
 990 +
 991 +       /* Set GPIO alternate functions to SPI */
 992 +       ltq_gpio_request(LTQ_SPI_GPIO_DI, 1, 0, 0, "spi-di");
 993 +       ltq_gpio_request(LTQ_SPI_GPIO_DO, 1, 0, 1, "spi-do");
 994 +       ltq_gpio_request(LTQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk");
 995 +
 996 +       ltq_spi_hw_enable(hw);
 997 +
 998 +       /* Read module capabilities */
 999 +       id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
1000 +       hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1001 +       hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1002 +       hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
1003 +
1004 +       ltq_spi_config_mode_set(hw);
1005 +
1006 +       /* Enable error checking, disable TX/RX, set idle value high */
1007 +       data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
1008 +           LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
1009 +           LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
1010 +       ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
1011 +
1012 +       /* Enable master mode and clear error flags */
1013 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
1014 +                         LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
1015 +
1016 +       /* Reset GPIO/CS registers */
1017 +       ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
1018 +       ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
1019 +
1020 +       /* Enable and flush FIFOs */
1021 +       ltq_spi_reset_fifos(hw);
1022 +
1023 +       ret = spi_bitbang_start(&hw->bitbang);
1024 +       if (ret) {
1025 +               dev_err(&pdev->dev, "spi_bitbang_start\n");
1026 +               goto err_bitbang;
1027 +       }
1028 +
1029 +       platform_set_drvdata(pdev, hw);
1030 +
1031 +       pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
1032 +               id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
1033 +
1034 +       return 0;
1035 +
1036 +err_bitbang:
1037 +       ltq_spi_hw_disable(hw);
1038 +
1039 +err_irq:
1040 +       clk_put(hw->clk);
1041 +
1042 +       for (; i > 0; i--)
1043 +               free_irq(hw->irq[i], hw);
1044 +
1045 +err_master:
1046 +       spi_master_put(master);
1047 +
1048 +err:
1049 +       return ret;
1050 +}
1051 +
1052 +static int __exit ltq_spi_remove(struct platform_device *pdev)
1053 +{
1054 +       struct ltq_spi *hw = platform_get_drvdata(pdev);
1055 +       int ret, i;
1056 +
1057 +       ret = spi_bitbang_stop(&hw->bitbang);
1058 +       if (ret)
1059 +               return ret;
1060 +
1061 +       platform_set_drvdata(pdev, NULL);
1062 +
1063 +       ltq_spi_config_mode_set(hw);
1064 +       ltq_spi_hw_disable(hw);
1065 +
1066 +       for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
1067 +               if (0 < hw->irq[i])
1068 +                       free_irq(hw->irq[i], hw);
1069 +
1070 +       gpio_free(LTQ_SPI_GPIO_DI);
1071 +       gpio_free(LTQ_SPI_GPIO_DO);
1072 +       gpio_free(LTQ_SPI_GPIO_CLK);
1073 +
1074 +       clk_put(hw->clk);
1075 +       spi_master_put(hw->bitbang.master);
1076 +
1077 +       return 0;
1078 +}
1079 +
1080 +static struct platform_driver ltq_spi_driver = {
1081 +       .driver = {
1082 +                  .name = "ltq-spi",
1083 +                  .owner = THIS_MODULE,
1084 +                  },
1085 +       .remove = __exit_p(ltq_spi_remove),
1086 +};
1087 +
1088 +static int __init ltq_spi_init(void)
1089 +{
1090 +       return platform_driver_probe(&ltq_spi_driver, ltq_spi_probe);
1091 +}
1092 +module_init(ltq_spi_init);
1093 +
1094 +static void __exit ltq_spi_exit(void)
1095 +{
1096 +       platform_driver_unregister(&ltq_spi_driver);
1097 +}
1098 +module_exit(ltq_spi_exit);
1099 +
1100 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1101 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1102 +MODULE_LICENSE("GPL");
1103 +MODULE_ALIAS("platform:ltq-spi");