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rtl8366_smi: move RTL8366S driver into a separate file
[openwrt.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366s.h>
21
22 #include "rtl8366_smi.h"
23
24 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
29 #define RTL8366S_DRIVER_VER "0.2.0"
30
31 #define RTL8366S_PHY_NO_MAX 4
32 #define RTL8366S_PHY_PAGE_MAX 7
33 #define RTL8366S_PHY_ADDR_MAX 31
34
35 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
36 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0105
45 #define RTL8366S_CHIP_ID_8366 0x8366
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0420
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0421
66 #define RTL8366_LED_0_1_CTRL_REG 0x0422
67 #define RTL8366_LED_2_3_CTRL_REG 0x0423
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x11F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s {
150 struct device *parent;
151 struct rtl8366_smi smi;
152 struct mii_bus *mii_bus;
153 int mii_irq[PHY_MAX_ADDR];
154 struct switch_dev dev;
155 char buf[4096];
156 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
157 struct dentry *debugfs_root;
158 #endif
159 };
160
161 struct rtl8366s_vlanconfig {
162 u16 reserved2:1;
163 u16 priority:3;
164 u16 vid:12;
165
166 u16 reserved1:1;
167 u16 fid:3;
168 u16 untag:6;
169 u16 member:6;
170 };
171
172 struct rtl8366s_vlan4kentry {
173 u16 reserved1:4;
174 u16 vid:12;
175
176 u16 reserved2:1;
177 u16 fid:3;
178 u16 untag:6;
179 u16 member:6;
180 };
181
182 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
183 u16 g_dbg_reg;
184 #endif
185
186 static const char *MIBCOUNTERS[] = {
187 "IfInOctets ",
188 "EtherStatsOctets ",
189 "EtherStatsUnderSizePkts ",
190 "EtherFregament ",
191 "EtherStatsPkts64Octets ",
192 "EtherStatsPkts65to127Octets ",
193 "EtherStatsPkts128to255Octets ",
194 "EtherStatsPkts256to511Octets ",
195 "EtherStatsPkts512to1023Octets ",
196 "EtherStatsPkts1024to1518Octets ",
197 "EtherOversizeStats ",
198 "EtherStatsJabbers ",
199 "IfInUcastPkts ",
200 "EtherStatsMulticastPkts ",
201 "EtherStatsBroadcastPkts ",
202 "EtherStatsDropEvents ",
203 "Dot3StatsFCSErrors ",
204 "Dot3StatsSymbolErrors ",
205 "Dot3InPauseFrames ",
206 "Dot3ControlInUnknownOpcodes ",
207 "IfOutOctets ",
208 "Dot3StatsSingleCollisionFrames ",
209 "Dot3StatMultipleCollisionFrames ",
210 "Dot3sDeferredTransmissions ",
211 "Dot3StatsLateCollisions ",
212 "EtherStatsCollisions ",
213 "Dot3StatsExcessiveCollisions ",
214 "Dot3OutPauseFrames ",
215 "Dot1dBasePortDelayExceededDiscards",
216 "Dot1dTpPortInDiscards ",
217 "IfOutUcastPkts ",
218 "IfOutMulticastPkts ",
219 "IfOutBroadcastPkts ",
220 NULL,
221 };
222
223 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
224 {
225 return container_of(sw, struct rtl8366s, dev);
226 }
227
228 static int rtl8366s_read_phy_reg(struct rtl8366s *rtl,
229 u32 phy_no, u32 page, u32 addr, u32 *data)
230 {
231 struct rtl8366_smi *smi = &rtl->smi;
232 u32 reg;
233 int ret;
234
235 if (phy_no > RTL8366S_PHY_NO_MAX)
236 return -EINVAL;
237
238 if (page > RTL8366S_PHY_PAGE_MAX)
239 return -EINVAL;
240
241 if (addr > RTL8366S_PHY_ADDR_MAX)
242 return -EINVAL;
243
244 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
245 RTL8366S_PHY_CTRL_READ);
246 if (ret)
247 return ret;
248
249 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
250 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
251 (addr & RTL8366S_PHY_REG_MASK);
252
253 ret = rtl8366_smi_write_reg(smi, reg, 0);
254 if (ret)
255 return ret;
256
257 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
258 if (ret)
259 return ret;
260
261 return 0;
262 }
263
264 static int rtl8366s_write_phy_reg(struct rtl8366s *rtl,
265 u32 phy_no, u32 page, u32 addr, u32 data)
266 {
267 struct rtl8366_smi *smi = &rtl->smi;
268 u32 reg;
269 int ret;
270
271 if (phy_no > RTL8366S_PHY_NO_MAX)
272 return -EINVAL;
273
274 if (page > RTL8366S_PHY_PAGE_MAX)
275 return -EINVAL;
276
277 if (addr > RTL8366S_PHY_ADDR_MAX)
278 return -EINVAL;
279
280 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
281 RTL8366S_PHY_CTRL_WRITE);
282 if (ret)
283 return ret;
284
285 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
286 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
287 (addr & RTL8366S_PHY_REG_MASK);
288
289 ret = rtl8366_smi_write_reg(smi, reg, data);
290 if (ret)
291 return ret;
292
293 return 0;
294 }
295
296 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
297 int port, unsigned long long *val)
298 {
299 struct rtl8366_smi *smi = &rtl->smi;
300 int i;
301 int err;
302 u32 addr, data, regoffset;
303 u64 mibvalue;
304
305 /* address offset to MIBs counter */
306 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
307 2, 2, 2, 2, 2, 2, 2, 2, 2,
308 2, 2, 4, 2, 2, 2, 2, 2, 2,
309 2, 2, 2, 2, 2, 2};
310
311 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
312 return -EINVAL;
313
314 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
315
316 for (i = 0; i < counter; i++)
317 regoffset += mibLength[i];
318
319 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
320
321 /*
322 * Writing access counter address first
323 * then ASIC will prepare 64bits counter wait for being retrived
324 */
325 data = 0; /* writing data will be discard by ASIC */
326 err = rtl8366_smi_write_reg(smi, addr, data);
327 if (err)
328 return err;
329
330 /* read MIB control register */
331 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
332 if (err)
333 return err;
334
335 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
336 return -EBUSY;
337
338 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
339 return -EIO;
340
341 mibvalue = 0;
342 addr = addr + mibLength[counter] - 1;
343 i = mibLength[counter];
344
345 while (i) {
346 err = rtl8366_smi_read_reg(smi, addr, &data);
347 if (err)
348 return err;
349
350 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
351
352 addr--;
353 i--;
354 }
355
356 *val = mibvalue;
357 return 0;
358 }
359
360 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
361 struct rtl8366s_vlan4kentry *vlan4k)
362 {
363 struct rtl8366_smi *smi = &rtl->smi;
364 int err;
365 u32 data;
366 u16 *tableaddr;
367
368 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
369 vlan4k->vid = vid;
370
371 if (vid >= RTL8366_NUM_VIDS)
372 return -EINVAL;
373
374 tableaddr = (u16 *)vlan4k;
375
376 /* write VID */
377 data = *tableaddr;
378 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
379 if (err)
380 return err;
381
382 /* write table access control word */
383 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
384 RTL8366S_TABLE_VLAN_READ_CTRL);
385 if (err)
386 return err;
387
388 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
389 if (err)
390 return err;
391
392 *tableaddr = data;
393 tableaddr++;
394
395 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
396 &data);
397 if (err)
398 return err;
399
400 *tableaddr = data;
401 vlan4k->vid = vid;
402
403 return 0;
404 }
405
406 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
407 const struct rtl8366s_vlan4kentry *vlan4k)
408 {
409 struct rtl8366_smi *smi = &rtl->smi;
410 int err;
411 u32 data;
412 u16 *tableaddr;
413
414 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
415 vlan4k->member > RTL8366_PORT_ALL ||
416 vlan4k->untag > RTL8366_PORT_ALL ||
417 vlan4k->fid > RTL8366S_FIDMAX)
418 return -EINVAL;
419
420 tableaddr = (u16 *)vlan4k;
421
422 data = *tableaddr;
423
424 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
425 if (err)
426 return err;
427
428 tableaddr++;
429
430 data = *tableaddr;
431
432 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
433 data);
434 if (err)
435 return err;
436
437 /* write table access control word */
438 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
439 RTL8366S_TABLE_VLAN_WRITE_CTRL);
440
441 return err;
442 }
443
444 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
445 struct rtl8366s_vlanconfig *vlanmc)
446 {
447 struct rtl8366_smi *smi = &rtl->smi;
448 int err;
449 u32 addr;
450 u32 data;
451 u16 *tableaddr;
452
453 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
454
455 if (index >= RTL8366_NUM_VLANS)
456 return -EINVAL;
457
458 tableaddr = (u16 *)vlanmc;
459
460 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
461 err = rtl8366_smi_read_reg(smi, addr, &data);
462 if (err)
463 return err;
464
465 *tableaddr = data;
466 tableaddr++;
467
468 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
469 err = rtl8366_smi_read_reg(smi, addr, &data);
470 if (err)
471 return err;
472
473 *tableaddr = data;
474
475 return 0;
476 }
477
478 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
479 const struct rtl8366s_vlanconfig
480 *vlanmc)
481 {
482 struct rtl8366_smi *smi = &rtl->smi;
483 int err;
484 u32 addr;
485 u32 data;
486 u16 *tableaddr;
487
488 if (index >= RTL8366_NUM_VLANS ||
489 vlanmc->vid >= RTL8366_NUM_VIDS ||
490 vlanmc->priority > RTL8366S_PRIORITYMAX ||
491 vlanmc->member > RTL8366_PORT_ALL ||
492 vlanmc->untag > RTL8366_PORT_ALL ||
493 vlanmc->fid > RTL8366S_FIDMAX)
494 return -EINVAL;
495
496 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
497
498 tableaddr = (u16 *)vlanmc;
499 data = *tableaddr;
500
501 err = rtl8366_smi_write_reg(smi, addr, data);
502 if (err)
503 return err;
504
505 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
506
507 tableaddr++;
508 data = *tableaddr;
509
510 err = rtl8366_smi_write_reg(smi, addr, data);
511 if (err)
512 return err;
513
514 return 0;
515 }
516
517 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
518 int *val)
519 {
520 struct rtl8366_smi *smi = &rtl->smi;
521 u32 data;
522 int err;
523
524 if (port >= RTL8366_NUM_PORTS)
525 return -EINVAL;
526
527 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
528 &data);
529 if (err)
530 return err;
531
532 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
533 RTL8366S_PORT_VLAN_CTRL_MASK;
534
535 return 0;
536
537 }
538
539 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
540 int *val)
541 {
542 struct rtl8366s_vlanconfig vlanmc;
543 int err;
544 int index;
545
546 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
547 if (err)
548 return err;
549
550 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
551 if (err)
552 return err;
553
554 *val = vlanmc.vid;
555 return 0;
556 }
557
558 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
559 int index)
560 {
561 struct rtl8366_smi *smi = &rtl->smi;
562 u32 data;
563 int err;
564
565 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
566 return -EINVAL;
567
568 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
569 &data);
570 if (err)
571 return err;
572
573 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
574 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
575 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
576 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
577
578 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
579 data);
580 return err;
581 }
582
583 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
584 {
585 int i;
586 struct rtl8366s_vlanconfig vlanmc;
587 struct rtl8366s_vlan4kentry vlan4k;
588
589 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
590 return -EINVAL;
591
592 /* Updating the 4K entry; lookup it and change the port member set */
593 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
594 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
595 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
596 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
597
598 /*
599 * For the 16 entries more work needs to be done. First see if such
600 * VID is already there and change it
601 */
602 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
603 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
604
605 /* Try to find an existing vid and update port member set */
606 if (val == vlanmc.vid) {
607 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
608 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
609
610 /* Now update PVID register settings */
611 rtl8366s_set_port_vlan_index(rtl, port, i);
612
613 return 0;
614 }
615 }
616
617 /*
618 * PVID could not be found from vlan table. Replace unused (one that
619 * has no member ports) with new one
620 */
621 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
622 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
623
624 /*
625 * See if this vlan member configuration is unused. It is
626 * unused if member set contains no ports or CPU port only
627 */
628 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
629 vlanmc.vid = val;
630 vlanmc.priority = 0;
631 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
632 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
633 vlanmc.fid = 0;
634
635 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
636
637 /* Now update PVID register settings */
638 rtl8366s_set_port_vlan_index(rtl, port, i);
639
640 return 0;
641 }
642 }
643
644 dev_err(rtl->parent,
645 "All 16 vlan member configurations are in use\n");
646
647 return -EINVAL;
648 }
649
650
651 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
652 {
653 struct rtl8366_smi *smi = &rtl->smi;
654 u32 data = 0;
655
656 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
657
658 if (enable)
659 data |= RTL8366_CHIP_CTRL_VLAN;
660 else
661 data &= ~RTL8366_CHIP_CTRL_VLAN;
662
663 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
664 }
665
666 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
667 {
668 struct rtl8366_smi *smi = &rtl->smi;
669 u32 data = 0;
670
671 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
672
673 if (enable)
674 data |= 1;
675 else
676 data &= ~1;
677
678 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
679 }
680
681 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
682 {
683 struct rtl8366s_vlan4kentry vlan4k;
684 struct rtl8366s_vlanconfig vlanmc;
685 int err;
686 int i;
687
688 /* clear 16 VLAN member configuration */
689 vlanmc.vid = 0;
690 vlanmc.priority = 0;
691 vlanmc.member = 0;
692 vlanmc.untag = 0;
693 vlanmc.fid = 0;
694 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
695 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
696 if (err)
697 return err;
698 }
699
700 /* Set a default VLAN with vid 1 to 4K table for all ports */
701 vlan4k.vid = 1;
702 vlan4k.member = RTL8366_PORT_ALL;
703 vlan4k.untag = RTL8366_PORT_ALL;
704 vlan4k.fid = 0;
705 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
706 if (err)
707 return err;
708
709 /* Set all ports PVID to default VLAN */
710 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
711 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
712 if (err)
713 return err;
714 }
715
716 return 0;
717 }
718
719 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
720 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
721 {
722 file->private_data = inode->i_private;
723 return 0;
724 }
725
726 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
727 char __user *user_buf,
728 size_t count, loff_t *ppos)
729 {
730 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
731 int i, j, len = 0;
732 char *buf = rtl->buf;
733
734 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
735 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
736 " "
737 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
738 "Port 4\n");
739
740 for (i = 0; i < 33; ++i) {
741 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
742 i, MIBCOUNTERS[i]);
743 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
744 unsigned long long counter = 0;
745
746 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
747 len += snprintf(buf + len,
748 sizeof(rtl->buf) - len,
749 "[%llu]", counter);
750 else
751 len += snprintf(buf + len,
752 sizeof(rtl->buf) - len,
753 "[error]");
754
755 if (j != RTL8366_NUM_PORTS - 1) {
756 if (counter < 100000)
757 len += snprintf(buf + len,
758 sizeof(rtl->buf) - len,
759 "\t");
760
761 len += snprintf(buf + len,
762 sizeof(rtl->buf) - len,
763 "\t");
764 }
765 }
766 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
767 }
768
769 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
770
771 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
772 }
773
774 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
775 char __user *user_buf,
776 size_t count, loff_t *ppos)
777 {
778 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
779 int i, j, len = 0;
780 char *buf = rtl->buf;
781
782 len += snprintf(buf + len, sizeof(rtl->buf) - len,
783 "VLAN Member Config:\n");
784 len += snprintf(buf + len, sizeof(rtl->buf) - len,
785 "\t id \t vid \t prio \t member \t untag \t fid "
786 "\tports\n");
787
788 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
789 struct rtl8366s_vlanconfig vlanmc;
790
791 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
792
793 len += snprintf(buf + len, sizeof(rtl->buf) - len,
794 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
795 "\t", i, vlanmc.vid, vlanmc.priority,
796 vlanmc.member, vlanmc.untag, vlanmc.fid);
797
798 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
799 int index = 0;
800 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
801 if (index == i)
802 len += snprintf(buf + len,
803 sizeof(rtl->buf) - len,
804 "%d", j);
805 }
806 }
807 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
808 }
809
810 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
811 }
812
813 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
814 char __user *user_buf,
815 size_t count, loff_t *ppos)
816 {
817 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
818 struct rtl8366_smi *smi = &rtl->smi;
819 u32 t, reg = g_dbg_reg;
820 int err, len = 0;
821 char *buf = rtl->buf;
822
823 memset(buf, '\0', sizeof(rtl->buf));
824
825 err = rtl8366_smi_read_reg(smi, reg, &t);
826 if (err) {
827 len += snprintf(buf, sizeof(rtl->buf),
828 "Read failed (reg: 0x%04x)\n", reg);
829 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
830 }
831
832 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
833 reg, t);
834
835 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
836 }
837
838 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
839 const char __user *user_buf,
840 size_t count, loff_t *ppos)
841 {
842 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
843 struct rtl8366_smi *smi = &rtl->smi;
844 unsigned long data;
845 u32 reg = g_dbg_reg;
846 int err;
847 size_t len;
848 char *buf = rtl->buf;
849
850 len = min(count, sizeof(rtl->buf) - 1);
851 if (copy_from_user(buf, user_buf, len)) {
852 dev_err(rtl->parent, "copy from user failed\n");
853 return -EFAULT;
854 }
855
856 buf[len] = '\0';
857 if (len > 0 && buf[len - 1] == '\n')
858 buf[len - 1] = '\0';
859
860
861 if (strict_strtoul(buf, 16, &data)) {
862 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
863 } else {
864 err = rtl8366_smi_write_reg(smi, reg, data);
865 if (err) {
866 dev_err(rtl->parent,
867 "writing reg 0x%04x val 0x%04lx failed\n",
868 reg, data);
869 }
870 }
871
872 return count;
873 }
874
875 static const struct file_operations fops_rtl8366s_regs = {
876 .read = rtl8366s_read_debugfs_reg,
877 .write = rtl8366s_write_debugfs_reg,
878 .open = rtl8366s_debugfs_open,
879 .owner = THIS_MODULE
880 };
881
882 static const struct file_operations fops_rtl8366s_vlan = {
883 .read = rtl8366s_read_debugfs_vlan,
884 .open = rtl8366s_debugfs_open,
885 .owner = THIS_MODULE
886 };
887
888 static const struct file_operations fops_rtl8366s_mibs = {
889 .read = rtl8366s_read_debugfs_mibs,
890 .open = rtl8366s_debugfs_open,
891 .owner = THIS_MODULE
892 };
893
894 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
895 {
896 struct dentry *node;
897 struct dentry *root;
898
899 if (!rtl->debugfs_root)
900 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
901
902 if (!rtl->debugfs_root) {
903 dev_err(rtl->parent, "Unable to create debugfs dir\n");
904 return;
905 }
906 root = rtl->debugfs_root;
907
908 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
909 if (!node) {
910 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
911 return;
912 }
913
914 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
915 &fops_rtl8366s_regs);
916 if (!node) {
917 dev_err(rtl->parent, "Creating debugfs file val failed\n");
918 return;
919 }
920
921 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
922 &fops_rtl8366s_vlan);
923 if (!node) {
924 dev_err(rtl->parent,
925 "Creating debugfs file vlan failed\n");
926 return;
927 }
928
929 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
930 &fops_rtl8366s_mibs);
931 if (!node) {
932 dev_err(rtl->parent,
933 "Creating debugfs file mibs failed\n");
934 return;
935 }
936 }
937
938 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
939 {
940 if (rtl->debugfs_root) {
941 debugfs_remove_recursive(rtl->debugfs_root);
942 rtl->debugfs_root = NULL;
943 }
944 }
945
946 #else
947 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
948 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
949 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
950
951 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
952 const struct switch_attr *attr,
953 struct switch_val *val)
954 {
955 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
956 struct rtl8366_smi *smi = &rtl->smi;
957 u32 data = 0;
958
959 if (val->value.i == 1) {
960 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
961 data |= (1 << 2);
962 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
963 }
964
965 return 0;
966 }
967
968 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
969 const struct switch_attr *attr,
970 struct switch_val *val)
971 {
972 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
973 struct rtl8366_smi *smi = &rtl->smi;
974 u32 data;
975
976 if (attr->ofs == 1) {
977 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
978
979 if (data & RTL8366_CHIP_CTRL_VLAN)
980 val->value.i = 1;
981 else
982 val->value.i = 0;
983 } else if (attr->ofs == 2) {
984 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
985
986 if (data & 0x0001)
987 val->value.i = 1;
988 else
989 val->value.i = 0;
990 }
991
992 return 0;
993 }
994
995 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
996 const struct switch_attr *attr,
997 struct switch_val *val)
998 {
999 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1000 struct rtl8366_smi *smi = &rtl->smi;
1001 u32 data;
1002
1003 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1004
1005 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1006
1007 return 0;
1008 }
1009
1010 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1013 {
1014 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1015 struct rtl8366_smi *smi = &rtl->smi;
1016 u32 data;
1017
1018 if (val->value.i >= 6)
1019 return -EINVAL;
1020
1021 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1022
1023 data &= ~RTL8366_LED_BLINKRATE_MASK;
1024 data |= val->value.i;
1025
1026 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1027
1028 return 0;
1029 }
1030
1031 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1032 const struct switch_attr *attr,
1033 struct switch_val *val)
1034 {
1035 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1036
1037 if (attr->ofs == 1)
1038 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1039 else
1040 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1041 }
1042
1043 static const char *rtl8366s_speed_str(unsigned speed)
1044 {
1045 switch (speed) {
1046 case 0:
1047 return "10baseT";
1048 case 1:
1049 return "100baseT";
1050 case 2:
1051 return "1000baseT";
1052 }
1053
1054 return "unknown";
1055 }
1056
1057 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1058 const struct switch_attr *attr,
1059 struct switch_val *val)
1060 {
1061 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1062 struct rtl8366_smi *smi = &rtl->smi;
1063 u32 len = 0, data = 0;
1064
1065 if (val->port_vlan >= RTL8366_NUM_PORTS)
1066 return -EINVAL;
1067
1068 memset(rtl->buf, '\0', sizeof(rtl->buf));
1069 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1070 (val->port_vlan / 2), &data);
1071
1072 if (val->port_vlan % 2)
1073 data = data >> 8;
1074
1075 len = snprintf(rtl->buf, sizeof(rtl->buf),
1076 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1077 val->port_vlan,
1078 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1079 rtl8366s_speed_str(data &
1080 RTL8366S_PORT_STATUS_SPEED_MASK),
1081 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1082 "full" : "half",
1083 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1084 "tx-pause ": "",
1085 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1086 "rx-pause " : "",
1087 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1088
1089 val->value.s = rtl->buf;
1090 val->len = len;
1091
1092 return 0;
1093 }
1094
1095 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1096 const struct switch_attr *attr,
1097 struct switch_val *val)
1098 {
1099 int i;
1100 u32 len = 0;
1101 struct rtl8366s_vlanconfig vlanmc;
1102 struct rtl8366s_vlan4kentry vlan4k;
1103 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1104 char *buf = rtl->buf;
1105
1106 if (val->port_vlan >= RTL8366_NUM_VLANS)
1107 return -EINVAL;
1108
1109 memset(buf, '\0', sizeof(rtl->buf));
1110
1111 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1112 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1113
1114 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1115 val->port_vlan);
1116
1117 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1118 int index = 0;
1119 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1120 index == val->port_vlan)
1121 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1122 "%d", i);
1123 }
1124 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1125
1126 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1127 "\t\t vid \t prio \t member \t untag \t fid\n");
1128 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1129 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1130 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1131 vlanmc.vid, vlanmc.priority, vlanmc.member,
1132 vlanmc.untag, vlanmc.fid);
1133 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1134 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1135 "%d \t \t 0x%04x \t 0x%04x \t %d",
1136 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1137
1138 val->value.s = buf;
1139 val->len = len;
1140
1141 return 0;
1142 }
1143
1144 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1145 const struct switch_attr *attr,
1146 struct switch_val *val)
1147 {
1148 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1149 struct rtl8366_smi *smi = &rtl->smi;
1150 u32 data = 0;
1151
1152 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1153 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1154 return -EINVAL;
1155
1156 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1157 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1158 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1159 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1160 } else {
1161 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1162 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1163 (val->value.i << (val->port_vlan * 4));
1164 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1165 }
1166
1167 return 0;
1168 }
1169
1170 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1171 const struct switch_attr *attr,
1172 struct switch_val *val)
1173 {
1174 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1175 struct rtl8366_smi *smi = &rtl->smi;
1176 u32 data = 0;
1177
1178 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1179 return -EINVAL;
1180
1181 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1182 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1183
1184 return 0;
1185 }
1186
1187 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1188 const struct switch_attr *attr,
1189 struct switch_val *val)
1190 {
1191 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1192 struct rtl8366_smi *smi = &rtl->smi;
1193 u32 data = 0;
1194
1195 if (val->port_vlan >= RTL8366_NUM_PORTS)
1196 return -EINVAL;
1197
1198 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1199 data |= (1 << (val->port_vlan + 3));
1200 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1201
1202 return 0;
1203 }
1204
1205 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1206 const struct switch_attr *attr,
1207 struct switch_val *val)
1208 {
1209 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1210 int i, len = 0;
1211 unsigned long long counter = 0;
1212 char *buf = rtl->buf;
1213
1214 if (val->port_vlan >= RTL8366_NUM_PORTS)
1215 return -EINVAL;
1216
1217 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1218 "Port %d MIB counters\n",
1219 val->port_vlan);
1220
1221 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1222 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1223 "%d:%s\t", i, MIBCOUNTERS[i]);
1224 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1225 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1226 "[%llu]\n", counter);
1227 else
1228 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1229 "[error]\n");
1230 }
1231
1232 val->value.s = buf;
1233 val->len = len;
1234 return 0;
1235 }
1236
1237 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1238 struct switch_val *val)
1239 {
1240 struct rtl8366s_vlanconfig vlanmc;
1241 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1242 struct switch_port *port;
1243 int i;
1244
1245 if (val->port_vlan >= RTL8366_NUM_VLANS)
1246 return -EINVAL;
1247
1248 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1249
1250 port = &val->value.ports[0];
1251 val->len = 0;
1252 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1253 if (!(vlanmc.member & BIT(i)))
1254 continue;
1255
1256 port->id = i;
1257 port->flags = (vlanmc.untag & BIT(i)) ?
1258 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1259 val->len++;
1260 port++;
1261 }
1262 return 0;
1263 }
1264
1265 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1266 struct switch_val *val)
1267 {
1268 struct rtl8366s_vlanconfig vlanmc;
1269 struct rtl8366s_vlan4kentry vlan4k;
1270 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1271 struct switch_port *port;
1272 int i;
1273
1274 if (val->port_vlan >= RTL8366_NUM_VLANS)
1275 return -EINVAL;
1276
1277 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1278 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1279
1280 vlanmc.untag = 0;
1281 vlanmc.member = 0;
1282
1283 port = &val->value.ports[0];
1284 for (i = 0; i < val->len; i++, port++) {
1285 vlanmc.member |= BIT(port->id);
1286
1287 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1288 vlanmc.untag |= BIT(port->id);
1289 }
1290
1291 vlan4k.member = vlanmc.member;
1292 vlan4k.untag = vlanmc.untag;
1293
1294 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1295 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1296 return 0;
1297 }
1298
1299 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1300 {
1301 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1302 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1303 }
1304
1305 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1306 {
1307 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1308 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1309 }
1310
1311 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1312 {
1313 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1314 struct rtl8366_smi *smi = &rtl->smi;
1315 int timeout = 10;
1316 u32 data;
1317
1318 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1319 RTL8366_CHIP_CTRL_RESET_HW);
1320 do {
1321 msleep(1);
1322 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1323 return -EIO;
1324
1325 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1326 break;
1327 } while (--timeout);
1328
1329 if (!timeout) {
1330 printk("Timeout waiting for the switch to reset\n");
1331 return -EIO;
1332 }
1333
1334 return rtl8366s_reset_vlan(rtl);
1335 }
1336
1337 static struct switch_attr rtl8366s_globals[] = {
1338 {
1339 .type = SWITCH_TYPE_INT,
1340 .name = "enable_vlan",
1341 .description = "Enable VLAN mode",
1342 .set = rtl8366s_sw_set_vlan_enable,
1343 .get = rtl8366s_sw_get_vlan_enable,
1344 .max = 1,
1345 .ofs = 1
1346 }, {
1347 .type = SWITCH_TYPE_INT,
1348 .name = "enable_vlan4k",
1349 .description = "Enable VLAN 4K mode",
1350 .set = rtl8366s_sw_set_vlan_enable,
1351 .get = rtl8366s_sw_get_vlan_enable,
1352 .max = 1,
1353 .ofs = 2
1354 }, {
1355 .type = SWITCH_TYPE_INT,
1356 .name = "reset_mibs",
1357 .description = "Reset all MIB counters",
1358 .set = rtl8366s_sw_reset_mibs,
1359 .get = NULL,
1360 .max = 1
1361 }, {
1362 .type = SWITCH_TYPE_INT,
1363 .name = "blinkrate",
1364 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1365 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1366 .set = rtl8366s_sw_set_blinkrate,
1367 .get = rtl8366s_sw_get_blinkrate,
1368 .max = 5
1369 },
1370 };
1371
1372 static struct switch_attr rtl8366s_port[] = {
1373 {
1374 .type = SWITCH_TYPE_STRING,
1375 .name = "link",
1376 .description = "Get port link information",
1377 .max = 1,
1378 .set = NULL,
1379 .get = rtl8366s_sw_get_port_link,
1380 }, {
1381 .type = SWITCH_TYPE_INT,
1382 .name = "reset_mib",
1383 .description = "Reset single port MIB counters",
1384 .max = 1,
1385 .set = rtl8366s_sw_reset_port_mibs,
1386 .get = NULL,
1387 }, {
1388 .type = SWITCH_TYPE_STRING,
1389 .name = "mib",
1390 .description = "Get MIB counters for port",
1391 .max = 33,
1392 .set = NULL,
1393 .get = rtl8366s_sw_get_port_mib,
1394 }, {
1395 .type = SWITCH_TYPE_INT,
1396 .name = "led",
1397 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1398 .max = 15,
1399 .set = rtl8366s_sw_set_port_led,
1400 .get = rtl8366s_sw_get_port_led,
1401 },
1402 };
1403
1404 static struct switch_attr rtl8366s_vlan[] = {
1405 {
1406 .type = SWITCH_TYPE_STRING,
1407 .name = "info",
1408 .description = "Get vlan information",
1409 .max = 1,
1410 .set = NULL,
1411 .get = rtl8366s_sw_get_vlan_info,
1412 },
1413 };
1414
1415 /* template */
1416 static struct switch_dev rtl8366_switch_dev = {
1417 .name = "RTL8366S",
1418 .cpu_port = RTL8366_PORT_NUM_CPU,
1419 .ports = RTL8366_NUM_PORTS,
1420 .vlans = RTL8366_NUM_VLANS,
1421 .attr_global = {
1422 .attr = rtl8366s_globals,
1423 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1424 },
1425 .attr_port = {
1426 .attr = rtl8366s_port,
1427 .n_attr = ARRAY_SIZE(rtl8366s_port),
1428 },
1429 .attr_vlan = {
1430 .attr = rtl8366s_vlan,
1431 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1432 },
1433
1434 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1435 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1436 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1437 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1438 .reset_switch = rtl8366s_sw_reset_switch,
1439 };
1440
1441 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1442 {
1443 struct switch_dev *dev = &rtl->dev;
1444 int err;
1445
1446 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1447 dev->priv = rtl;
1448 dev->devname = dev_name(rtl->parent);
1449
1450 err = register_switch(dev, NULL);
1451 if (err)
1452 dev_err(rtl->parent, "switch registration failed\n");
1453
1454 return err;
1455 }
1456
1457 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1458 {
1459 unregister_switch(&rtl->dev);
1460 }
1461
1462 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1463 {
1464 struct rtl8366s *rtl = bus->priv;
1465 u32 val = 0;
1466 int err;
1467
1468 err = rtl8366s_read_phy_reg(rtl, addr, 0, reg, &val);
1469 if (err)
1470 return 0xffff;
1471
1472 return val;
1473 }
1474
1475 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1476 {
1477 struct rtl8366s *rtl = bus->priv;
1478 u32 t;
1479 int err;
1480
1481 err = rtl8366s_write_phy_reg(rtl, addr, 0, reg, val);
1482 /* flush write */
1483 (void) rtl8366s_read_phy_reg(rtl, addr, 0, reg, &t);
1484
1485 return err;
1486 }
1487
1488 static int rtl8366s_mii_init(struct rtl8366s *rtl)
1489 {
1490 int ret;
1491 int i;
1492
1493 rtl->mii_bus = mdiobus_alloc();
1494 if (rtl->mii_bus == NULL) {
1495 ret = -ENOMEM;
1496 goto err;
1497 }
1498
1499 rtl->mii_bus->priv = (void *) rtl;
1500 rtl->mii_bus->name = "rtl8366-rtl";
1501 rtl->mii_bus->read = rtl8366s_mii_read;
1502 rtl->mii_bus->write = rtl8366s_mii_write;
1503 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1504 dev_name(rtl->parent));
1505 rtl->mii_bus->parent = rtl->parent;
1506 rtl->mii_bus->phy_mask = ~(0x1f);
1507 rtl->mii_bus->irq = rtl->mii_irq;
1508 for (i = 0; i < PHY_MAX_ADDR; i++)
1509 rtl->mii_irq[i] = PHY_POLL;
1510
1511 ret = mdiobus_register(rtl->mii_bus);
1512 if (ret)
1513 goto err_free;
1514
1515 return 0;
1516
1517 err_free:
1518 mdiobus_free(rtl->mii_bus);
1519 err:
1520 return ret;
1521 }
1522
1523 static void rtl8366s_mii_cleanup(struct rtl8366s *rtl)
1524 {
1525 mdiobus_unregister(rtl->mii_bus);
1526 mdiobus_free(rtl->mii_bus);
1527 }
1528
1529 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1530 {
1531 return (bus->read == rtl8366s_mii_read &&
1532 bus->write == rtl8366s_mii_write);
1533 }
1534
1535 static int rtl8366s_setup(struct rtl8366s *rtl)
1536 {
1537 struct rtl8366_smi *smi = &rtl->smi;
1538 u32 chip_id = 0;
1539 u32 chip_ver = 0;
1540 int ret;
1541
1542 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1543 if (ret) {
1544 dev_err(rtl->parent, "unable to read chip id\n");
1545 return ret;
1546 }
1547
1548 switch (chip_id) {
1549 case RTL8366S_CHIP_ID_8366:
1550 break;
1551 default:
1552 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1553 return -ENODEV;
1554 }
1555
1556 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1557 &chip_ver);
1558 if (ret) {
1559 dev_err(rtl->parent, "unable to read chip version\n");
1560 return ret;
1561 }
1562
1563 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1564 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1565
1566 rtl8366s_debugfs_init(rtl);
1567
1568 return 0;
1569 }
1570
1571 static int __init rtl8366s_probe(struct platform_device *pdev)
1572 {
1573 static int rtl8366_smi_version_printed;
1574 struct rtl8366s_platform_data *pdata;
1575 struct rtl8366s *rtl;
1576 struct rtl8366_smi *smi;
1577 int err;
1578
1579 if (!rtl8366_smi_version_printed++)
1580 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1581 " version " RTL8366S_DRIVER_VER"\n");
1582
1583 pdata = pdev->dev.platform_data;
1584 if (!pdata) {
1585 dev_err(&pdev->dev, "no platform data specified\n");
1586 err = -EINVAL;
1587 goto err_out;
1588 }
1589
1590 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1591 if (!rtl) {
1592 dev_err(&pdev->dev, "no memory for private data\n");
1593 err = -ENOMEM;
1594 goto err_out;
1595 }
1596
1597 rtl->parent = &pdev->dev;
1598
1599 smi = &rtl->smi;
1600 smi->parent = &pdev->dev;
1601 smi->gpio_sda = pdata->gpio_sda;
1602 smi->gpio_sck = pdata->gpio_sck;
1603
1604 err = rtl8366_smi_init(smi);
1605 if (err)
1606 goto err_free_rtl;
1607
1608 platform_set_drvdata(pdev, rtl);
1609
1610 err = rtl8366s_setup(rtl);
1611 if (err)
1612 goto err_clear_drvdata;
1613
1614 err = rtl8366s_mii_init(rtl);
1615 if (err)
1616 goto err_clear_drvdata;
1617
1618 err = rtl8366s_switch_init(rtl);
1619 if (err)
1620 goto err_mii_cleanup;
1621
1622 return 0;
1623
1624 err_mii_cleanup:
1625 rtl8366s_mii_cleanup(rtl);
1626 err_clear_drvdata:
1627 platform_set_drvdata(pdev, NULL);
1628 rtl8366_smi_cleanup(smi);
1629 err_free_rtl:
1630 kfree(rtl);
1631 err_out:
1632 return err;
1633 }
1634
1635 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1636 {
1637 if (!rtl8366s_mii_bus_match(phydev->bus))
1638 return -EINVAL;
1639
1640 return 0;
1641 }
1642
1643 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1644 {
1645 return 0;
1646 }
1647
1648 static struct phy_driver rtl8366s_phy_driver = {
1649 .phy_id = 0x001cc960,
1650 .name = "Realtek RTL8366S",
1651 .phy_id_mask = 0x1ffffff0,
1652 .features = PHY_GBIT_FEATURES,
1653 .config_aneg = rtl8366s_phy_config_aneg,
1654 .config_init = rtl8366s_phy_config_init,
1655 .read_status = genphy_read_status,
1656 .driver = {
1657 .owner = THIS_MODULE,
1658 },
1659 };
1660
1661 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1662 {
1663 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1664
1665 if (rtl) {
1666 rtl8366s_switch_cleanup(rtl);
1667 rtl8366s_debugfs_remove(rtl);
1668 rtl8366s_mii_cleanup(rtl);
1669 platform_set_drvdata(pdev, NULL);
1670 rtl8366_smi_cleanup(&rtl->smi);
1671 kfree(rtl);
1672 }
1673
1674 return 0;
1675 }
1676
1677 static struct platform_driver rtl8366s_driver = {
1678 .driver = {
1679 .name = RTL8366S_DRIVER_NAME,
1680 .owner = THIS_MODULE,
1681 },
1682 .probe = rtl8366s_probe,
1683 .remove = __devexit_p(rtl8366s_remove),
1684 };
1685
1686 static int __init rtl8366s_module_init(void)
1687 {
1688 int ret;
1689 ret = platform_driver_register(&rtl8366s_driver);
1690 if (ret)
1691 return ret;
1692
1693 ret = phy_driver_register(&rtl8366s_phy_driver);
1694 if (ret)
1695 goto err_platform_unregister;
1696
1697 return 0;
1698
1699 err_platform_unregister:
1700 platform_driver_unregister(&rtl8366s_driver);
1701 return ret;
1702 }
1703 module_init(rtl8366s_module_init);
1704
1705 static void __exit rtl8366s_module_exit(void)
1706 {
1707 phy_driver_unregister(&rtl8366s_phy_driver);
1708 platform_driver_unregister(&rtl8366s_driver);
1709 }
1710 module_exit(rtl8366s_module_exit);
1711
1712 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1713 MODULE_VERSION(RTL8366S_DRIVER_VER);
1714 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1715 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1716 MODULE_LICENSE("GPL v2");
1717 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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