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fix a typo in the compat-wireless build speedup patch
[openwrt.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From 8dff6729a634d7cf223679d9a29a3df77927540c Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Sat, 8 Aug 2009 23:47:53 +0200
4 Subject: [PATCH 2/3] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Luis, Mattias, Mark, Felix and Xose.
9
10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
14 Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
15 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
16 ---
17 drivers/net/wireless/rt2x00/Kconfig | 26 +
18 drivers/net/wireless/rt2x00/Makefile | 1 +
19 drivers/net/wireless/rt2x00/rt2800pci.c | 3243 +++++++++++++++++++++++++++++++
20 drivers/net/wireless/rt2x00/rt2800pci.h | 1929 ++++++++++++++++++
21 drivers/net/wireless/rt2x00/rt2x00.h | 6 +
22 5 files changed, 5205 insertions(+), 0 deletions(-)
23 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
24 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
25
26 --- a/drivers/net/wireless/rt2x00/Makefile
27 +++ b/drivers/net/wireless/rt2x00/Makefile
28 @@ -16,6 +16,7 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
29 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
30 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
31 obj-$(CONFIG_RT61PCI) += rt61pci.o
32 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
33 obj-$(CONFIG_RT2500USB) += rt2500usb.o
34 obj-$(CONFIG_RT73USB) += rt73usb.o
35 obj-$(CONFIG_RT2800USB) += rt2800usb.o
36 --- /dev/null
37 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
38 @@ -0,0 +1,3241 @@
39 +/*
40 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
41 + <http://rt2x00.serialmonkey.com>
42 +
43 + This program is free software; you can redistribute it and/or modify
44 + it under the terms of the GNU General Public License as published by
45 + the Free Software Foundation; either version 2 of the License, or
46 + (at your option) any later version.
47 +
48 + This program is distributed in the hope that it will be useful,
49 + but WITHOUT ANY WARRANTY; without even the implied warranty of
50 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
51 + GNU General Public License for more details.
52 +
53 + You should have received a copy of the GNU General Public License
54 + along with this program; if not, write to the
55 + Free Software Foundation, Inc.,
56 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
57 + */
58 +
59 +/*
60 + Module: rt2800pci
61 + Abstract: rt2800pci device specific routines.
62 + Supported chipsets: RT2800E & RT2800ED.
63 + */
64 +
65 +#include <linux/crc-ccitt.h>
66 +#include <linux/delay.h>
67 +#include <linux/etherdevice.h>
68 +#include <linux/init.h>
69 +#include <linux/kernel.h>
70 +#include <linux/module.h>
71 +#include <linux/pci.h>
72 +#include <linux/platform_device.h>
73 +#include <linux/eeprom_93cx6.h>
74 +
75 +#include "rt2x00.h"
76 +#include "rt2x00pci.h"
77 +#include "rt2x00soc.h"
78 +#include "rt2800pci.h"
79 +
80 +#ifdef CONFIG_RT2800PCI_PCI_MODULE
81 +#define CONFIG_RT2800PCI_PCI
82 +#endif
83 +
84 +#ifdef CONFIG_RT2800PCI_WISOC_MODULE
85 +#define CONFIG_RT2800PCI_WISOC
86 +#endif
87 +
88 +/*
89 + * Allow hardware encryption to be disabled.
90 + */
91 +static int modparam_nohwcrypt = 0;
92 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
93 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
94 +
95 +/*
96 + * Register access.
97 + * BBP and RF register require indirect register access,
98 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
99 + * These indirect registers work with busy bits,
100 + * and we will try maximal REGISTER_BUSY_COUNT times to access
101 + * the register while taking a REGISTER_BUSY_DELAY us delay
102 + * between each attampt. When the busy bit is still set at that time,
103 + * the access attempt is considered to have failed,
104 + * and we will print an error.
105 + */
106 +#define WAIT_FOR_BBP(__dev, __reg) \
107 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
108 +#define WAIT_FOR_RFCSR(__dev, __reg) \
109 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
110 +#define WAIT_FOR_RF(__dev, __reg) \
111 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
112 +#define WAIT_FOR_MCU(__dev, __reg) \
113 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
114 + H2M_MAILBOX_CSR_OWNER, (__reg))
115 +
116 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
117 + const unsigned int word, const u8 value)
118 +{
119 + u32 reg;
120 +
121 + mutex_lock(&rt2x00dev->csr_mutex);
122 +
123 + /*
124 + * Wait until the BBP becomes available, afterwards we
125 + * can safely write the new data into the register.
126 + */
127 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 + reg = 0;
129 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
130 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
131 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
132 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
133 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
134 +
135 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
136 + }
137 +
138 + mutex_unlock(&rt2x00dev->csr_mutex);
139 +}
140 +
141 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
142 + const unsigned int word, u8 *value)
143 +{
144 + u32 reg;
145 +
146 + mutex_lock(&rt2x00dev->csr_mutex);
147 +
148 + /*
149 + * Wait until the BBP becomes available, afterwards we
150 + * can safely write the read request into the register.
151 + * After the data has been written, we wait until hardware
152 + * returns the correct value, if at any time the register
153 + * doesn't become available in time, reg will be 0xffffffff
154 + * which means we return 0xff to the caller.
155 + */
156 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
157 + reg = 0;
158 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
159 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
160 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
161 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
162 +
163 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
164 +
165 + WAIT_FOR_BBP(rt2x00dev, &reg);
166 + }
167 +
168 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
169 +
170 + mutex_unlock(&rt2x00dev->csr_mutex);
171 +}
172 +
173 +static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
174 + const unsigned int word, const u8 value)
175 +{
176 + u32 reg;
177 +
178 + mutex_lock(&rt2x00dev->csr_mutex);
179 +
180 + /*
181 + * Wait until the RFCSR becomes available, afterwards we
182 + * can safely write the new data into the register.
183 + */
184 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
185 + reg = 0;
186 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
187 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
188 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
189 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
190 +
191 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
192 + }
193 +
194 + mutex_unlock(&rt2x00dev->csr_mutex);
195 +}
196 +
197 +static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
198 + const unsigned int word, u8 *value)
199 +{
200 + u32 reg;
201 +
202 + mutex_lock(&rt2x00dev->csr_mutex);
203 +
204 + /*
205 + * Wait until the RFCSR becomes available, afterwards we
206 + * can safely write the read request into the register.
207 + * After the data has been written, we wait until hardware
208 + * returns the correct value, if at any time the register
209 + * doesn't become available in time, reg will be 0xffffffff
210 + * which means we return 0xff to the caller.
211 + */
212 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
213 + reg = 0;
214 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
215 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
216 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
217 +
218 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
219 +
220 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
221 + }
222 +
223 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
224 +
225 + mutex_unlock(&rt2x00dev->csr_mutex);
226 +}
227 +
228 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
229 + const unsigned int word, const u32 value)
230 +{
231 + u32 reg;
232 +
233 + mutex_lock(&rt2x00dev->csr_mutex);
234 +
235 + /*
236 + * Wait until the RF becomes available, afterwards we
237 + * can safely write the new data into the register.
238 + */
239 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
240 + reg = 0;
241 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
242 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
243 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
244 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
245 +
246 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
247 + rt2x00_rf_write(rt2x00dev, word, value);
248 + }
249 +
250 + mutex_unlock(&rt2x00dev->csr_mutex);
251 +}
252 +
253 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
254 + const u8 command, const u8 token,
255 + const u8 arg0, const u8 arg1)
256 +{
257 + u32 reg;
258 +
259 + /*
260 + * RT2880 and RT3052 don't support MCU requests.
261 + */
262 + if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
263 + rt2x00_rt(&rt2x00dev->chip, RT3052))
264 + return;
265 +
266 + mutex_lock(&rt2x00dev->csr_mutex);
267 +
268 + /*
269 + * Wait until the MCU becomes available, afterwards we
270 + * can safely write the new data into the register.
271 + */
272 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
273 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
274 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
275 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
276 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
277 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
278 +
279 + reg = 0;
280 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
281 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
282 + }
283 +
284 + mutex_unlock(&rt2x00dev->csr_mutex);
285 +}
286 +
287 +static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
288 +{
289 + unsigned int i;
290 + u32 reg;
291 +
292 + for (i = 0; i < 200; i++) {
293 + rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
294 +
295 + if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
296 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
297 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
298 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
299 + break;
300 +
301 + udelay(REGISTER_BUSY_DELAY);
302 + }
303 +
304 + if (i == 200)
305 + ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
306 +
307 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
308 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
309 +}
310 +
311 +#ifdef CONFIG_RT2800PCI_WISOC
312 +static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
313 +{
314 + u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
315 +
316 + memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
317 +}
318 +#else
319 +static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
320 +{
321 +}
322 +#endif /* CONFIG_RT2800PCI_WISOC */
323 +
324 +#ifdef CONFIG_RT2800PCI_PCI
325 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
326 +{
327 + struct rt2x00_dev *rt2x00dev = eeprom->data;
328 + u32 reg;
329 +
330 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
331 +
332 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
333 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
334 + eeprom->reg_data_clock =
335 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
336 + eeprom->reg_chip_select =
337 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
338 +}
339 +
340 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
341 +{
342 + struct rt2x00_dev *rt2x00dev = eeprom->data;
343 + u32 reg = 0;
344 +
345 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
346 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
347 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
348 + !!eeprom->reg_data_clock);
349 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
350 + !!eeprom->reg_chip_select);
351 +
352 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
353 +}
354 +
355 +static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
356 +{
357 + struct eeprom_93cx6 eeprom;
358 + u32 reg;
359 +
360 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
361 +
362 + eeprom.data = rt2x00dev;
363 + eeprom.register_read = rt2800pci_eepromregister_read;
364 + eeprom.register_write = rt2800pci_eepromregister_write;
365 + eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
366 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
367 + eeprom.reg_data_in = 0;
368 + eeprom.reg_data_out = 0;
369 + eeprom.reg_data_clock = 0;
370 + eeprom.reg_chip_select = 0;
371 +
372 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
373 + EEPROM_SIZE / sizeof(u16));
374 +}
375 +#else
376 +static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
377 +{
378 +}
379 +#endif /* CONFIG_RT2800PCI_PCI */
380 +
381 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
382 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
383 + .owner = THIS_MODULE,
384 + .csr = {
385 + .read = rt2x00pci_register_read,
386 + .write = rt2x00pci_register_write,
387 + .flags = RT2X00DEBUGFS_OFFSET,
388 + .word_base = CSR_REG_BASE,
389 + .word_size = sizeof(u32),
390 + .word_count = CSR_REG_SIZE / sizeof(u32),
391 + },
392 + .eeprom = {
393 + .read = rt2x00_eeprom_read,
394 + .write = rt2x00_eeprom_write,
395 + .word_base = EEPROM_BASE,
396 + .word_size = sizeof(u16),
397 + .word_count = EEPROM_SIZE / sizeof(u16),
398 + },
399 + .bbp = {
400 + .read = rt2800pci_bbp_read,
401 + .write = rt2800pci_bbp_write,
402 + .word_base = BBP_BASE,
403 + .word_size = sizeof(u8),
404 + .word_count = BBP_SIZE / sizeof(u8),
405 + },
406 + .rf = {
407 + .read = rt2x00_rf_read,
408 + .write = rt2800pci_rf_write,
409 + .word_base = RF_BASE,
410 + .word_size = sizeof(u32),
411 + .word_count = RF_SIZE / sizeof(u32),
412 + },
413 +};
414 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
415 +
416 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
417 +{
418 + u32 reg;
419 +
420 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
421 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
422 +}
423 +
424 +#ifdef CONFIG_RT2X00_LIB_LEDS
425 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
426 + enum led_brightness brightness)
427 +{
428 + struct rt2x00_led *led =
429 + container_of(led_cdev, struct rt2x00_led, led_dev);
430 + unsigned int enabled = brightness != LED_OFF;
431 + unsigned int bg_mode =
432 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
433 + unsigned int polarity =
434 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
435 + EEPROM_FREQ_LED_POLARITY);
436 + unsigned int ledmode =
437 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
438 + EEPROM_FREQ_LED_MODE);
439 +
440 + if (led->type == LED_TYPE_RADIO) {
441 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
442 + enabled ? 0x20 : 0);
443 + } else if (led->type == LED_TYPE_ASSOC) {
444 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
445 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
446 + } else if (led->type == LED_TYPE_QUALITY) {
447 + /*
448 + * The brightness is divided into 6 levels (0 - 5),
449 + * The specs tell us the following levels:
450 + * 0, 1 ,3, 7, 15, 31
451 + * to determine the level in a simple way we can simply
452 + * work with bitshifting:
453 + * (1 << level) - 1
454 + */
455 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
456 + (1 << brightness / (LED_FULL / 6)) - 1,
457 + polarity);
458 + }
459 +}
460 +
461 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
462 + unsigned long *delay_on,
463 + unsigned long *delay_off)
464 +{
465 + struct rt2x00_led *led =
466 + container_of(led_cdev, struct rt2x00_led, led_dev);
467 + u32 reg;
468 +
469 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
470 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
471 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
472 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
473 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
474 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
475 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
476 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
477 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
478 +
479 + return 0;
480 +}
481 +
482 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
483 + struct rt2x00_led *led,
484 + enum led_type type)
485 +{
486 + led->rt2x00dev = rt2x00dev;
487 + led->type = type;
488 + led->led_dev.brightness_set = rt2800pci_brightness_set;
489 + led->led_dev.blink_set = rt2800pci_blink_set;
490 + led->flags = LED_INITIALIZED;
491 +}
492 +#endif /* CONFIG_RT2X00_LIB_LEDS */
493 +
494 +/*
495 + * Configuration handlers.
496 + */
497 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
498 + struct rt2x00lib_crypto *crypto,
499 + struct ieee80211_key_conf *key)
500 +{
501 + struct mac_wcid_entry wcid_entry;
502 + struct mac_iveiv_entry iveiv_entry;
503 + u32 offset;
504 + u32 reg;
505 +
506 + offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
507 +
508 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
509 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
510 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
511 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
512 + (crypto->cmd == SET_KEY) * crypto->cipher);
513 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
514 + (crypto->cmd == SET_KEY) * crypto->bssidx);
515 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
516 + rt2x00pci_register_write(rt2x00dev, offset, reg);
517 +
518 + offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
519 +
520 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
521 + if ((crypto->cipher == CIPHER_TKIP) ||
522 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
523 + (crypto->cipher == CIPHER_AES))
524 + iveiv_entry.iv[3] |= 0x20;
525 + iveiv_entry.iv[3] |= key->keyidx << 6;
526 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
527 + &iveiv_entry, sizeof(iveiv_entry));
528 +
529 + offset = MAC_WCID_ENTRY(key->hw_key_idx);
530 +
531 + memset(&wcid_entry, 0, sizeof(wcid_entry));
532 + if (crypto->cmd == SET_KEY)
533 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
534 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
535 + &wcid_entry, sizeof(wcid_entry));
536 +}
537 +
538 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
539 + struct rt2x00lib_crypto *crypto,
540 + struct ieee80211_key_conf *key)
541 +{
542 + struct hw_key_entry key_entry;
543 + struct rt2x00_field32 field;
544 + u32 offset;
545 + u32 reg;
546 +
547 + if (crypto->cmd == SET_KEY) {
548 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
549 +
550 + memcpy(key_entry.key, crypto->key,
551 + sizeof(key_entry.key));
552 + memcpy(key_entry.tx_mic, crypto->tx_mic,
553 + sizeof(key_entry.tx_mic));
554 + memcpy(key_entry.rx_mic, crypto->rx_mic,
555 + sizeof(key_entry.rx_mic));
556 +
557 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
558 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
559 + &key_entry, sizeof(key_entry));
560 + }
561 +
562 + /*
563 + * The cipher types are stored over multiple registers
564 + * starting with SHARED_KEY_MODE_BASE each word will have
565 + * 32 bits and contains the cipher types for 2 bssidx each.
566 + * Using the correct defines correctly will cause overhead,
567 + * so just calculate the correct offset.
568 + */
569 + field.bit_offset = 4 * (key->hw_key_idx % 8);
570 + field.bit_mask = 0x7 << field.bit_offset;
571 +
572 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
573 +
574 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
575 + rt2x00_set_field32(&reg, field,
576 + (crypto->cmd == SET_KEY) * crypto->cipher);
577 + rt2x00pci_register_write(rt2x00dev, offset, reg);
578 +
579 + /*
580 + * Update WCID information
581 + */
582 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
583 +
584 + return 0;
585 +}
586 +
587 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
588 + struct rt2x00lib_crypto *crypto,
589 + struct ieee80211_key_conf *key)
590 +{
591 + struct hw_key_entry key_entry;
592 + u32 offset;
593 +
594 + if (crypto->cmd == SET_KEY) {
595 + /*
596 + * 1 pairwise key is possible per AID, this means that the AID
597 + * equals our hw_key_idx. Make sure the WCID starts _after_ the
598 + * last possible shared key entry.
599 + */
600 + if (crypto->aid > (256 - 32))
601 + return -ENOSPC;
602 +
603 + key->hw_key_idx = 32 + crypto->aid;
604 +
605 +
606 + memcpy(key_entry.key, crypto->key,
607 + sizeof(key_entry.key));
608 + memcpy(key_entry.tx_mic, crypto->tx_mic,
609 + sizeof(key_entry.tx_mic));
610 + memcpy(key_entry.rx_mic, crypto->rx_mic,
611 + sizeof(key_entry.rx_mic));
612 +
613 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
614 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
615 + &key_entry, sizeof(key_entry));
616 + }
617 +
618 + /*
619 + * Update WCID information
620 + */
621 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
622 +
623 + return 0;
624 +}
625 +
626 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
627 + const unsigned int filter_flags)
628 +{
629 + u32 reg;
630 +
631 + /*
632 + * Start configuration steps.
633 + * Note that the version error will always be dropped
634 + * and broadcast frames will always be accepted since
635 + * there is no filter for it at this time.
636 + */
637 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
638 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
639 + !(filter_flags & FIF_FCSFAIL));
640 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
641 + !(filter_flags & FIF_PLCPFAIL));
642 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
643 + !(filter_flags & FIF_PROMISC_IN_BSS));
644 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
645 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
646 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
647 + !(filter_flags & FIF_ALLMULTI));
648 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
649 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
650 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
651 + !(filter_flags & FIF_CONTROL));
652 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
653 + !(filter_flags & FIF_CONTROL));
654 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
655 + !(filter_flags & FIF_CONTROL));
656 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
657 + !(filter_flags & FIF_CONTROL));
658 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
659 + !(filter_flags & FIF_CONTROL));
660 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
661 + !(filter_flags & FIF_PSPOLL));
662 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
663 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
664 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
665 + !(filter_flags & FIF_CONTROL));
666 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
667 +}
668 +
669 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
670 + struct rt2x00_intf *intf,
671 + struct rt2x00intf_conf *conf,
672 + const unsigned int flags)
673 +{
674 + unsigned int beacon_base;
675 + u32 reg;
676 +
677 + if (flags & CONFIG_UPDATE_TYPE) {
678 + /*
679 + * Clear current synchronisation setup.
680 + * For the Beacon base registers we only need to clear
681 + * the first byte since that byte contains the VALID and OWNER
682 + * bits which (when set to 0) will invalidate the entire beacon.
683 + */
684 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
685 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
686 +
687 + /*
688 + * Enable synchronisation.
689 + */
690 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
691 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
692 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
693 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
694 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
695 + }
696 +
697 + if (flags & CONFIG_UPDATE_MAC) {
698 + reg = le32_to_cpu(conf->mac[1]);
699 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
700 + conf->mac[1] = cpu_to_le32(reg);
701 +
702 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
703 + conf->mac, sizeof(conf->mac));
704 + }
705 +
706 + if (flags & CONFIG_UPDATE_BSSID) {
707 + reg = le32_to_cpu(conf->bssid[1]);
708 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
709 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
710 + conf->bssid[1] = cpu_to_le32(reg);
711 +
712 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
713 + conf->bssid, sizeof(conf->bssid));
714 + }
715 +}
716 +
717 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
718 + struct rt2x00lib_erp *erp)
719 +{
720 + u32 reg;
721 +
722 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
723 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
724 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
725 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
726 +
727 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
728 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
729 + !!erp->short_preamble);
730 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
731 + !!erp->short_preamble);
732 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
733 +
734 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
735 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
736 + erp->cts_protection ? 2 : 0);
737 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
738 +
739 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
740 + erp->basic_rates);
741 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
742 +
743 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
744 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
745 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
746 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
747 +
748 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
749 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
750 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
751 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
752 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
753 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
754 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
755 +
756 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
757 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
758 + erp->beacon_int * 16);
759 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
760 +}
761 +
762 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
763 + struct antenna_setup *ant)
764 +{
765 + u8 r1;
766 + u8 r3;
767 +
768 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
769 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
770 +
771 + /*
772 + * Configure the TX antenna.
773 + */
774 + switch ((int)ant->tx) {
775 + case 1:
776 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
777 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
778 + break;
779 + case 2:
780 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
781 + break;
782 + case 3:
783 + /* Do nothing */
784 + break;
785 + }
786 +
787 + /*
788 + * Configure the RX antenna.
789 + */
790 + switch ((int)ant->rx) {
791 + case 1:
792 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
793 + break;
794 + case 2:
795 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
796 + break;
797 + case 3:
798 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
799 + break;
800 + }
801 +
802 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
803 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
804 +}
805 +
806 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
807 + struct rt2x00lib_conf *libconf)
808 +{
809 + u16 eeprom;
810 + short lna_gain;
811 +
812 + if (libconf->rf.channel <= 14) {
813 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
814 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
815 + } else if (libconf->rf.channel <= 64) {
816 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
817 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
818 + } else if (libconf->rf.channel <= 128) {
819 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
820 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
821 + } else {
822 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
823 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
824 + }
825 +
826 + rt2x00dev->lna_gain = lna_gain;
827 +}
828 +
829 +static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
830 + struct ieee80211_conf *conf,
831 + struct rf_channel *rf,
832 + struct channel_info *info)
833 +{
834 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
835 +
836 + if (rt2x00dev->default_ant.tx == 1)
837 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
838 +
839 + if (rt2x00dev->default_ant.rx == 1) {
840 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
841 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
842 + } else if (rt2x00dev->default_ant.rx == 2)
843 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
844 +
845 + if (rf->channel > 14) {
846 + /*
847 + * When TX power is below 0, we should increase it by 7 to
848 + * make it a positive value (Minumum value is -7).
849 + * However this means that values between 0 and 7 have
850 + * double meaning, and we should set a 7DBm boost flag.
851 + */
852 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
853 + (info->tx_power1 >= 0));
854 +
855 + if (info->tx_power1 < 0)
856 + info->tx_power1 += 7;
857 +
858 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
859 + TXPOWER_A_TO_DEV(info->tx_power1));
860 +
861 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
862 + (info->tx_power2 >= 0));
863 +
864 + if (info->tx_power2 < 0)
865 + info->tx_power2 += 7;
866 +
867 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
868 + TXPOWER_A_TO_DEV(info->tx_power2));
869 + } else {
870 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
871 + TXPOWER_G_TO_DEV(info->tx_power1));
872 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
873 + TXPOWER_G_TO_DEV(info->tx_power2));
874 + }
875 +
876 + rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
877 +
878 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
879 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
880 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
881 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
882 +
883 + udelay(200);
884 +
885 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
886 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
887 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
888 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
889 +
890 + udelay(200);
891 +
892 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
893 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
894 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
895 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
896 +}
897 +
898 +static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
899 + struct ieee80211_conf *conf,
900 + struct rf_channel *rf,
901 + struct channel_info *info)
902 +{
903 + u8 rfcsr;
904 +
905 + rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
906 + rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
907 +
908 + rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
909 + rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
910 + rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
911 +
912 + rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
913 + rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
914 + TXPOWER_G_TO_DEV(info->tx_power1));
915 + rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
916 +
917 + rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
918 + rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
919 + rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
920 +
921 + rt2800pci_rfcsr_write(rt2x00dev, 24,
922 + rt2x00dev->calibration[conf_is_ht40(conf)]);
923 +
924 + rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
925 + rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
926 + rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
927 +}
928 +
929 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
930 + struct ieee80211_conf *conf,
931 + struct rf_channel *rf,
932 + struct channel_info *info)
933 +{
934 + u32 reg;
935 + unsigned int tx_pin;
936 + u8 bbp;
937 +
938 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
939 + rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
940 + else
941 + rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
942 +
943 + /*
944 + * Change BBP settings
945 + */
946 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
947 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
948 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
949 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
950 +
951 + if (rf->channel <= 14) {
952 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
953 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
954 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
955 + } else {
956 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
957 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
958 + }
959 + } else {
960 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
961 +
962 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
963 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
964 + else
965 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
966 + }
967 +
968 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
969 + rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
970 + rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
971 + rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
972 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
973 +
974 + tx_pin = 0;
975 +
976 + /* Turn on unused PA or LNA when not using 1T or 1R */
977 + if (rt2x00dev->default_ant.tx != 1) {
978 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
979 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
980 + }
981 +
982 + /* Turn on unused PA or LNA when not using 1T or 1R */
983 + if (rt2x00dev->default_ant.rx != 1) {
984 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
985 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
986 + }
987 +
988 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
989 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
990 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
991 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
992 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
993 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
994 +
995 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
996 +
997 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
998 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
999 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1000 +
1001 + rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1002 + rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1003 + rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1004 +
1005 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1006 + if (conf_is_ht40(conf)) {
1007 + rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1008 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1009 + rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1010 + } else {
1011 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1012 + rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1013 + rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1014 + }
1015 + }
1016 +
1017 + msleep(1);
1018 +}
1019 +
1020 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1021 + const int txpower)
1022 +{
1023 + u32 reg;
1024 + u32 value = TXPOWER_G_TO_DEV(txpower);
1025 + u8 r1;
1026 +
1027 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1028 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1029 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
1030 +
1031 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1032 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1033 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1034 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1035 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1036 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1037 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1038 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1039 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1040 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1041 +
1042 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1043 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1044 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1045 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1046 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1047 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1048 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1049 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1050 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1051 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1052 +
1053 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1054 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1055 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1056 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1057 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1058 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1059 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1060 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1061 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1062 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1063 +
1064 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1065 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1066 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1067 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1068 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1069 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1070 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1071 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1072 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1073 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1074 +
1075 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1076 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1077 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1078 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1079 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1080 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1081 +}
1082 +
1083 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1084 + struct rt2x00lib_conf *libconf)
1085 +{
1086 + u32 reg;
1087 +
1088 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1089 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1090 + libconf->conf->short_frame_max_tx_count);
1091 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1092 + libconf->conf->long_frame_max_tx_count);
1093 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1094 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1095 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1096 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1097 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1098 +}
1099 +
1100 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1101 + struct rt2x00lib_conf *libconf)
1102 +{
1103 + enum dev_state state =
1104 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
1105 + STATE_SLEEP : STATE_AWAKE;
1106 + u32 reg;
1107 +
1108 + if (state == STATE_SLEEP) {
1109 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1110 +
1111 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1112 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1113 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1114 + libconf->conf->listen_interval - 1);
1115 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1116 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1117 +
1118 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1119 + } else {
1120 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1121 +
1122 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1123 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1124 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1125 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1126 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1127 + }
1128 +}
1129 +
1130 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1131 + struct rt2x00lib_conf *libconf,
1132 + const unsigned int flags)
1133 +{
1134 + /* Always recalculate LNA gain before changing configuration */
1135 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
1136 +
1137 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1138 + rt2800pci_config_channel(rt2x00dev, libconf->conf,
1139 + &libconf->rf, &libconf->channel);
1140 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1141 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1142 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1143 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
1144 + if (flags & IEEE80211_CONF_CHANGE_PS)
1145 + rt2800pci_config_ps(rt2x00dev, libconf);
1146 +}
1147 +
1148 +/*
1149 + * Link tuning
1150 + */
1151 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1152 + struct link_qual *qual)
1153 +{
1154 + u32 reg;
1155 +
1156 + /*
1157 + * Update FCS error count from register.
1158 + */
1159 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1160 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1161 +}
1162 +
1163 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1164 +{
1165 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1166 + return 0x2e + rt2x00dev->lna_gain;
1167 +
1168 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1169 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1170 + else
1171 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1172 +}
1173 +
1174 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1175 + struct link_qual *qual, u8 vgc_level)
1176 +{
1177 + if (qual->vgc_level != vgc_level) {
1178 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1179 + qual->vgc_level = vgc_level;
1180 + qual->vgc_level_reg = vgc_level;
1181 + }
1182 +}
1183 +
1184 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1185 + struct link_qual *qual)
1186 +{
1187 + rt2800pci_set_vgc(rt2x00dev, qual,
1188 + rt2800pci_get_default_vgc(rt2x00dev));
1189 +}
1190 +
1191 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1192 + struct link_qual *qual, const u32 count)
1193 +{
1194 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1195 + return;
1196 +
1197 + /*
1198 + * When RSSI is better then -80 increase VGC level with 0x10
1199 + */
1200 + rt2800pci_set_vgc(rt2x00dev, qual,
1201 + rt2800pci_get_default_vgc(rt2x00dev) +
1202 + ((qual->rssi > -80) * 0x10));
1203 +}
1204 +
1205 +/*
1206 + * Firmware functions
1207 + */
1208 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1209 +{
1210 + return FIRMWARE_RT2860;
1211 +}
1212 +
1213 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1214 + const u8 *data, const size_t len)
1215 +{
1216 + u16 fw_crc;
1217 + u16 crc;
1218 +
1219 + /*
1220 + * Only support 8kb firmware files.
1221 + */
1222 + if (len != 8192)
1223 + return FW_BAD_LENGTH;
1224 +
1225 + /*
1226 + * The last 2 bytes in the firmware array are the crc checksum itself,
1227 + * this means that we should never pass those 2 bytes to the crc
1228 + * algorithm.
1229 + */
1230 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1231 +
1232 + /*
1233 + * Use the crc ccitt algorithm.
1234 + * This will return the same value as the legacy driver which
1235 + * used bit ordering reversion on the both the firmware bytes
1236 + * before input input as well as on the final output.
1237 + * Obviously using crc ccitt directly is much more efficient.
1238 + */
1239 + crc = crc_ccitt(~0, data, len - 2);
1240 +
1241 + /*
1242 + * There is a small difference between the crc-itu-t + bitrev and
1243 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1244 + * will be swapped, use swab16 to convert the crc to the correct
1245 + * value.
1246 + */
1247 + crc = swab16(crc);
1248 +
1249 + return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1250 +}
1251 +
1252 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1253 + const u8 *data, const size_t len)
1254 +{
1255 + unsigned int i;
1256 + u32 reg;
1257 +
1258 + /*
1259 + * Wait for stable hardware.
1260 + */
1261 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1262 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1263 + if (reg && reg != ~0)
1264 + break;
1265 + msleep(1);
1266 + }
1267 +
1268 + if (i == REGISTER_BUSY_COUNT) {
1269 + ERROR(rt2x00dev, "Unstable hardware.\n");
1270 + return -EBUSY;
1271 + }
1272 +
1273 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1274 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1275 +
1276 + /*
1277 + * Disable DMA, will be reenabled later when enabling
1278 + * the radio.
1279 + */
1280 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1281 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1282 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1283 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1284 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1285 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1286 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1287 +
1288 + /*
1289 + * enable Host program ram write selection
1290 + */
1291 + reg = 0;
1292 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1293 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1294 +
1295 + /*
1296 + * Write firmware to device.
1297 + */
1298 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1299 + data, len);
1300 +
1301 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1302 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1303 +
1304 + /*
1305 + * Wait for device to stabilize.
1306 + */
1307 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1308 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1309 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1310 + break;
1311 + msleep(1);
1312 + }
1313 +
1314 + if (i == REGISTER_BUSY_COUNT) {
1315 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1316 + return -EBUSY;
1317 + }
1318 +
1319 + /*
1320 + * Disable interrupts
1321 + */
1322 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1323 +
1324 + /*
1325 + * Initialize BBP R/W access agent
1326 + */
1327 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1328 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1329 +
1330 + return 0;
1331 +}
1332 +
1333 +/*
1334 + * Initialization functions.
1335 + */
1336 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1337 +{
1338 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1339 + u32 word;
1340 +
1341 + if (entry->queue->qid == QID_RX) {
1342 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1343 +
1344 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1345 + } else {
1346 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1347 +
1348 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1349 + }
1350 +}
1351 +
1352 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1353 +{
1354 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1355 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1356 + u32 word;
1357 +
1358 + if (entry->queue->qid == QID_RX) {
1359 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1360 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1361 + rt2x00_desc_write(entry_priv->desc, 0, word);
1362 +
1363 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1364 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1365 + rt2x00_desc_write(entry_priv->desc, 1, word);
1366 + } else {
1367 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1368 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1369 + rt2x00_desc_write(entry_priv->desc, 1, word);
1370 + }
1371 +}
1372 +
1373 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1374 +{
1375 + struct queue_entry_priv_pci *entry_priv;
1376 + u32 reg;
1377 +
1378 + /*
1379 + * Initialize registers.
1380 + */
1381 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1382 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1383 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1384 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1385 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1386 +
1387 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1388 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1389 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1390 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1391 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1392 +
1393 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1394 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1395 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1396 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1397 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1398 +
1399 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1400 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1401 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1402 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1403 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1404 +
1405 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1406 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1407 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1408 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1409 + rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1410 +
1411 + /*
1412 + * Enable global DMA configuration
1413 + */
1414 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1415 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1416 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1417 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1418 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1419 +
1420 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1421 +
1422 + return 0;
1423 +}
1424 +
1425 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1426 +{
1427 + u32 reg;
1428 + unsigned int i;
1429 +
1430 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1431 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1432 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1433 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1434 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1435 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1436 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1437 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1438 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1439 +
1440 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1441 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1442 +
1443 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1444 +
1445 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1446 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1447 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1448 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1449 +
1450 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1451 +
1452 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1453 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1454 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1455 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1456 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1457 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1458 +
1459 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1460 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1461 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1462 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1463 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1464 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1465 +
1466 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1467 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1468 +
1469 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1470 +
1471 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1472 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1473 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1474 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1475 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1476 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1477 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1478 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1479 +
1480 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1481 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1482 +
1483 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1484 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1485 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1486 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1487 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1488 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1489 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1490 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1491 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1492 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1493 +
1494 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1495 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1496 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1497 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1498 +
1499 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1500 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1501 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1502 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1503 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1504 + else
1505 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1506 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1507 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1508 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1509 +
1510 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1511 +
1512 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1513 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1514 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1515 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1516 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1517 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1518 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1519 +
1520 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1521 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1522 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1523 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1524 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1525 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1526 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1527 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1528 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1529 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1530 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1531 +
1532 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1533 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1534 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1535 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1536 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1537 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1538 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1539 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1540 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1541 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1542 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1543 +
1544 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1545 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1546 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1547 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1548 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1549 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1550 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1551 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1552 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1553 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1554 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1555 +
1556 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1557 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1558 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1559 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1560 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1561 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1562 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1563 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1564 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1565 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1566 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1567 +
1568 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1569 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1570 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1571 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1572 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1573 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1574 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1575 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1576 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1577 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1578 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1579 +
1580 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1581 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1582 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1583 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1584 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1585 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1586 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1587 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1588 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1589 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1590 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1591 +
1592 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1593 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1594 +
1595 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1596 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1597 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1598 + IEEE80211_MAX_RTS_THRESHOLD);
1599 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1600 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1601 +
1602 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1603 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1604 +
1605 + /*
1606 + * ASIC will keep garbage value after boot, clear encryption keys.
1607 + */
1608 + for (i = 0; i < 256; i++) {
1609 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1610 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1611 + wcid, sizeof(wcid));
1612 +
1613 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1614 + rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1615 + }
1616 +
1617 + for (i = 0; i < 16; i++)
1618 + rt2x00pci_register_write(rt2x00dev,
1619 + SHARED_KEY_MODE_ENTRY(i), 0);
1620 +
1621 + /*
1622 + * Clear all beacons
1623 + * For the Beacon base registers we only need to clear
1624 + * the first byte since that byte contains the VALID and OWNER
1625 + * bits which (when set to 0) will invalidate the entire beacon.
1626 + */
1627 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1628 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1629 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1630 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1631 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1632 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1633 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1634 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1635 +
1636 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1637 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1638 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1639 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1640 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1641 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1642 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1643 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1644 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1645 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1646 +
1647 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1648 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1649 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1650 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1651 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1652 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1653 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1654 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1655 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1656 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1657 +
1658 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1659 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1660 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1661 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1662 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1663 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1664 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1665 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1666 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1667 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1668 +
1669 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1670 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1671 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1672 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1673 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1674 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1675 +
1676 + /*
1677 + * We must clear the error counters.
1678 + * These registers are cleared on read,
1679 + * so we may pass a useless variable to store the value.
1680 + */
1681 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1682 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1683 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1684 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1685 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1686 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1687 +
1688 + return 0;
1689 +}
1690 +
1691 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1692 +{
1693 + unsigned int i;
1694 + u32 reg;
1695 +
1696 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1697 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1698 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1699 + return 0;
1700 +
1701 + udelay(REGISTER_BUSY_DELAY);
1702 + }
1703 +
1704 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1705 + return -EACCES;
1706 +}
1707 +
1708 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1709 +{
1710 + unsigned int i;
1711 + u8 value;
1712 +
1713 + /*
1714 + * BBP was enabled after firmware was loaded,
1715 + * but we need to reactivate it now.
1716 + */
1717 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1718 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1719 + msleep(1);
1720 +
1721 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1722 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1723 + if ((value != 0xff) && (value != 0x00))
1724 + return 0;
1725 + udelay(REGISTER_BUSY_DELAY);
1726 + }
1727 +
1728 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1729 + return -EACCES;
1730 +}
1731 +
1732 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1733 +{
1734 + unsigned int i;
1735 + u16 eeprom;
1736 + u8 reg_id;
1737 + u8 value;
1738 +
1739 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1740 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1741 + return -EACCES;
1742 +
1743 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1744 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1745 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1746 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1747 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1748 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1749 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1750 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1751 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1752 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1753 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1754 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1755 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1756 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1757 +
1758 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1759 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1760 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1761 + }
1762 +
1763 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1764 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1765 +
1766 + if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1767 + rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1768 + rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1769 + rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1770 + }
1771 +
1772 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1773 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1774 +
1775 + if (eeprom != 0xffff && eeprom != 0x0000) {
1776 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1777 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1778 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1779 + }
1780 + }
1781 +
1782 + return 0;
1783 +}
1784 +
1785 +static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1786 + bool bw40, u8 rfcsr24, u8 filter_target)
1787 +{
1788 + unsigned int i;
1789 + u8 bbp;
1790 + u8 rfcsr;
1791 + u8 passband;
1792 + u8 stopband;
1793 + u8 overtuned = 0;
1794 +
1795 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1796 +
1797 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1798 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1799 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1800 +
1801 + rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1802 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1803 + rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1804 +
1805 + /*
1806 + * Set power & frequency of passband test tone
1807 + */
1808 + rt2800pci_bbp_write(rt2x00dev, 24, 0);
1809 +
1810 + for (i = 0; i < 100; i++) {
1811 + rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1812 + msleep(1);
1813 +
1814 + rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1815 + if (passband)
1816 + break;
1817 + }
1818 +
1819 + /*
1820 + * Set power & frequency of stopband test tone
1821 + */
1822 + rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1823 +
1824 + for (i = 0; i < 100; i++) {
1825 + rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1826 + msleep(1);
1827 +
1828 + rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1829 +
1830 + if ((passband - stopband) <= filter_target) {
1831 + rfcsr24++;
1832 + overtuned += ((passband - stopband) == filter_target);
1833 + } else
1834 + break;
1835 +
1836 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1837 + }
1838 +
1839 + rfcsr24 -= !!overtuned;
1840 +
1841 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1842 + return rfcsr24;
1843 +}
1844 +
1845 +static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1846 +{
1847 + u8 rfcsr;
1848 + u8 bbp;
1849 +
1850 + if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1851 + !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1852 + !rt2x00_rf(&rt2x00dev->chip, RF3022))
1853 + return 0;
1854 +
1855 + /*
1856 + * Init RF calibration.
1857 + */
1858 + rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1859 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1860 + rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1861 + msleep(1);
1862 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1863 + rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1864 +
1865 + rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1866 + rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1867 + rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1868 + rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1869 + rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1870 + rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1871 + rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1872 + rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1873 + rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1874 + rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1875 + rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1876 + rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1877 + rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1878 + rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1879 + rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1880 + rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1881 + rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1882 + rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1883 + rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1884 + rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1885 + rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1886 + rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1887 + rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1888 + rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1889 + rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1890 + rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1891 + rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1892 + rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1893 + rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1894 + rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1895 +
1896 + /*
1897 + * Set RX Filter calibration for 20MHz and 40MHz
1898 + */
1899 + rt2x00dev->calibration[0] =
1900 + rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1901 + rt2x00dev->calibration[1] =
1902 + rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1903 +
1904 + /*
1905 + * Set back to initial state
1906 + */
1907 + rt2800pci_bbp_write(rt2x00dev, 24, 0);
1908 +
1909 + rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1910 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1911 + rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1912 +
1913 + /*
1914 + * set BBP back to BW20
1915 + */
1916 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1917 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1918 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1919 +
1920 + return 0;
1921 +}
1922 +
1923 +/*
1924 + * Device state switch handlers.
1925 + */
1926 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1927 + enum dev_state state)
1928 +{
1929 + u32 reg;
1930 +
1931 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1932 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1933 + (state == STATE_RADIO_RX_ON) ||
1934 + (state == STATE_RADIO_RX_ON_LINK));
1935 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1936 +}
1937 +
1938 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1939 + enum dev_state state)
1940 +{
1941 + int mask = (state == STATE_RADIO_IRQ_ON);
1942 + u32 reg;
1943 +
1944 + /*
1945 + * When interrupts are being enabled, the interrupt registers
1946 + * should clear the register to assure a clean state.
1947 + */
1948 + if (state == STATE_RADIO_IRQ_ON) {
1949 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1950 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1951 + }
1952 +
1953 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1954 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1955 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1956 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1957 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1958 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1959 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1960 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1961 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1962 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1963 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1964 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1965 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1966 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1967 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1968 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1969 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1970 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1971 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1972 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1973 +}
1974 +
1975 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1976 +{
1977 + unsigned int i;
1978 + u32 reg;
1979 +
1980 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1981 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1982 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1983 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1984 + return 0;
1985 +
1986 + msleep(1);
1987 + }
1988 +
1989 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1990 + return -EACCES;
1991 +}
1992 +
1993 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1994 +{
1995 + u32 reg;
1996 + u16 word;
1997 +
1998 + /*
1999 + * Initialize all registers.
2000 + */
2001 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2002 + rt2800pci_init_queues(rt2x00dev) ||
2003 + rt2800pci_init_registers(rt2x00dev) ||
2004 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2005 + rt2800pci_init_bbp(rt2x00dev) ||
2006 + rt2800pci_init_rfcsr(rt2x00dev)))
2007 + return -EIO;
2008 +
2009 + /*
2010 + * Send signal to firmware during boot time.
2011 + */
2012 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2013 +
2014 + /*
2015 + * Enable RX.
2016 + */
2017 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2018 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2019 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2020 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2021 +
2022 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2023 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2024 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2025 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2026 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2027 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2028 +
2029 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2030 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2031 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2032 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2033 +
2034 + /*
2035 + * Initialize LED control
2036 + */
2037 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2038 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2039 + word & 0xff, (word >> 8) & 0xff);
2040 +
2041 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2042 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2043 + word & 0xff, (word >> 8) & 0xff);
2044 +
2045 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2046 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2047 + word & 0xff, (word >> 8) & 0xff);
2048 +
2049 + return 0;
2050 +}
2051 +
2052 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2053 +{
2054 + u32 reg;
2055 +
2056 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2057 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2058 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2059 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2060 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2061 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2062 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2063 +
2064 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2065 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2066 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
2067 +
2068 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2069 +
2070 + /* Wait for DMA, ignore error */
2071 + rt2800pci_wait_wpdma_ready(rt2x00dev);
2072 +}
2073 +
2074 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2075 + enum dev_state state)
2076 +{
2077 + /*
2078 + * Always put the device to sleep (even when we intend to wakeup!)
2079 + * if the device is booting and wasn't asleep it will return
2080 + * failure when attempting to wakeup.
2081 + */
2082 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2083 +
2084 + if (state == STATE_AWAKE) {
2085 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2086 + rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2087 + }
2088 +
2089 + return 0;
2090 +}
2091 +
2092 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2093 + enum dev_state state)
2094 +{
2095 + int retval = 0;
2096 +
2097 + switch (state) {
2098 + case STATE_RADIO_ON:
2099 + /*
2100 + * Before the radio can be enabled, the device first has
2101 + * to be woken up. After that it needs a bit of time
2102 + * to be fully awake and then the radio can be enabled.
2103 + */
2104 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2105 + msleep(1);
2106 + retval = rt2800pci_enable_radio(rt2x00dev);
2107 + break;
2108 + case STATE_RADIO_OFF:
2109 + /*
2110 + * After the radio has been disabled, the device should
2111 + * be put to sleep for powersaving.
2112 + */
2113 + rt2800pci_disable_radio(rt2x00dev);
2114 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2115 + break;
2116 + case STATE_RADIO_RX_ON:
2117 + case STATE_RADIO_RX_ON_LINK:
2118 + case STATE_RADIO_RX_OFF:
2119 + case STATE_RADIO_RX_OFF_LINK:
2120 + rt2800pci_toggle_rx(rt2x00dev, state);
2121 + break;
2122 + case STATE_RADIO_IRQ_ON:
2123 + case STATE_RADIO_IRQ_OFF:
2124 + rt2800pci_toggle_irq(rt2x00dev, state);
2125 + break;
2126 + case STATE_DEEP_SLEEP:
2127 + case STATE_SLEEP:
2128 + case STATE_STANDBY:
2129 + case STATE_AWAKE:
2130 + retval = rt2800pci_set_state(rt2x00dev, state);
2131 + break;
2132 + default:
2133 + retval = -ENOTSUPP;
2134 + break;
2135 + }
2136 +
2137 + if (unlikely(retval))
2138 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2139 + state, retval);
2140 +
2141 + return retval;
2142 +}
2143 +
2144 +/*
2145 + * TX descriptor initialization
2146 + */
2147 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2148 + struct sk_buff *skb,
2149 + struct txentry_desc *txdesc)
2150 +{
2151 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2152 + __le32 *txd = skbdesc->desc;
2153 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2154 + u32 word;
2155 +
2156 + /*
2157 + * Initialize TX Info descriptor
2158 + */
2159 + rt2x00_desc_read(txwi, 0, &word);
2160 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
2161 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2162 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2163 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2164 + rt2x00_set_field32(&word, TXWI_W0_TS,
2165 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2166 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2167 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2168 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2169 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2170 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2171 + rt2x00_set_field32(&word, TXWI_W0_BW,
2172 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2173 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2174 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2175 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2176 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2177 + rt2x00_desc_write(txwi, 0, word);
2178 +
2179 + rt2x00_desc_read(txwi, 1, &word);
2180 + rt2x00_set_field32(&word, TXWI_W1_ACK,
2181 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2182 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2183 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2184 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2185 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2186 + test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2187 + txdesc->key_idx : 0xff);
2188 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2189 + skb->len - txdesc->l2pad);
2190 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2191 + skbdesc->entry->queue->qid);
2192 + rt2x00_desc_write(txwi, 1, word);
2193 +
2194 + /*
2195 + * Always write 0 to IV/EIV fields, hardware will insert the IV
2196 + * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
2197 + * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
2198 + * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2199 + * crypto entry in the registers should be used to encrypt the frame.
2200 + */
2201 + _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2202 + _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2203 +
2204 + /*
2205 + * Initialize TX descriptor
2206 + */
2207 + rt2x00_desc_read(txd, 0, &word);
2208 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2209 + rt2x00_desc_write(txd, 0, word);
2210 +
2211 + rt2x00_desc_read(txd, 1, &word);
2212 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2213 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2214 + rt2x00_set_field32(&word, TXD_W1_BURST,
2215 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2216 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2217 + rt2x00dev->hw->extra_tx_headroom);
2218 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2219 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2220 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2221 + rt2x00_desc_write(txd, 1, word);
2222 +
2223 + rt2x00_desc_read(txd, 2, &word);
2224 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2225 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2226 + rt2x00_desc_write(txd, 2, word);
2227 +
2228 + rt2x00_desc_read(txd, 3, &word);
2229 + rt2x00_set_field32(&word, TXD_W3_WIV,
2230 + !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2231 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2232 + rt2x00_desc_write(txd, 3, word);
2233 +}
2234 +
2235 +/*
2236 + * TX data initialization
2237 + */
2238 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2239 +{
2240 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2241 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2242 + unsigned int beacon_base;
2243 + u32 reg;
2244 +
2245 + /*
2246 + * Disable beaconing while we are reloading the beacon data,
2247 + * otherwise we might be sending out invalid data.
2248 + */
2249 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2250 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2251 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2252 +
2253 + /*
2254 + * Write entire beacon with descriptor to register.
2255 + */
2256 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2257 + rt2x00pci_register_multiwrite(rt2x00dev,
2258 + beacon_base,
2259 + skbdesc->desc, skbdesc->desc_len);
2260 + rt2x00pci_register_multiwrite(rt2x00dev,
2261 + beacon_base + skbdesc->desc_len,
2262 + entry->skb->data, entry->skb->len);
2263 +
2264 + /*
2265 + * Clean up beacon skb.
2266 + */
2267 + dev_kfree_skb_any(entry->skb);
2268 + entry->skb = NULL;
2269 +}
2270 +
2271 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2272 + const enum data_queue_qid queue_idx)
2273 +{
2274 + struct data_queue *queue;
2275 + unsigned int idx, qidx = 0;
2276 + u32 reg;
2277 +
2278 + if (queue_idx == QID_BEACON) {
2279 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2280 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2281 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2282 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2283 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2284 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2285 + }
2286 + return;
2287 + }
2288 +
2289 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2290 + return;
2291 +
2292 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2293 + idx = queue->index[Q_INDEX];
2294 +
2295 + if (queue_idx == QID_MGMT)
2296 + qidx = 5;
2297 + else
2298 + qidx = queue_idx;
2299 +
2300 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2301 +}
2302 +
2303 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2304 + const enum data_queue_qid qid)
2305 +{
2306 + u32 reg;
2307 +
2308 + if (qid == QID_BEACON) {
2309 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2310 + return;
2311 + }
2312 +
2313 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2314 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2315 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2316 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2317 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2318 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2319 +}
2320 +
2321 +/*
2322 + * RX control handlers
2323 + */
2324 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2325 + struct rxdone_entry_desc *rxdesc)
2326 +{
2327 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2328 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2329 + __le32 *rxd = entry_priv->desc;
2330 + __le32 *rxwi = (__le32 *)entry->skb->data;
2331 + u32 rxd3;
2332 + u32 rxwi0;
2333 + u32 rxwi1;
2334 + u32 rxwi2;
2335 + u32 rxwi3;
2336 +
2337 + rt2x00_desc_read(rxd, 3, &rxd3);
2338 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2339 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2340 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2341 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2342 +
2343 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2344 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2345 +
2346 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2347 + /*
2348 + * Unfortunately we don't know the cipher type used during
2349 + * decryption. This prevents us from correct providing
2350 + * correct statistics through debugfs.
2351 + */
2352 + rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2353 + rxdesc->cipher_status =
2354 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2355 + }
2356 +
2357 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2358 + /*
2359 + * Hardware has stripped IV/EIV data from 802.11 frame during
2360 + * decryption. Unfortunately the descriptor doesn't contain
2361 + * any fields with the EIV/IV data either, so they can't
2362 + * be restored by rt2x00lib.
2363 + */
2364 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2365 +
2366 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2367 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2368 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2369 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2370 + }
2371 +
2372 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2373 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2374 +
2375 + if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
2376 + rxdesc->dev_flags |= RXDONE_L2PAD;
2377 +
2378 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2379 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2380 +
2381 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2382 + rxdesc->flags |= RX_FLAG_40MHZ;
2383 +
2384 + /*
2385 + * Detect RX rate, always use MCS as signal type.
2386 + */
2387 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2388 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2389 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2390 +
2391 + /*
2392 + * Mask of 0x8 bit to remove the short preamble flag.
2393 + */
2394 + if (rxdesc->rate_mode == RATE_MODE_CCK)
2395 + rxdesc->signal &= ~0x8;
2396 +
2397 + rxdesc->rssi =
2398 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2399 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2400 +
2401 + rxdesc->noise =
2402 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2403 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2404 +
2405 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2406 +
2407 + /*
2408 + * Set RX IDX in register to inform hardware that we have handled
2409 + * this entry and it is available for reuse again.
2410 + */
2411 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2412 +
2413 + /*
2414 + * Remove TXWI descriptor from start of buffer.
2415 + */
2416 + skb_pull(entry->skb, RXWI_DESC_SIZE);
2417 + skb_trim(entry->skb, rxdesc->size);
2418 +}
2419 +
2420 +/*
2421 + * Interrupt functions.
2422 + */
2423 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2424 +{
2425 + struct data_queue *queue;
2426 + struct queue_entry *entry;
2427 + struct queue_entry *entry_done;
2428 + struct queue_entry_priv_pci *entry_priv;
2429 + struct txdone_entry_desc txdesc;
2430 + u32 word;
2431 + u32 reg;
2432 + u32 old_reg;
2433 + int type;
2434 + int index;
2435 +
2436 + /*
2437 + * During each loop we will compare the freshly read
2438 + * TX_STA_FIFO register value with the value read from
2439 + * the previous loop. If the 2 values are equal then
2440 + * we should stop processing because the chance it
2441 + * quite big that the device has been unplugged and
2442 + * we risk going into an endless loop.
2443 + */
2444 + old_reg = 0;
2445 +
2446 + while (1) {
2447 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2448 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2449 + break;
2450 +
2451 + if (old_reg == reg)
2452 + break;
2453 + old_reg = reg;
2454 +
2455 + /*
2456 + * Skip this entry when it contains an invalid
2457 + * queue identication number.
2458 + */
2459 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2460 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2461 + if (unlikely(!queue))
2462 + continue;
2463 +
2464 + /*
2465 + * Skip this entry when it contains an invalid
2466 + * index number.
2467 + */
2468 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2469 + if (unlikely(index >= queue->limit))
2470 + continue;
2471 +
2472 + entry = &queue->entries[index];
2473 + entry_priv = entry->priv_data;
2474 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2475 +
2476 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2477 + while (entry != entry_done) {
2478 + /*
2479 + * Catch up.
2480 + * Just report any entries we missed as failed.
2481 + */
2482 + WARNING(rt2x00dev,
2483 + "TX status report missed for entry %d\n",
2484 + entry_done->entry_idx);
2485 +
2486 + txdesc.flags = 0;
2487 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2488 + txdesc.retry = 0;
2489 +
2490 + rt2x00lib_txdone(entry_done, &txdesc);
2491 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2492 + }
2493 +
2494 + /*
2495 + * Obtain the status about this packet.
2496 + */
2497 + txdesc.flags = 0;
2498 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2499 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2500 + else
2501 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2502 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2503 +
2504 + rt2x00lib_txdone(entry, &txdesc);
2505 + }
2506 +}
2507 +
2508 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2509 +{
2510 + struct rt2x00_dev *rt2x00dev = dev_instance;
2511 + u32 reg;
2512 +
2513 + /* Read status and ACK all interrupts */
2514 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2515 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2516 +
2517 + if (!reg)
2518 + return IRQ_NONE;
2519 +
2520 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2521 + return IRQ_HANDLED;
2522 +
2523 + /*
2524 + * 1 - Rx ring done interrupt.
2525 + */
2526 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2527 + rt2x00pci_rxdone(rt2x00dev);
2528 +
2529 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2530 + rt2800pci_txdone(rt2x00dev);
2531 +
2532 + return IRQ_HANDLED;
2533 +}
2534 +
2535 +/*
2536 + * Device probe functions.
2537 + */
2538 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2539 +{
2540 + u16 word;
2541 + u8 *mac;
2542 + u8 default_lna_gain;
2543 +
2544 + /*
2545 + * Read EEPROM into buffer
2546 + */
2547 + switch(rt2x00dev->chip.rt) {
2548 + case RT2880:
2549 + case RT3052:
2550 + rt2800pci_read_eeprom_soc(rt2x00dev);
2551 + break;
2552 + default:
2553 + rt2800pci_read_eeprom_pci(rt2x00dev);
2554 + break;
2555 + }
2556 +
2557 + /*
2558 + * Start validation of the data that has been read.
2559 + */
2560 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2561 + if (!is_valid_ether_addr(mac)) {
2562 + DECLARE_MAC_BUF(macbuf);
2563 +
2564 + random_ether_addr(mac);
2565 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2566 + }
2567 +
2568 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2569 + if (word == 0xffff) {
2570 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2571 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2572 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2573 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2574 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2575 + } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2576 + /*
2577 + * There is a max of 2 RX streams for RT2860 series
2578 + */
2579 + if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2580 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2581 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2582 + }
2583 +
2584 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2585 + if (word == 0xffff) {
2586 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2587 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2588 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2589 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2590 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2591 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2592 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2593 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2594 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2595 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2596 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2597 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2598 + }
2599 +
2600 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2601 + if ((word & 0x00ff) == 0x00ff) {
2602 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2603 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2604 + LED_MODE_TXRX_ACTIVITY);
2605 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2606 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2607 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2608 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2609 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2610 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2611 + }
2612 +
2613 + /*
2614 + * During the LNA validation we are going to use
2615 + * lna0 as correct value. Note that EEPROM_LNA
2616 + * is never validated.
2617 + */
2618 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2619 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2620 +
2621 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2622 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2623 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2624 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2625 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2626 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2627 +
2628 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2629 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2630 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2631 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2632 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2633 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2634 + default_lna_gain);
2635 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2636 +
2637 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2638 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2639 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2640 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2641 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2642 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2643 +
2644 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2645 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2646 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2647 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2648 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2649 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2650 + default_lna_gain);
2651 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2652 +
2653 + return 0;
2654 +}
2655 +
2656 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2657 +{
2658 + u32 reg;
2659 + u16 value;
2660 + u16 eeprom;
2661 +
2662 + /*
2663 + * Read EEPROM word for configuration.
2664 + */
2665 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2666 +
2667 + /*
2668 + * Identify RF chipset.
2669 + */
2670 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2671 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2672 + rt2x00_set_chip_rf(rt2x00dev, value, reg);
2673 +
2674 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2675 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2676 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2677 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2678 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2679 + !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2680 + !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2681 + !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2682 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2683 + return -ENODEV;
2684 + }
2685 +
2686 + /*
2687 + * Identify default antenna configuration.
2688 + */
2689 + rt2x00dev->default_ant.tx =
2690 + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2691 + rt2x00dev->default_ant.rx =
2692 + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2693 +
2694 + /*
2695 + * Read frequency offset and RF programming sequence.
2696 + */
2697 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2698 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2699 +
2700 + /*
2701 + * Read external LNA informations.
2702 + */
2703 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2704 +
2705 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2706 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2707 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2708 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2709 +
2710 + /*
2711 + * Detect if this device has an hardware controlled radio.
2712 + */
2713 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2714 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2715 +
2716 + /*
2717 + * Store led settings, for correct led behaviour.
2718 + */
2719 +#ifdef CONFIG_RT2X00_LIB_LEDS
2720 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2721 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2722 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2723 +
2724 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2725 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2726 +
2727 + return 0;
2728 +}
2729 +
2730 +/*
2731 + * RF value list for rt2860
2732 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2733 + */
2734 +static const struct rf_channel rf_vals[] = {
2735 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2736 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2737 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2738 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2739 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2740 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2741 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2742 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2743 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2744 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2745 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2746 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2747 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2748 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2749 +
2750 + /* 802.11 UNI / HyperLan 2 */
2751 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2752 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2753 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2754 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2755 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2756 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2757 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2758 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2759 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2760 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2761 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2762 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2763 +
2764 + /* 802.11 HyperLan 2 */
2765 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2766 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2767 + { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2768 + { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2769 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2770 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2771 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2772 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2773 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2774 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2775 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2776 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2777 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2778 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2779 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2780 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2781 +
2782 + /* 802.11 UNII */
2783 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2784 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2785 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2786 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2787 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2788 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2789 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2790 +
2791 + /* 802.11 Japan */
2792 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2793 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2794 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2795 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2796 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2797 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2798 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2799 +};
2800 +
2801 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2802 +{
2803 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2804 + struct channel_info *info;
2805 + char *tx_power1;
2806 + char *tx_power2;
2807 + unsigned int i;
2808 + u16 eeprom;
2809 +
2810 + /*
2811 + * Initialize all hw fields.
2812 + */
2813 + rt2x00dev->hw->flags =
2814 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2815 + IEEE80211_HW_SIGNAL_DBM |
2816 + IEEE80211_HW_SUPPORTS_PS |
2817 + IEEE80211_HW_PS_NULLFUNC_STACK;
2818 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2819 +
2820 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2821 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2822 + rt2x00_eeprom_addr(rt2x00dev,
2823 + EEPROM_MAC_ADDR_0));
2824 +
2825 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2826 +
2827 + /*
2828 + * Initialize hw_mode information.
2829 + */
2830 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2831 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2832 +
2833 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2834 + rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2835 + rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2836 + rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2837 + spec->num_channels = 14;
2838 + spec->channels = rf_vals;
2839 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2840 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2841 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2842 + spec->num_channels = ARRAY_SIZE(rf_vals);
2843 + spec->channels = rf_vals;
2844 + }
2845 +
2846 + /*
2847 + * Initialize HT information.
2848 + */
2849 + spec->ht.ht_supported = true;
2850 + spec->ht.cap =
2851 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2852 + IEEE80211_HT_CAP_GRN_FLD |
2853 + IEEE80211_HT_CAP_SGI_20 |
2854 + IEEE80211_HT_CAP_SGI_40 |
2855 + IEEE80211_HT_CAP_TX_STBC |
2856 + IEEE80211_HT_CAP_RX_STBC |
2857 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2858 + spec->ht.ampdu_factor = 3;
2859 + spec->ht.ampdu_density = 4;
2860 + spec->ht.mcs.tx_params =
2861 + IEEE80211_HT_MCS_TX_DEFINED |
2862 + IEEE80211_HT_MCS_TX_RX_DIFF |
2863 + ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2864 + IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2865 +
2866 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2867 + case 3:
2868 + spec->ht.mcs.rx_mask[2] = 0xff;
2869 + case 2:
2870 + spec->ht.mcs.rx_mask[1] = 0xff;
2871 + case 1:
2872 + spec->ht.mcs.rx_mask[0] = 0xff;
2873 + spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2874 + break;
2875 + }
2876 +
2877 + /*
2878 + * Create channel information array
2879 + */
2880 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2881 + if (!info)
2882 + return -ENOMEM;
2883 +
2884 + spec->channels_info = info;
2885 +
2886 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2887 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2888 +
2889 + for (i = 0; i < 14; i++) {
2890 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2891 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2892 + }
2893 +
2894 + if (spec->num_channels > 14) {
2895 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2896 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2897 +
2898 + for (i = 14; i < spec->num_channels; i++) {
2899 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2900 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2901 + }
2902 + }
2903 +
2904 + return 0;
2905 +}
2906 +
2907 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2908 +{
2909 + int retval;
2910 +
2911 + /*
2912 + * Allocate eeprom data.
2913 + */
2914 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2915 + if (retval)
2916 + return retval;
2917 +
2918 + retval = rt2800pci_init_eeprom(rt2x00dev);
2919 + if (retval)
2920 + return retval;
2921 +
2922 + /*
2923 + * Initialize hw specifications.
2924 + */
2925 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2926 + if (retval)
2927 + return retval;
2928 +
2929 + /*
2930 + * This device has multiple filters for control frames
2931 + * and has a separate filter for PS Poll frames.
2932 + */
2933 + __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2934 + __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2935 +
2936 + /*
2937 + * This device requires firmware.
2938 + */
2939 + if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
2940 + !rt2x00_rt(&rt2x00dev->chip, RT3052))
2941 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2942 + __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2943 + __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2944 + if (!modparam_nohwcrypt)
2945 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2946 +
2947 + /*
2948 + * Set the rssi offset.
2949 + */
2950 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2951 +
2952 + return 0;
2953 +}
2954 +
2955 +/*
2956 + * IEEE80211 stack callback functions.
2957 + */
2958 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2959 + u32 *iv32, u16 *iv16)
2960 +{
2961 + struct rt2x00_dev *rt2x00dev = hw->priv;
2962 + struct mac_iveiv_entry iveiv_entry;
2963 + u32 offset;
2964 +
2965 + offset = MAC_IVEIV_ENTRY(hw_key_idx);
2966 + rt2x00pci_register_multiread(rt2x00dev, offset,
2967 + &iveiv_entry, sizeof(iveiv_entry));
2968 +
2969 + memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2970 + memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2971 +}
2972 +
2973 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2974 +{
2975 + struct rt2x00_dev *rt2x00dev = hw->priv;
2976 + u32 reg;
2977 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2978 +
2979 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2980 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2981 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2982 +
2983 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2984 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2985 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2986 +
2987 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2988 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2989 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2990 +
2991 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2992 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2993 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2994 +
2995 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2996 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2997 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2998 +
2999 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3000 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3001 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3002 +
3003 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3004 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3005 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3006 +
3007 + return 0;
3008 +}
3009 +
3010 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3011 + const struct ieee80211_tx_queue_params *params)
3012 +{
3013 + struct rt2x00_dev *rt2x00dev = hw->priv;
3014 + struct data_queue *queue;
3015 + struct rt2x00_field32 field;
3016 + int retval;
3017 + u32 reg;
3018 + u32 offset;
3019 +
3020 + /*
3021 + * First pass the configuration through rt2x00lib, that will
3022 + * update the queue settings and validate the input. After that
3023 + * we are free to update the registers based on the value
3024 + * in the queue parameter.
3025 + */
3026 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3027 + if (retval)
3028 + return retval;
3029 +
3030 + /*
3031 + * We only need to perform additional register initialization
3032 + * for WMM queues/
3033 + */
3034 + if (queue_idx >= 4)
3035 + return 0;
3036 +
3037 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3038 +
3039 + /* Update WMM TXOP register */
3040 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3041 + field.bit_offset = (queue_idx & 1) * 16;
3042 + field.bit_mask = 0xffff << field.bit_offset;
3043 +
3044 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
3045 + rt2x00_set_field32(&reg, field, queue->txop);
3046 + rt2x00pci_register_write(rt2x00dev, offset, reg);
3047 +
3048 + /* Update WMM registers */
3049 + field.bit_offset = queue_idx * 4;
3050 + field.bit_mask = 0xf << field.bit_offset;
3051 +
3052 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3053 + rt2x00_set_field32(&reg, field, queue->aifs);
3054 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3055 +
3056 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3057 + rt2x00_set_field32(&reg, field, queue->cw_min);
3058 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3059 +
3060 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3061 + rt2x00_set_field32(&reg, field, queue->cw_max);
3062 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3063 +
3064 + /* Update EDCA registers */
3065 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3066 +
3067 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
3068 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3069 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3070 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3071 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3072 + rt2x00pci_register_write(rt2x00dev, offset, reg);
3073 +
3074 + return 0;
3075 +}
3076 +
3077 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3078 +{
3079 + struct rt2x00_dev *rt2x00dev = hw->priv;
3080 + u64 tsf;
3081 + u32 reg;
3082 +
3083 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3084 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3085 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3086 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3087 +
3088 + return tsf;
3089 +}
3090 +
3091 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3092 + .tx = rt2x00mac_tx,
3093 + .start = rt2x00mac_start,
3094 + .stop = rt2x00mac_stop,
3095 + .add_interface = rt2x00mac_add_interface,
3096 + .remove_interface = rt2x00mac_remove_interface,
3097 + .config = rt2x00mac_config,
3098 + .configure_filter = rt2x00mac_configure_filter,
3099 + .set_key = rt2x00mac_set_key,
3100 + .get_stats = rt2x00mac_get_stats,
3101 + .get_tkip_seq = rt2800pci_get_tkip_seq,
3102 + .set_rts_threshold = rt2800pci_set_rts_threshold,
3103 + .bss_info_changed = rt2x00mac_bss_info_changed,
3104 + .conf_tx = rt2800pci_conf_tx,
3105 + .get_tx_stats = rt2x00mac_get_tx_stats,
3106 + .get_tsf = rt2800pci_get_tsf,
3107 + .rfkill_poll = rt2x00mac_rfkill_poll,
3108 +};
3109 +
3110 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3111 + .irq_handler = rt2800pci_interrupt,
3112 + .probe_hw = rt2800pci_probe_hw,
3113 + .get_firmware_name = rt2800pci_get_firmware_name,
3114 + .check_firmware = rt2800pci_check_firmware,
3115 + .load_firmware = rt2800pci_load_firmware,
3116 + .initialize = rt2x00pci_initialize,
3117 + .uninitialize = rt2x00pci_uninitialize,
3118 + .get_entry_state = rt2800pci_get_entry_state,
3119 + .clear_entry = rt2800pci_clear_entry,
3120 + .set_device_state = rt2800pci_set_device_state,
3121 + .rfkill_poll = rt2800pci_rfkill_poll,
3122 + .link_stats = rt2800pci_link_stats,
3123 + .reset_tuner = rt2800pci_reset_tuner,
3124 + .link_tuner = rt2800pci_link_tuner,
3125 + .write_tx_desc = rt2800pci_write_tx_desc,
3126 + .write_tx_data = rt2x00pci_write_tx_data,
3127 + .write_beacon = rt2800pci_write_beacon,
3128 + .kick_tx_queue = rt2800pci_kick_tx_queue,
3129 + .kill_tx_queue = rt2800pci_kill_tx_queue,
3130 + .fill_rxdone = rt2800pci_fill_rxdone,
3131 + .config_shared_key = rt2800pci_config_shared_key,
3132 + .config_pairwise_key = rt2800pci_config_pairwise_key,
3133 + .config_filter = rt2800pci_config_filter,
3134 + .config_intf = rt2800pci_config_intf,
3135 + .config_erp = rt2800pci_config_erp,
3136 + .config_ant = rt2800pci_config_ant,
3137 + .config = rt2800pci_config,
3138 +};
3139 +
3140 +static const struct data_queue_desc rt2800pci_queue_rx = {
3141 + .entry_num = RX_ENTRIES,
3142 + .data_size = AGGREGATION_SIZE,
3143 + .desc_size = RXD_DESC_SIZE,
3144 + .priv_size = sizeof(struct queue_entry_priv_pci),
3145 +};
3146 +
3147 +static const struct data_queue_desc rt2800pci_queue_tx = {
3148 + .entry_num = TX_ENTRIES,
3149 + .data_size = AGGREGATION_SIZE,
3150 + .desc_size = TXD_DESC_SIZE,
3151 + .priv_size = sizeof(struct queue_entry_priv_pci),
3152 +};
3153 +
3154 +static const struct data_queue_desc rt2800pci_queue_bcn = {
3155 + .entry_num = 8 * BEACON_ENTRIES,
3156 + .data_size = 0, /* No DMA required for beacons */
3157 + .desc_size = TXWI_DESC_SIZE,
3158 + .priv_size = sizeof(struct queue_entry_priv_pci),
3159 +};
3160 +
3161 +static const struct rt2x00_ops rt2800pci_ops = {
3162 + .name = KBUILD_MODNAME,
3163 + .max_sta_intf = 1,
3164 + .max_ap_intf = 8,
3165 + .eeprom_size = EEPROM_SIZE,
3166 + .rf_size = RF_SIZE,
3167 + .tx_queues = NUM_TX_QUEUES,
3168 + .rx = &rt2800pci_queue_rx,
3169 + .tx = &rt2800pci_queue_tx,
3170 + .bcn = &rt2800pci_queue_bcn,
3171 + .lib = &rt2800pci_rt2x00_ops,
3172 + .hw = &rt2800pci_mac80211_ops,
3173 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3174 + .debugfs = &rt2800pci_rt2x00debug,
3175 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3176 +};
3177 +
3178 +/*
3179 + * RT2800pci module information.
3180 + */
3181 +static struct pci_device_id rt2800pci_device_table[] = {
3182 + /* Edimax */
3183 + { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
3184 + { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
3185 + { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
3186 + { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
3187 + { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
3188 + { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
3189 + { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
3190 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3191 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3192 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3193 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3194 + { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
3195 + { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3196 + { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3197 + { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3198 + { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
3199 + { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
3200 + /* Awt */
3201 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3202 + { 0, }
3203 +};
3204 +
3205 +MODULE_AUTHOR(DRV_PROJECT);
3206 +MODULE_VERSION(DRV_VERSION);
3207 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3208 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3209 +#ifdef CONFIG_RT2800PCI_PCI
3210 +MODULE_FIRMWARE(FIRMWARE_RT2860);
3211 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3212 +#endif /* CONFIG_RT2800PCI_PCI */
3213 +MODULE_LICENSE("GPL");
3214 +
3215 +#ifdef CONFIG_RT2800PCI_WISOC
3216 +#if defined(CONFIG_RALINK_RT288X)
3217 +__rt2x00soc_probe(RT2880, &rt2800pci_ops);
3218 +#elif defined(CONFIG_RALINK_RT305X)
3219 +__rt2x00soc_probe(RT3052, &rt2800pci_ops);
3220 +#endif
3221 +
3222 +static struct platform_driver rt2800soc_driver = {
3223 + .driver = {
3224 + .name = "rt2800_wmac",
3225 + .owner = THIS_MODULE,
3226 + .mod_name = KBUILD_MODNAME,
3227 + },
3228 + .probe = __rt2x00soc_probe,
3229 + .remove = __devexit_p(rt2x00soc_remove),
3230 + .suspend = rt2x00soc_suspend,
3231 + .resume = rt2x00soc_resume,
3232 +};
3233 +#endif /* CONFIG_RT2800PCI_WISOC */
3234 +
3235 +#ifdef CONFIG_RT2800PCI_PCI
3236 +static struct pci_driver rt2800pci_driver = {
3237 + .name = KBUILD_MODNAME,
3238 + .id_table = rt2800pci_device_table,
3239 + .probe = rt2x00pci_probe,
3240 + .remove = __devexit_p(rt2x00pci_remove),
3241 + .suspend = rt2x00pci_suspend,
3242 + .resume = rt2x00pci_resume,
3243 +};
3244 +#endif /* CONFIG_RT2800PCI_PCI */
3245 +
3246 +static int __init rt2800pci_init(void)
3247 +{
3248 + int ret = 0;
3249 +
3250 +#ifdef CONFIG_RT2800PCI_WISOC
3251 + ret = platform_driver_register(&rt2800soc_driver);
3252 + if (ret)
3253 + return ret;
3254 +#endif
3255 +#ifdef CONFIG_RT2800PCI_PCI
3256 + ret = pci_register_driver(&rt2800pci_driver);
3257 + if (ret) {
3258 +#ifdef CONFIG_RT2800PCI_WISOC
3259 + platform_driver_unregister(&rt2800soc_driver);
3260 +#endif
3261 + return ret;
3262 + }
3263 +#endif
3264 +
3265 + return ret;
3266 +}
3267 +
3268 +static void __exit rt2800pci_exit(void)
3269 +{
3270 +#ifdef CONFIG_RT2800PCI_PCI
3271 + pci_unregister_driver(&rt2800pci_driver);
3272 +#endif
3273 +#ifdef CONFIG_RT2800PCI_WISOC
3274 + platform_driver_unregister(&rt2800soc_driver);
3275 +#endif
3276 +}
3277 +
3278 +module_init(rt2800pci_init);
3279 +module_exit(rt2800pci_exit);
3280 --- /dev/null
3281 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
3282 @@ -0,0 +1,1929 @@
3283 +/*
3284 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3285 + <http://rt2x00.serialmonkey.com>
3286 +
3287 + This program is free software; you can redistribute it and/or modify
3288 + it under the terms of the GNU General Public License as published by
3289 + the Free Software Foundation; either version 2 of the License, or
3290 + (at your option) any later version.
3291 +
3292 + This program is distributed in the hope that it will be useful,
3293 + but WITHOUT ANY WARRANTY; without even the implied warranty of
3294 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3295 + GNU General Public License for more details.
3296 +
3297 + You should have received a copy of the GNU General Public License
3298 + along with this program; if not, write to the
3299 + Free Software Foundation, Inc.,
3300 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3301 + */
3302 +
3303 +/*
3304 + Module: rt2800pci
3305 + Abstract: Data structures and registers for the rt2800pci module.
3306 + Supported chipsets: RT2800E & RT2800ED.
3307 + */
3308 +
3309 +#ifndef RT2800PCI_H
3310 +#define RT2800PCI_H
3311 +
3312 +/*
3313 + * RF chip defines.
3314 + *
3315 + * RF2820 2.4G 2T3R
3316 + * RF2850 2.4G/5G 2T3R
3317 + * RF2720 2.4G 1T2R
3318 + * RF2750 2.4G/5G 1T2R
3319 + * RF3020 2.4G 1T1R
3320 + * RF2020 2.4G B/G
3321 + * RF3021 2.4G 1T2R
3322 + * RF3022 2.4G 2T2R
3323 + */
3324 +#define RF2820 0x0001
3325 +#define RF2850 0x0002
3326 +#define RF2720 0x0003
3327 +#define RF2750 0x0004
3328 +#define RF3020 0x0005
3329 +#define RF2020 0x0006
3330 +#define RF3021 0x0007
3331 +#define RF3022 0x0008
3332 +
3333 +/*
3334 + * RT2860 version
3335 + */
3336 +#define RT2860C_VERSION 0x28600100
3337 +#define RT2860D_VERSION 0x28600101
3338 +#define RT2880E_VERSION 0x28720200
3339 +#define RT2883_VERSION 0x28830300
3340 +#define RT3070_VERSION 0x30700200
3341 +
3342 +/*
3343 + * Signal information.
3344 + * Default offset is required for RSSI <-> dBm conversion.
3345 + */
3346 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
3347 +
3348 +/*
3349 + * Register layout information.
3350 + */
3351 +#define CSR_REG_BASE 0x1000
3352 +#define CSR_REG_SIZE 0x0800
3353 +#define EEPROM_BASE 0x0000
3354 +#define EEPROM_SIZE 0x0110
3355 +#define BBP_BASE 0x0000
3356 +#define BBP_SIZE 0x0080
3357 +#define RF_BASE 0x0004
3358 +#define RF_SIZE 0x0010
3359 +
3360 +/*
3361 + * Number of TX queues.
3362 + */
3363 +#define NUM_TX_QUEUES 4
3364 +
3365 +/*
3366 + * PCI registers.
3367 + */
3368 +
3369 +/*
3370 + * E2PROM_CSR: EEPROM control register.
3371 + * RELOAD: Write 1 to reload eeprom content.
3372 + * TYPE: 0: 93c46, 1:93c66.
3373 + * LOAD_STATUS: 1:loading, 0:done.
3374 + */
3375 +#define E2PROM_CSR 0x0004
3376 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
3377 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
3378 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
3379 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
3380 +#define E2PROM_CSR_TYPE FIELD32(0x00000030)
3381 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
3382 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
3383 +
3384 +/*
3385 + * HOST-MCU shared memory
3386 + */
3387 +#define HOST_CMD_CSR 0x0404
3388 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
3389 +
3390 +/*
3391 + * INT_SOURCE_CSR: Interrupt source register.
3392 + * Write one to clear corresponding bit.
3393 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3394 + */
3395 +#define INT_SOURCE_CSR 0x0200
3396 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
3397 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
3398 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
3399 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3400 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3401 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3402 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3403 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3404 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3405 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
3406 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
3407 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
3408 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
3409 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3410 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3411 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3412 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3413 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3414 +
3415 +/*
3416 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3417 + */
3418 +#define INT_MASK_CSR 0x0204
3419 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3420 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3421 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3422 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3423 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3424 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3425 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3426 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3427 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3428 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3429 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3430 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3431 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3432 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3433 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3434 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3435 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3436 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3437 +
3438 +/*
3439 + * WPDMA_GLO_CFG
3440 + */
3441 +#define WPDMA_GLO_CFG 0x0208
3442 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3443 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3444 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3445 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3446 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3447 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3448 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3449 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3450 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3451 +
3452 +/*
3453 + * WPDMA_RST_IDX
3454 + */
3455 +#define WPDMA_RST_IDX 0x020c
3456 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3457 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3458 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3459 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3460 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3461 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3462 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3463 +
3464 +/*
3465 + * DELAY_INT_CFG
3466 + */
3467 +#define DELAY_INT_CFG 0x0210
3468 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3469 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3470 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3471 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3472 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3473 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3474 +
3475 +/*
3476 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3477 + * AIFSN0: AC_BE
3478 + * AIFSN1: AC_BK
3479 + * AIFSN1: AC_VI
3480 + * AIFSN1: AC_VO
3481 + */
3482 +#define WMM_AIFSN_CFG 0x0214
3483 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3484 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3485 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3486 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3487 +
3488 +/*
3489 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3490 + * CWMIN0: AC_BE
3491 + * CWMIN1: AC_BK
3492 + * CWMIN1: AC_VI
3493 + * CWMIN1: AC_VO
3494 + */
3495 +#define WMM_CWMIN_CFG 0x0218
3496 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3497 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3498 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3499 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3500 +
3501 +/*
3502 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3503 + * CWMAX0: AC_BE
3504 + * CWMAX1: AC_BK
3505 + * CWMAX1: AC_VI
3506 + * CWMAX1: AC_VO
3507 + */
3508 +#define WMM_CWMAX_CFG 0x021c
3509 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3510 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3511 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3512 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3513 +
3514 +/*
3515 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3516 + * AC0TXOP: AC_BK in unit of 32us
3517 + * AC1TXOP: AC_BE in unit of 32us
3518 + */
3519 +#define WMM_TXOP0_CFG 0x0220
3520 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3521 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3522 +
3523 +/*
3524 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3525 + * AC2TXOP: AC_VI in unit of 32us
3526 + * AC3TXOP: AC_VO in unit of 32us
3527 + */
3528 +#define WMM_TXOP1_CFG 0x0224
3529 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3530 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3531 +
3532 +/*
3533 + * GPIO_CTRL_CFG:
3534 + */
3535 +#define GPIO_CTRL_CFG 0x0228
3536 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3537 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3538 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3539 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3540 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3541 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3542 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3543 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3544 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3545 +
3546 +/*
3547 + * MCU_CMD_CFG
3548 + */
3549 +#define MCU_CMD_CFG 0x022c
3550 +
3551 +/*
3552 + * AC_BK register offsets
3553 + */
3554 +#define TX_BASE_PTR0 0x0230
3555 +#define TX_MAX_CNT0 0x0234
3556 +#define TX_CTX_IDX0 0x0238
3557 +#define TX_DTX_IDX0 0x023c
3558 +
3559 +/*
3560 + * AC_BE register offsets
3561 + */
3562 +#define TX_BASE_PTR1 0x0240
3563 +#define TX_MAX_CNT1 0x0244
3564 +#define TX_CTX_IDX1 0x0248
3565 +#define TX_DTX_IDX1 0x024c
3566 +
3567 +/*
3568 + * AC_VI register offsets
3569 + */
3570 +#define TX_BASE_PTR2 0x0250
3571 +#define TX_MAX_CNT2 0x0254
3572 +#define TX_CTX_IDX2 0x0258
3573 +#define TX_DTX_IDX2 0x025c
3574 +
3575 +/*
3576 + * AC_VO register offsets
3577 + */
3578 +#define TX_BASE_PTR3 0x0260
3579 +#define TX_MAX_CNT3 0x0264
3580 +#define TX_CTX_IDX3 0x0268
3581 +#define TX_DTX_IDX3 0x026c
3582 +
3583 +/*
3584 + * HCCA register offsets
3585 + */
3586 +#define TX_BASE_PTR4 0x0270
3587 +#define TX_MAX_CNT4 0x0274
3588 +#define TX_CTX_IDX4 0x0278
3589 +#define TX_DTX_IDX4 0x027c
3590 +
3591 +/*
3592 + * MGMT register offsets
3593 + */
3594 +#define TX_BASE_PTR5 0x0280
3595 +#define TX_MAX_CNT5 0x0284
3596 +#define TX_CTX_IDX5 0x0288
3597 +#define TX_DTX_IDX5 0x028c
3598 +
3599 +/*
3600 + * Queue register offset macros
3601 + */
3602 +#define TX_QUEUE_REG_OFFSET 0x10
3603 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3604 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3605 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3606 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3607 +
3608 +/*
3609 + * RX register offsets
3610 + */
3611 +#define RX_BASE_PTR 0x0290
3612 +#define RX_MAX_CNT 0x0294
3613 +#define RX_CRX_IDX 0x0298
3614 +#define RX_DRX_IDX 0x029c
3615 +
3616 +/*
3617 + * PBF_SYS_CTRL
3618 + * HOST_RAM_WRITE: enable Host program ram write selection
3619 + */
3620 +#define PBF_SYS_CTRL 0x0400
3621 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3622 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3623 +
3624 +/*
3625 + * PBF registers
3626 + * Most are for debug. Driver doesn't touch PBF register.
3627 + */
3628 +#define PBF_CFG 0x0408
3629 +#define PBF_MAX_PCNT 0x040c
3630 +#define PBF_CTRL 0x0410
3631 +#define PBF_INT_STA 0x0414
3632 +#define PBF_INT_ENA 0x0418
3633 +
3634 +/*
3635 + * BCN_OFFSET0:
3636 + */
3637 +#define BCN_OFFSET0 0x042c
3638 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3639 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3640 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3641 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3642 +
3643 +/*
3644 + * BCN_OFFSET1:
3645 + */
3646 +#define BCN_OFFSET1 0x0430
3647 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3648 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3649 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3650 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3651 +
3652 +/*
3653 + * PBF registers
3654 + * Most are for debug. Driver doesn't touch PBF register.
3655 + */
3656 +#define TXRXQ_PCNT 0x0438
3657 +#define PBF_DBG 0x043c
3658 +
3659 +/*
3660 + * RF registers
3661 + */
3662 +#define RF_CSR_CFG 0x0500
3663 +#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
3664 +#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
3665 +#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
3666 +#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
3667 +
3668 +/*
3669 + * MAC Control/Status Registers(CSR).
3670 + * Some values are set in TU, whereas 1 TU == 1024 us.
3671 + */
3672 +
3673 +/*
3674 + * MAC_CSR0: ASIC revision number.
3675 + * ASIC_REV: 0
3676 + * ASIC_VER: 2860
3677 + */
3678 +#define MAC_CSR0 0x1000
3679 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3680 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3681 +
3682 +/*
3683 + * MAC_SYS_CTRL:
3684 + */
3685 +#define MAC_SYS_CTRL 0x1004
3686 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3687 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3688 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3689 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3690 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3691 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3692 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3693 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3694 +
3695 +/*
3696 + * MAC_ADDR_DW0: STA MAC register 0
3697 + */
3698 +#define MAC_ADDR_DW0 0x1008
3699 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3700 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3701 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3702 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3703 +
3704 +/*
3705 + * MAC_ADDR_DW1: STA MAC register 1
3706 + * UNICAST_TO_ME_MASK:
3707 + * Used to mask off bits from byte 5 of the MAC address
3708 + * to determine the UNICAST_TO_ME bit for RX frames.
3709 + * The full mask is complemented by BSS_ID_MASK:
3710 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3711 + */
3712 +#define MAC_ADDR_DW1 0x100c
3713 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3714 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3715 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3716 +
3717 +/*
3718 + * MAC_BSSID_DW0: BSSID register 0
3719 + */
3720 +#define MAC_BSSID_DW0 0x1010
3721 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3722 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3723 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3724 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3725 +
3726 +/*
3727 + * MAC_BSSID_DW1: BSSID register 1
3728 + * BSS_ID_MASK:
3729 + * 0: 1-BSSID mode (BSS index = 0)
3730 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3731 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3732 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3733 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3734 + * BSSID. This will make sure that those bits will be ignored
3735 + * when determining the MY_BSS of RX frames.
3736 + */
3737 +#define MAC_BSSID_DW1 0x1014
3738 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3739 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3740 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3741 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3742 +
3743 +/*
3744 + * MAX_LEN_CFG: Maximum frame length register.
3745 + * MAX_MPDU: rt2860b max 16k bytes
3746 + * MAX_PSDU: Maximum PSDU length
3747 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3748 + */
3749 +#define MAX_LEN_CFG 0x1018
3750 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3751 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3752 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3753 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3754 +
3755 +/*
3756 + * BBP_CSR_CFG: BBP serial control register
3757 + * VALUE: Register value to program into BBP
3758 + * REG_NUM: Selected BBP register
3759 + * READ_CONTROL: 0 write BBP, 1 read BBP
3760 + * BUSY: ASIC is busy executing BBP commands
3761 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3762 + * BBP_RW_MODE: 0 serial, 1 paralell
3763 + */
3764 +#define BBP_CSR_CFG 0x101c
3765 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3766 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3767 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3768 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3769 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3770 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3771 +
3772 +/*
3773 + * RF_CSR_CFG0: RF control register
3774 + * REGID_AND_VALUE: Register value to program into RF
3775 + * BITWIDTH: Selected RF register
3776 + * STANDBYMODE: 0 high when standby, 1 low when standby
3777 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3778 + * BUSY: ASIC is busy executing RF commands
3779 + */
3780 +#define RF_CSR_CFG0 0x1020
3781 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3782 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3783 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3784 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3785 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3786 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3787 +
3788 +/*
3789 + * RF_CSR_CFG1: RF control register
3790 + * REGID_AND_VALUE: Register value to program into RF
3791 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3792 + * 0: 3 system clock cycle (37.5usec)
3793 + * 1: 5 system clock cycle (62.5usec)
3794 + */
3795 +#define RF_CSR_CFG1 0x1024
3796 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3797 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3798 +
3799 +/*
3800 + * RF_CSR_CFG2: RF control register
3801 + * VALUE: Register value to program into RF
3802 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3803 + * 0: 3 system clock cycle (37.5usec)
3804 + * 1: 5 system clock cycle (62.5usec)
3805 + */
3806 +#define RF_CSR_CFG2 0x1028
3807 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3808 +
3809 +/*
3810 + * LED_CFG: LED control
3811 + * color LED's:
3812 + * 0: off
3813 + * 1: blinking upon TX2
3814 + * 2: periodic slow blinking
3815 + * 3: always on
3816 + * LED polarity:
3817 + * 0: active low
3818 + * 1: active high
3819 + */
3820 +#define LED_CFG 0x102c
3821 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3822 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3823 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3824 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3825 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3826 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3827 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3828 +
3829 +/*
3830 + * XIFS_TIME_CFG: MAC timing
3831 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3832 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3833 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3834 + * when MAC doesn't reference BBP signal BBRXEND
3835 + * EIFS: unit 1us
3836 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3837 + *
3838 + */
3839 +#define XIFS_TIME_CFG 0x1100
3840 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3841 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3842 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3843 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3844 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3845 +
3846 +/*
3847 + * BKOFF_SLOT_CFG:
3848 + */
3849 +#define BKOFF_SLOT_CFG 0x1104
3850 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3851 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3852 +
3853 +/*
3854 + * NAV_TIME_CFG:
3855 + */
3856 +#define NAV_TIME_CFG 0x1108
3857 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3858 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3859 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3860 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3861 +
3862 +/*
3863 + * CH_TIME_CFG: count as channel busy
3864 + */
3865 +#define CH_TIME_CFG 0x110c
3866 +
3867 +/*
3868 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3869 + */
3870 +#define PBF_LIFE_TIMER 0x1110
3871 +
3872 +/*
3873 + * BCN_TIME_CFG:
3874 + * BEACON_INTERVAL: in unit of 1/16 TU
3875 + * TSF_TICKING: Enable TSF auto counting
3876 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3877 + * BEACON_GEN: Enable beacon generator
3878 + */
3879 +#define BCN_TIME_CFG 0x1114
3880 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3881 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3882 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3883 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3884 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3885 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3886 +
3887 +/*
3888 + * TBTT_SYNC_CFG:
3889 + */
3890 +#define TBTT_SYNC_CFG 0x1118
3891 +
3892 +/*
3893 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3894 + */
3895 +#define TSF_TIMER_DW0 0x111c
3896 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3897 +
3898 +/*
3899 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3900 + */
3901 +#define TSF_TIMER_DW1 0x1120
3902 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3903 +
3904 +/*
3905 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3906 + */
3907 +#define TBTT_TIMER 0x1124
3908 +
3909 +/*
3910 + * INT_TIMER_CFG:
3911 + */
3912 +#define INT_TIMER_CFG 0x1128
3913 +
3914 +/*
3915 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3916 + */
3917 +#define INT_TIMER_EN 0x112c
3918 +
3919 +/*
3920 + * CH_IDLE_STA: channel idle time
3921 + */
3922 +#define CH_IDLE_STA 0x1130
3923 +
3924 +/*
3925 + * CH_BUSY_STA: channel busy time
3926 + */
3927 +#define CH_BUSY_STA 0x1134
3928 +
3929 +/*
3930 + * MAC_STATUS_CFG:
3931 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3932 + * if 1 or higher one of the 2 registers is busy.
3933 + */
3934 +#define MAC_STATUS_CFG 0x1200
3935 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3936 +
3937 +/*
3938 + * PWR_PIN_CFG:
3939 + */
3940 +#define PWR_PIN_CFG 0x1204
3941 +
3942 +/*
3943 + * AUTOWAKEUP_CFG: Manual power control / status register
3944 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3945 + * AUTOWAKE: 0:sleep, 1:awake
3946 + */
3947 +#define AUTOWAKEUP_CFG 0x1208
3948 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3949 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3950 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3951 +
3952 +/*
3953 + * EDCA_AC0_CFG:
3954 + */
3955 +#define EDCA_AC0_CFG 0x1300
3956 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3957 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3958 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3959 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3960 +
3961 +/*
3962 + * EDCA_AC1_CFG:
3963 + */
3964 +#define EDCA_AC1_CFG 0x1304
3965 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3966 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3967 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3968 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3969 +
3970 +/*
3971 + * EDCA_AC2_CFG:
3972 + */
3973 +#define EDCA_AC2_CFG 0x1308
3974 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3975 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3976 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3977 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3978 +
3979 +/*
3980 + * EDCA_AC3_CFG:
3981 + */
3982 +#define EDCA_AC3_CFG 0x130c
3983 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3984 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3985 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3986 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3987 +
3988 +/*
3989 + * EDCA_TID_AC_MAP:
3990 + */
3991 +#define EDCA_TID_AC_MAP 0x1310
3992 +
3993 +/*
3994 + * TX_PWR_CFG_0:
3995 + */
3996 +#define TX_PWR_CFG_0 0x1314
3997 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3998 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3999 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
4000 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
4001 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
4002 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
4003 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
4004 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
4005 +
4006 +/*
4007 + * TX_PWR_CFG_1:
4008 + */
4009 +#define TX_PWR_CFG_1 0x1318
4010 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
4011 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
4012 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
4013 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
4014 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
4015 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
4016 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
4017 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
4018 +
4019 +/*
4020 + * TX_PWR_CFG_2:
4021 + */
4022 +#define TX_PWR_CFG_2 0x131c
4023 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
4024 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
4025 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
4026 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
4027 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
4028 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
4029 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
4030 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
4031 +
4032 +/*
4033 + * TX_PWR_CFG_3:
4034 + */
4035 +#define TX_PWR_CFG_3 0x1320
4036 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
4037 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
4038 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
4039 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
4040 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
4041 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
4042 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
4043 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
4044 +
4045 +/*
4046 + * TX_PWR_CFG_4:
4047 + */
4048 +#define TX_PWR_CFG_4 0x1324
4049 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
4050 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
4051 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
4052 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
4053 +
4054 +/*
4055 + * TX_PIN_CFG:
4056 + */
4057 +#define TX_PIN_CFG 0x1328
4058 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
4059 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
4060 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
4061 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
4062 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
4063 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
4064 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
4065 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
4066 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
4067 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
4068 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
4069 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
4070 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
4071 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
4072 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
4073 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
4074 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
4075 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
4076 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
4077 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
4078 +
4079 +/*
4080 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
4081 + */
4082 +#define TX_BAND_CFG 0x132c
4083 +#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
4084 +#define TX_BAND_CFG_A FIELD32(0x00000002)
4085 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
4086 +
4087 +/*
4088 + * TX_SW_CFG0:
4089 + */
4090 +#define TX_SW_CFG0 0x1330
4091 +
4092 +/*
4093 + * TX_SW_CFG1:
4094 + */
4095 +#define TX_SW_CFG1 0x1334
4096 +
4097 +/*
4098 + * TX_SW_CFG2:
4099 + */
4100 +#define TX_SW_CFG2 0x1338
4101 +
4102 +/*
4103 + * TXOP_THRES_CFG:
4104 + */
4105 +#define TXOP_THRES_CFG 0x133c
4106 +
4107 +/*
4108 + * TXOP_CTRL_CFG:
4109 + */
4110 +#define TXOP_CTRL_CFG 0x1340
4111 +
4112 +/*
4113 + * TX_RTS_CFG:
4114 + * RTS_THRES: unit:byte
4115 + * RTS_FBK_EN: enable rts rate fallback
4116 + */
4117 +#define TX_RTS_CFG 0x1344
4118 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
4119 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
4120 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
4121 +
4122 +/*
4123 + * TX_TIMEOUT_CFG:
4124 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
4125 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
4126 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
4127 + * it is recommended that:
4128 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
4129 + */
4130 +#define TX_TIMEOUT_CFG 0x1348
4131 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
4132 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
4133 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
4134 +
4135 +/*
4136 + * TX_RTY_CFG:
4137 + * SHORT_RTY_LIMIT: short retry limit
4138 + * LONG_RTY_LIMIT: long retry limit
4139 + * LONG_RTY_THRE: Long retry threshoold
4140 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
4141 + * 0:expired by retry limit, 1: expired by mpdu life timer
4142 + * AGG_RTY_MODE: Aggregate MPDU retry mode
4143 + * 0:expired by retry limit, 1: expired by mpdu life timer
4144 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
4145 + */
4146 +#define TX_RTY_CFG 0x134c
4147 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
4148 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
4149 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
4150 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
4151 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
4152 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
4153 +
4154 +/*
4155 + * TX_LINK_CFG:
4156 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
4157 + * MFB_ENABLE: TX apply remote MFB 1:enable
4158 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
4159 + * 0: not apply remote remote unsolicit (MFS=7)
4160 + * TX_MRQ_EN: MCS request TX enable
4161 + * TX_RDG_EN: RDG TX enable
4162 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
4163 + * REMOTE_MFB: remote MCS feedback
4164 + * REMOTE_MFS: remote MCS feedback sequence number
4165 + */
4166 +#define TX_LINK_CFG 0x1350
4167 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
4168 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
4169 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
4170 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
4171 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
4172 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
4173 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
4174 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
4175 +
4176 +/*
4177 + * HT_FBK_CFG0:
4178 + */
4179 +#define HT_FBK_CFG0 0x1354
4180 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
4181 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
4182 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
4183 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
4184 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
4185 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
4186 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
4187 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
4188 +
4189 +/*
4190 + * HT_FBK_CFG1:
4191 + */
4192 +#define HT_FBK_CFG1 0x1358
4193 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
4194 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
4195 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
4196 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
4197 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
4198 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
4199 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
4200 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
4201 +
4202 +/*
4203 + * LG_FBK_CFG0:
4204 + */
4205 +#define LG_FBK_CFG0 0x135c
4206 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
4207 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
4208 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
4209 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
4210 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
4211 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
4212 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
4213 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
4214 +
4215 +/*
4216 + * LG_FBK_CFG1:
4217 + */
4218 +#define LG_FBK_CFG1 0x1360
4219 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
4220 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
4221 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
4222 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
4223 +
4224 +/*
4225 + * CCK_PROT_CFG: CCK Protection
4226 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4227 + * PROTECT_CTRL: Protection control frame type for CCK TX
4228 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
4229 + * PROTECT_NAV: TXOP protection type for CCK TX
4230 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4231 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4232 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4233 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4234 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4235 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4236 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4237 + * RTS_TH_EN: RTS threshold enable on CCK TX
4238 + */
4239 +#define CCK_PROT_CFG 0x1364
4240 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4241 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4242 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4243 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4244 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4245 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4246 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4247 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4248 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4249 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4250 +
4251 +/*
4252 + * OFDM_PROT_CFG: OFDM Protection
4253 + */
4254 +#define OFDM_PROT_CFG 0x1368
4255 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4256 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4257 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4258 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4259 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4260 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4261 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4262 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4263 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4264 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4265 +
4266 +/*
4267 + * MM20_PROT_CFG: MM20 Protection
4268 + */
4269 +#define MM20_PROT_CFG 0x136c
4270 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4271 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4272 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4273 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4274 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4275 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4276 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4277 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4278 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4279 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4280 +
4281 +/*
4282 + * MM40_PROT_CFG: MM40 Protection
4283 + */
4284 +#define MM40_PROT_CFG 0x1370
4285 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4286 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4287 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4288 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4289 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4290 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4291 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4292 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4293 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4294 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4295 +
4296 +/*
4297 + * GF20_PROT_CFG: GF20 Protection
4298 + */
4299 +#define GF20_PROT_CFG 0x1374
4300 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4301 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4302 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4303 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4304 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4305 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4306 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4307 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4308 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4309 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4310 +
4311 +/*
4312 + * GF40_PROT_CFG: GF40 Protection
4313 + */
4314 +#define GF40_PROT_CFG 0x1378
4315 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4316 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4317 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4318 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4319 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4320 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4321 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4322 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4323 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4324 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4325 +
4326 +/*
4327 + * EXP_CTS_TIME:
4328 + */
4329 +#define EXP_CTS_TIME 0x137c
4330 +
4331 +/*
4332 + * EXP_ACK_TIME:
4333 + */
4334 +#define EXP_ACK_TIME 0x1380
4335 +
4336 +/*
4337 + * RX_FILTER_CFG: RX configuration register.
4338 + */
4339 +#define RX_FILTER_CFG 0x1400
4340 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
4341 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
4342 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
4343 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4344 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
4345 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
4346 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
4347 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
4348 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
4349 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
4350 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
4351 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
4352 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
4353 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
4354 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
4355 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
4356 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
4357 +
4358 +/*
4359 + * AUTO_RSP_CFG:
4360 + * AUTORESPONDER: 0: disable, 1: enable
4361 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4362 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4363 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4364 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4365 + * DUAL_CTS_EN: Power bit value in control frame
4366 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4367 + */
4368 +#define AUTO_RSP_CFG 0x1404
4369 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
4370 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
4371 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
4372 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
4373 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
4374 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
4375 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
4376 +
4377 +/*
4378 + * LEGACY_BASIC_RATE:
4379 + */
4380 +#define LEGACY_BASIC_RATE 0x1408
4381 +
4382 +/*
4383 + * HT_BASIC_RATE:
4384 + */
4385 +#define HT_BASIC_RATE 0x140c
4386 +
4387 +/*
4388 + * HT_CTRL_CFG:
4389 + */
4390 +#define HT_CTRL_CFG 0x1410
4391 +
4392 +/*
4393 + * SIFS_COST_CFG:
4394 + */
4395 +#define SIFS_COST_CFG 0x1414
4396 +
4397 +/*
4398 + * RX_PARSER_CFG:
4399 + * Set NAV for all received frames
4400 + */
4401 +#define RX_PARSER_CFG 0x1418
4402 +
4403 +/*
4404 + * TX_SEC_CNT0:
4405 + */
4406 +#define TX_SEC_CNT0 0x1500
4407 +
4408 +/*
4409 + * RX_SEC_CNT0:
4410 + */
4411 +#define RX_SEC_CNT0 0x1504
4412 +
4413 +/*
4414 + * CCMP_FC_MUTE:
4415 + */
4416 +#define CCMP_FC_MUTE 0x1508
4417 +
4418 +/*
4419 + * TXOP_HLDR_ADDR0:
4420 + */
4421 +#define TXOP_HLDR_ADDR0 0x1600
4422 +
4423 +/*
4424 + * TXOP_HLDR_ADDR1:
4425 + */
4426 +#define TXOP_HLDR_ADDR1 0x1604
4427 +
4428 +/*
4429 + * TXOP_HLDR_ET:
4430 + */
4431 +#define TXOP_HLDR_ET 0x1608
4432 +
4433 +/*
4434 + * QOS_CFPOLL_RA_DW0:
4435 + */
4436 +#define QOS_CFPOLL_RA_DW0 0x160c
4437 +
4438 +/*
4439 + * QOS_CFPOLL_RA_DW1:
4440 + */
4441 +#define QOS_CFPOLL_RA_DW1 0x1610
4442 +
4443 +/*
4444 + * QOS_CFPOLL_QC:
4445 + */
4446 +#define QOS_CFPOLL_QC 0x1614
4447 +
4448 +/*
4449 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4450 + */
4451 +#define RX_STA_CNT0 0x1700
4452 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4453 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4454 +
4455 +/*
4456 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4457 + */
4458 +#define RX_STA_CNT1 0x1704
4459 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4460 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4461 +
4462 +/*
4463 + * RX_STA_CNT2:
4464 + */
4465 +#define RX_STA_CNT2 0x1708
4466 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4467 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4468 +
4469 +/*
4470 + * TX_STA_CNT0: TX Beacon count
4471 + */
4472 +#define TX_STA_CNT0 0x170c
4473 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4474 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4475 +
4476 +/*
4477 + * TX_STA_CNT1: TX tx count
4478 + */
4479 +#define TX_STA_CNT1 0x1710
4480 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4481 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4482 +
4483 +/*
4484 + * TX_STA_CNT2: TX tx count
4485 + */
4486 +#define TX_STA_CNT2 0x1714
4487 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4488 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4489 +
4490 +/*
4491 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4492 + */
4493 +#define TX_STA_FIFO 0x1718
4494 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4495 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4496 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4497 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4498 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4499 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4500 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4501 +
4502 +/*
4503 + * TX_AGG_CNT: Debug counter
4504 + */
4505 +#define TX_AGG_CNT 0x171c
4506 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4507 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4508 +
4509 +/*
4510 + * TX_AGG_CNT0:
4511 + */
4512 +#define TX_AGG_CNT0 0x1720
4513 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4514 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4515 +
4516 +/*
4517 + * TX_AGG_CNT1:
4518 + */
4519 +#define TX_AGG_CNT1 0x1724
4520 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4521 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4522 +
4523 +/*
4524 + * TX_AGG_CNT2:
4525 + */
4526 +#define TX_AGG_CNT2 0x1728
4527 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4528 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4529 +
4530 +/*
4531 + * TX_AGG_CNT3:
4532 + */
4533 +#define TX_AGG_CNT3 0x172c
4534 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4535 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4536 +
4537 +/*
4538 + * TX_AGG_CNT4:
4539 + */
4540 +#define TX_AGG_CNT4 0x1730
4541 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4542 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4543 +
4544 +/*
4545 + * TX_AGG_CNT5:
4546 + */
4547 +#define TX_AGG_CNT5 0x1734
4548 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4549 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4550 +
4551 +/*
4552 + * TX_AGG_CNT6:
4553 + */
4554 +#define TX_AGG_CNT6 0x1738
4555 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4556 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4557 +
4558 +/*
4559 + * TX_AGG_CNT7:
4560 + */
4561 +#define TX_AGG_CNT7 0x173c
4562 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4563 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4564 +
4565 +/*
4566 + * MPDU_DENSITY_CNT:
4567 + * TX_ZERO_DEL: TX zero length delimiter count
4568 + * RX_ZERO_DEL: RX zero length delimiter count
4569 + */
4570 +#define MPDU_DENSITY_CNT 0x1740
4571 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4572 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4573 +
4574 +/*
4575 + * Security key table memory.
4576 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4577 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4578 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4579 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4580 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4581 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4582 + */
4583 +#define MAC_WCID_BASE 0x1800
4584 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4585 +#define MAC_IVEIV_TABLE_BASE 0x6000
4586 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4587 +#define SHARED_KEY_TABLE_BASE 0x6c00
4588 +#define SHARED_KEY_MODE_BASE 0x7000
4589 +
4590 +#define MAC_WCID_ENTRY(__idx) \
4591 + ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4592 +#define PAIRWISE_KEY_ENTRY(__idx) \
4593 + ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4594 +#define MAC_IVEIV_ENTRY(__idx) \
4595 + ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4596 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4597 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4598 +#define SHARED_KEY_ENTRY(__idx) \
4599 + ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4600 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4601 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4602 +
4603 +struct mac_wcid_entry {
4604 + u8 mac[6];
4605 + u8 reserved[2];
4606 +} __attribute__ ((packed));
4607 +
4608 +struct hw_key_entry {
4609 + u8 key[16];
4610 + u8 tx_mic[8];
4611 + u8 rx_mic[8];
4612 +} __attribute__ ((packed));
4613 +
4614 +struct mac_iveiv_entry {
4615 + u8 iv[8];
4616 +} __attribute__ ((packed));
4617 +
4618 +/*
4619 + * MAC_WCID_ATTRIBUTE:
4620 + */
4621 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4622 +#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
4623 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4624 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4625 +
4626 +/*
4627 + * SHARED_KEY_MODE:
4628 + */
4629 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4630 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4631 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4632 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4633 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4634 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4635 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4636 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4637 +
4638 +/*
4639 + * HOST-MCU communication
4640 + */
4641 +
4642 +/*
4643 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4644 + */
4645 +#define H2M_MAILBOX_CSR 0x7010
4646 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4647 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4648 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4649 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4650 +
4651 +/*
4652 + * H2M_MAILBOX_CID:
4653 + */
4654 +#define H2M_MAILBOX_CID 0x7014
4655 +#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
4656 +#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
4657 +#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
4658 +#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
4659 +
4660 +/*
4661 + * H2M_MAILBOX_STATUS:
4662 + */
4663 +#define H2M_MAILBOX_STATUS 0x701c
4664 +
4665 +/*
4666 + * H2M_INT_SRC:
4667 + */
4668 +#define H2M_INT_SRC 0x7024
4669 +
4670 +/*
4671 + * H2M_BBP_AGENT:
4672 + */
4673 +#define H2M_BBP_AGENT 0x7028
4674 +
4675 +/*
4676 + * MCU_LEDCS: LED control for MCU Mailbox.
4677 + */
4678 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4679 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4680 +
4681 +/*
4682 + * HW_CS_CTS_BASE:
4683 + * Carrier-sense CTS frame base address.
4684 + * It's where mac stores carrier-sense frame for carrier-sense function.
4685 + */
4686 +#define HW_CS_CTS_BASE 0x7700
4687 +
4688 +/*
4689 + * HW_DFS_CTS_BASE:
4690 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4691 + */
4692 +#define HW_DFS_CTS_BASE 0x7780
4693 +
4694 +/*
4695 + * TXRX control registers - base address 0x3000
4696 + */
4697 +
4698 +/*
4699 + * TXRX_CSR1:
4700 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4701 + */
4702 +#define TXRX_CSR1 0x77d0
4703 +
4704 +/*
4705 + * HW_DEBUG_SETTING_BASE:
4706 + * since NULL frame won't be that long (256 byte)
4707 + * We steal 16 tail bytes to save debugging settings
4708 + */
4709 +#define HW_DEBUG_SETTING_BASE 0x77f0
4710 +#define HW_DEBUG_SETTING_BASE2 0x7770
4711 +
4712 +/*
4713 + * HW_BEACON_BASE
4714 + * In order to support maximum 8 MBSS and its maximum length
4715 + * is 512 bytes for each beacon
4716 + * Three section discontinue memory segments will be used.
4717 + * 1. The original region for BCN 0~3
4718 + * 2. Extract memory from FCE table for BCN 4~5
4719 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4720 + * It occupied those memory of wcid 238~253 for BCN 6
4721 + * and wcid 222~237 for BCN 7
4722 + *
4723 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4724 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4725 + */
4726 +#define HW_BEACON_BASE0 0x7800
4727 +#define HW_BEACON_BASE1 0x7a00
4728 +#define HW_BEACON_BASE2 0x7c00
4729 +#define HW_BEACON_BASE3 0x7e00
4730 +#define HW_BEACON_BASE4 0x7200
4731 +#define HW_BEACON_BASE5 0x7400
4732 +#define HW_BEACON_BASE6 0x5dc0
4733 +#define HW_BEACON_BASE7 0x5bc0
4734 +
4735 +#define HW_BEACON_OFFSET(__index) \
4736 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4737 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4738 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4739 +
4740 +/*
4741 + * 8051 firmware image.
4742 + */
4743 +#define FIRMWARE_RT2860 "rt2860.bin"
4744 +#define FIRMWARE_IMAGE_BASE 0x2000
4745 +
4746 +/*
4747 + * BBP registers.
4748 + * The wordsize of the BBP is 8 bits.
4749 + */
4750 +
4751 +/*
4752 + * BBP 1: TX Antenna
4753 + */
4754 +#define BBP1_TX_POWER FIELD8(0x07)
4755 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4756 +
4757 +/*
4758 + * BBP 3: RX Antenna
4759 + */
4760 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4761 +#define BBP3_HT40_PLUS FIELD8(0x20)
4762 +
4763 +/*
4764 + * BBP 4: Bandwidth
4765 + */
4766 +#define BBP4_TX_BF FIELD8(0x01)
4767 +#define BBP4_BANDWIDTH FIELD8(0x18)
4768 +
4769 +/*
4770 + * RFCSR registers
4771 + * The wordsize of the RFCSR is 8 bits.
4772 + */
4773 +
4774 +/*
4775 + * RFCSR 6:
4776 + */
4777 +#define RFCSR6_R FIELD8(0x03)
4778 +
4779 +/*
4780 + * RFCSR 7:
4781 + */
4782 +#define RFCSR7_RF_TUNING FIELD8(0x01)
4783 +
4784 +/*
4785 + * RFCSR 12:
4786 + */
4787 +#define RFCSR12_TX_POWER FIELD8(0x1f)
4788 +
4789 +/*
4790 + * RFCSR 22:
4791 + */
4792 +#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
4793 +
4794 +/*
4795 + * RFCSR 23:
4796 + */
4797 +#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
4798 +
4799 +/*
4800 + * RFCSR 30:
4801 + */
4802 +#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
4803 +
4804 +/*
4805 + * RF registers
4806 + */
4807 +
4808 +/*
4809 + * RF 2
4810 + */
4811 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4812 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4813 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4814 +
4815 +/*
4816 + * RF 3
4817 + */
4818 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4819 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4820 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4821 +
4822 +/*
4823 + * RF 4
4824 + */
4825 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4826 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4827 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4828 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4829 +#define RF4_HT40 FIELD32(0x00200000)
4830 +
4831 +/*
4832 + * EEPROM content.
4833 + * The wordsize of the EEPROM is 16 bits.
4834 + */
4835 +
4836 +/*
4837 + * EEPROM Version
4838 + */
4839 +#define EEPROM_VERSION 0x0001
4840 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4841 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4842 +
4843 +/*
4844 + * HW MAC address.
4845 + */
4846 +#define EEPROM_MAC_ADDR_0 0x0002
4847 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4848 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4849 +#define EEPROM_MAC_ADDR_1 0x0003
4850 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4851 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4852 +#define EEPROM_MAC_ADDR_2 0x0004
4853 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4854 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4855 +
4856 +/*
4857 + * EEPROM ANTENNA config
4858 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4859 + * TXPATH: 1: 1T, 2: 2T
4860 + */
4861 +#define EEPROM_ANTENNA 0x001a
4862 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4863 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4864 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4865 +
4866 +/*
4867 + * EEPROM NIC config
4868 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4869 + */
4870 +#define EEPROM_NIC 0x001b
4871 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4872 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4873 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4874 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4875 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4876 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4877 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4878 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4879 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4880 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4881 +
4882 +/*
4883 + * EEPROM frequency
4884 + */
4885 +#define EEPROM_FREQ 0x001d
4886 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4887 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4888 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4889 +
4890 +/*
4891 + * EEPROM LED
4892 + * POLARITY_RDY_G: Polarity RDY_G setting.
4893 + * POLARITY_RDY_A: Polarity RDY_A setting.
4894 + * POLARITY_ACT: Polarity ACT setting.
4895 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4896 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4897 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4898 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4899 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4900 + * LED_MODE: Led mode.
4901 + */
4902 +#define EEPROM_LED1 0x001e
4903 +#define EEPROM_LED2 0x001f
4904 +#define EEPROM_LED3 0x0020
4905 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4906 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4907 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4908 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4909 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4910 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4911 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4912 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4913 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4914 +
4915 +/*
4916 + * EEPROM LNA
4917 + */
4918 +#define EEPROM_LNA 0x0022
4919 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4920 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4921 +
4922 +/*
4923 + * EEPROM RSSI BG offset
4924 + */
4925 +#define EEPROM_RSSI_BG 0x0023
4926 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4927 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4928 +
4929 +/*
4930 + * EEPROM RSSI BG2 offset
4931 + */
4932 +#define EEPROM_RSSI_BG2 0x0024
4933 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4934 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4935 +
4936 +/*
4937 + * EEPROM RSSI A offset
4938 + */
4939 +#define EEPROM_RSSI_A 0x0025
4940 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4941 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4942 +
4943 +/*
4944 + * EEPROM RSSI A2 offset
4945 + */
4946 +#define EEPROM_RSSI_A2 0x0026
4947 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4948 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4949 +
4950 +/*
4951 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4952 + * This is delta in 40MHZ.
4953 + * VALUE: Tx Power dalta value (MAX=4)
4954 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4955 + * TXPOWER: Enable:
4956 + */
4957 +#define EEPROM_TXPOWER_DELTA 0x0028
4958 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4959 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4960 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4961 +
4962 +/*
4963 + * EEPROM TXPOWER 802.11BG
4964 + */
4965 +#define EEPROM_TXPOWER_BG1 0x0029
4966 +#define EEPROM_TXPOWER_BG2 0x0030
4967 +#define EEPROM_TXPOWER_BG_SIZE 7
4968 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4969 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4970 +
4971 +/*
4972 + * EEPROM TXPOWER 802.11A
4973 + */
4974 +#define EEPROM_TXPOWER_A1 0x003c
4975 +#define EEPROM_TXPOWER_A2 0x0053
4976 +#define EEPROM_TXPOWER_A_SIZE 6
4977 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4978 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4979 +
4980 +/*
4981 + * EEPROM TXpower byrate: 20MHZ power
4982 + */
4983 +#define EEPROM_TXPOWER_BYRATE 0x006f
4984 +
4985 +/*
4986 + * EEPROM BBP.
4987 + */
4988 +#define EEPROM_BBP_START 0x0078
4989 +#define EEPROM_BBP_SIZE 16
4990 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4991 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4992 +
4993 +/*
4994 + * MCU mailbox commands.
4995 + */
4996 +#define MCU_SLEEP 0x30
4997 +#define MCU_WAKEUP 0x31
4998 +#define MCU_RADIO_OFF 0x35
4999 +#define MCU_CURRENT 0x36
5000 +#define MCU_LED 0x50
5001 +#define MCU_LED_STRENGTH 0x51
5002 +#define MCU_LED_1 0x52
5003 +#define MCU_LED_2 0x53
5004 +#define MCU_LED_3 0x54
5005 +#define MCU_RADAR 0x60
5006 +#define MCU_BOOT_SIGNAL 0x72
5007 +#define MCU_BBP_SIGNAL 0x80
5008 +#define MCU_POWER_SAVE 0x83
5009 +
5010 +/*
5011 + * MCU mailbox tokens
5012 + */
5013 +#define TOKEN_WAKUP 3
5014 +
5015 +/*
5016 + * DMA descriptor defines.
5017 + */
5018 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
5019 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
5020 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
5021 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
5022 +
5023 +/*
5024 + * TX descriptor format for TX, PRIO and Beacon Ring.
5025 + */
5026 +
5027 +/*
5028 + * Word0
5029 + */
5030 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
5031 +
5032 +/*
5033 + * Word1
5034 + */
5035 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
5036 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
5037 +#define TXD_W1_BURST FIELD32(0x00008000)
5038 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
5039 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
5040 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
5041 +
5042 +/*
5043 + * Word2
5044 + */
5045 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
5046 +
5047 +/*
5048 + * Word3
5049 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
5050 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
5051 + * 0:MGMT, 1:HCCA 2:EDCA
5052 + */
5053 +#define TXD_W3_WIV FIELD32(0x01000000)
5054 +#define TXD_W3_QSEL FIELD32(0x06000000)
5055 +#define TXD_W3_TCO FIELD32(0x20000000)
5056 +#define TXD_W3_UCO FIELD32(0x40000000)
5057 +#define TXD_W3_ICO FIELD32(0x80000000)
5058 +
5059 +/*
5060 + * TX WI structure
5061 + */
5062 +
5063 +/*
5064 + * Word0
5065 + * FRAG: 1 To inform TKIP engine this is a fragment.
5066 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
5067 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
5068 + * BW: Channel bandwidth 20MHz or 40 MHz
5069 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
5070 + */
5071 +#define TXWI_W0_FRAG FIELD32(0x00000001)
5072 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
5073 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
5074 +#define TXWI_W0_TS FIELD32(0x00000008)
5075 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
5076 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
5077 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
5078 +#define TXWI_W0_MCS FIELD32(0x007f0000)
5079 +#define TXWI_W0_BW FIELD32(0x00800000)
5080 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
5081 +#define TXWI_W0_STBC FIELD32(0x06000000)
5082 +#define TXWI_W0_IFS FIELD32(0x08000000)
5083 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
5084 +
5085 +/*
5086 + * Word1
5087 + */
5088 +#define TXWI_W1_ACK FIELD32(0x00000001)
5089 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
5090 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
5091 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
5092 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
5093 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
5094 +
5095 +/*
5096 + * Word2
5097 + */
5098 +#define TXWI_W2_IV FIELD32(0xffffffff)
5099 +
5100 +/*
5101 + * Word3
5102 + */
5103 +#define TXWI_W3_EIV FIELD32(0xffffffff)
5104 +
5105 +/*
5106 + * RX descriptor format for RX Ring.
5107 + */
5108 +
5109 +/*
5110 + * Word0
5111 + */
5112 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
5113 +
5114 +/*
5115 + * Word1
5116 + */
5117 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
5118 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
5119 +#define RXD_W1_LS0 FIELD32(0x40000000)
5120 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
5121 +
5122 +/*
5123 + * Word2
5124 + */
5125 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
5126 +
5127 +/*
5128 + * Word3
5129 + * AMSDU: RX with 802.3 header, not 802.11 header.
5130 + * DECRYPTED: This frame is being decrypted.
5131 + */
5132 +#define RXD_W3_BA FIELD32(0x00000001)
5133 +#define RXD_W3_DATA FIELD32(0x00000002)
5134 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
5135 +#define RXD_W3_FRAG FIELD32(0x00000008)
5136 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
5137 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
5138 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
5139 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
5140 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
5141 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
5142 +#define RXD_W3_AMSDU FIELD32(0x00000800)
5143 +#define RXD_W3_HTC FIELD32(0x00001000)
5144 +#define RXD_W3_RSSI FIELD32(0x00002000)
5145 +#define RXD_W3_L2PAD FIELD32(0x00004000)
5146 +#define RXD_W3_AMPDU FIELD32(0x00008000)
5147 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
5148 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
5149 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
5150 +
5151 +/*
5152 + * RX WI structure
5153 + */
5154 +
5155 +/*
5156 + * Word0
5157 + */
5158 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
5159 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
5160 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
5161 +#define RXWI_W0_UDF FIELD32(0x0000e000)
5162 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
5163 +#define RXWI_W0_TID FIELD32(0xf0000000)
5164 +
5165 +/*
5166 + * Word1
5167 + */
5168 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
5169 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
5170 +#define RXWI_W1_MCS FIELD32(0x007f0000)
5171 +#define RXWI_W1_BW FIELD32(0x00800000)
5172 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
5173 +#define RXWI_W1_STBC FIELD32(0x06000000)
5174 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
5175 +
5176 +/*
5177 + * Word2
5178 + */
5179 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
5180 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
5181 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
5182 +
5183 +/*
5184 + * Word3
5185 + */
5186 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
5187 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
5188 +
5189 +/*
5190 + * Macros for converting txpower from EEPROM to mac80211 value
5191 + * and from mac80211 value to register value.
5192 + */
5193 +#define MIN_G_TXPOWER 0
5194 +#define MIN_A_TXPOWER -7
5195 +#define MAX_G_TXPOWER 31
5196 +#define MAX_A_TXPOWER 15
5197 +#define DEFAULT_TXPOWER 5
5198 +
5199 +#define TXPOWER_G_FROM_DEV(__txpower) \
5200 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5201 +
5202 +#define TXPOWER_G_TO_DEV(__txpower) \
5203 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
5204 +
5205 +#define TXPOWER_A_FROM_DEV(__txpower) \
5206 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5207 +
5208 +#define TXPOWER_A_TO_DEV(__txpower) \
5209 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5210 +
5211 +#endif /* RT2800PCI_H */
5212 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5213 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5214 @@ -158,6 +158,12 @@ struct rt2x00_chip {
5215 #define RT2561 0x0302
5216 #define RT2661 0x0401
5217 #define RT2571 0x1300
5218 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
5219 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
5220 +#define RT2890 0x0701 /* 2.4GHz PCIe */
5221 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
5222 +#define RT2880 0x2880 /* WSOC */
5223 +#define RT3052 0x3052 /* WSOC */
5224 #define RT2870 0x1600
5225
5226 u16 rf;
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