projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
[lantiq]
[openwrt.git] / target / linux / lantiq / patches / 104-board_xway.patch
1
2 --- /dev/null
3 +++ b/arch/mips/lantiq/xway/Kconfig
4 @@ -0,0 +1,19 @@
5 +if SOC_LANTIQ_XWAY
6 +
7 +menu "Mips Machine"
8 +
9 +config LANTIQ_MACH_EASY50812
10 + bool "Easy50812"
11 + default y
12 +
13 +config LANTIQ_MACH_EASY50712
14 + bool "Easy50712"
15 + default y
16 +
17 +config LANTIQ_MACH_EASY4010
18 + bool "Easy4010"
19 + default y
20 +
21 +endmenu
22 +
23 +endif
24 --- /dev/null
25 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
26 @@ -0,0 +1,116 @@
27 +/*
28 + * This program is free software; you can redistribute it and/or modify it
29 + * under the terms of the GNU General Public License version 2 as published
30 + * by the Free Software Foundation.
31 + *
32 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#include <linux/init.h>
36 +#include <linux/module.h>
37 +#include <linux/types.h>
38 +#include <linux/platform_device.h>
39 +#include <linux/mutex.h>
40 +#include <linux/gpio.h>
41 +
42 +#include <xway.h>
43 +
44 +#define LQ_EBU_BUSCON 0x1e7ff
45 +#define LQ_EBU_WP 0x80000000
46 +
47 +static int shadow = 0x0000;
48 +static void __iomem *virt;
49 +
50 +static int
51 +lq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
52 +{
53 + return 0;
54 +}
55 +
56 +static void
57 +lq_ebu_apply(void)
58 +{
59 + unsigned long flags;
60 + spin_lock_irqsave(&ebu_lock, flags);
61 + lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
62 + *((__u16*)virt) = shadow;
63 + lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
64 + spin_unlock_irqrestore(&ebu_lock, flags);
65 +}
66 +
67 +static void
68 +lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
69 +{
70 + if(value)
71 + shadow |= (1 << offset);
72 + else
73 + shadow &= ~(1 << offset);
74 + lq_ebu_apply();
75 +}
76 +
77 +static struct gpio_chip
78 +lq_ebu_chip =
79 +{
80 + .label = "lq_ebu",
81 + .direction_output = lq_ebu_direction_output,
82 + .set = lq_ebu_set,
83 + .base = 32,
84 + .ngpio = 16,
85 + .can_sleep = 1,
86 + .owner = THIS_MODULE,
87 +};
88 +
89 +static int __devinit
90 +lq_ebu_probe(struct platform_device *pdev)
91 +{
92 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93 + int ret = 0;
94 + if (!res)
95 + return -ENOENT;
96 + res = request_mem_region(res->start, resource_size(res),
97 + dev_name(&pdev->dev));
98 + if (!res)
99 + return -EBUSY;
100 +
101 + /* tell the ebu controller which mem addr we will be using */
102 + lq_w32(pdev->resource->start | 0x1, LQ_EBU_ADDRSEL1);
103 + lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
104 +
105 + virt = ioremap_nocache(res->start, resource_size(res));
106 + if (!virt)
107 + {
108 + dev_err(&pdev->dev, "Failed to ioremap mem region\n");
109 + ret = -ENOMEM;
110 + goto err_release_mem_region;
111 + }
112 + /* grab the default settings passed form the platform code */
113 + shadow = (unsigned int) pdev->dev.platform_data;
114 +
115 + ret = gpiochip_add(&lq_ebu_chip);
116 + if (!ret)
117 + {
118 + lq_ebu_apply();
119 + return 0;
120 + }
121 +
122 +err_release_mem_region:
123 + release_mem_region(res->start, resource_size(res));
124 + return ret;
125 +}
126 +
127 +static struct platform_driver
128 +lq_ebu_driver = {
129 + .probe = lq_ebu_probe,
130 + .driver = {
131 + .name = "lq_ebu",
132 + .owner = THIS_MODULE,
133 + },
134 +};
135 +
136 +static int __init
137 +init_lq_ebu(void)
138 +{
139 + return platform_driver_register(&lq_ebu_driver);
140 +}
141 +
142 +postcore_initcall(init_lq_ebu);
143 --- /dev/null
144 +++ b/arch/mips/lantiq/xway/gpio_leds.c
145 @@ -0,0 +1,161 @@
146 +/*
147 + * This program is free software; you can redistribute it and/or modify it
148 + * under the terms of the GNU General Public License version 2 as published
149 + * by the Free Software Foundation.
150 + *
151 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
152 + *
153 + */
154 +
155 +#include <linux/slab.h>
156 +#include <linux/init.h>
157 +#include <linux/module.h>
158 +#include <linux/types.h>
159 +#include <linux/platform_device.h>
160 +#include <linux/mutex.h>
161 +#include <linux/gpio.h>
162 +
163 +#include <xway.h>
164 +
165 +#define LQ_STP_BASE 0x1E100BB0
166 +#define LQ_STP_SIZE 0x40
167 +
168 +#define LQ_STP_CON0 0x00
169 +#define LQ_STP_CON1 0x04
170 +#define LQ_STP_CPU0 0x08
171 +#define LQ_STP_CPU1 0x0C
172 +#define LQ_STP_AR 0x10
173 +
174 +#define STP_CON0_SWU (1 << 31)
175 +
176 +#define LQ_STP_2HZ (0)
177 +#define LQ_STP_4HZ (1 << 23)
178 +#define LQ_STP_8HZ (2 << 23)
179 +#define LQ_STP_10HZ (3 << 23)
180 +#define LQ_STP_MASK (0xf << 23)
181 +
182 +#define LQ_STP_UPD_SRC_FPI (1 << 31)
183 +#define LQ_STP_UPD_MASK (3 << 30)
184 +#define LQ_STP_ADSL_SRC (3 << 24)
185 +
186 +#define LQ_STP_GROUP0 (1 << 0)
187 +
188 +#define LQ_STP_RISING 0
189 +#define LQ_STP_FALLING (1 << 26)
190 +#define LQ_STP_EDGE_MASK (1 << 26)
191 +
192 +#define lq_stp_r32(reg) __raw_readl(virt + reg)
193 +#define lq_stp_w32(val, reg) __raw_writel(val, virt + reg)
194 +#define lq_stp_w32_mask(clear, set, reg) \
195 + lq_w32((lq_r32(virt + reg) & ~clear) | set, virt + reg)
196 +
197 +static int shadow = 0xffff;
198 +static void __iomem *virt;
199 +
200 +static int
201 +lq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value)
202 +{
203 + return 0;
204 +}
205 +
206 +static void
207 +lq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
208 +{
209 + if(value)
210 + shadow |= (1 << offset);
211 + else
212 + shadow &= ~(1 << offset);
213 + lq_stp_w32(shadow, LQ_STP_CPU0);
214 +}
215 +
216 +static struct gpio_chip lq_stp_chip =
217 +{
218 + .label = "lq_stp",
219 + .direction_output = lq_stp_direction_output,
220 + .set = lq_stp_set,
221 + .base = 48,
222 + .ngpio = 24,
223 + .can_sleep = 1,
224 + .owner = THIS_MODULE,
225 +};
226 +
227 +static int
228 +lq_stp_hw_init(void)
229 +{
230 + /* the 3 pins used to control the external stp */
231 + lq_gpio_request(4, 1, 0, 1, "stp-st");
232 + lq_gpio_request(5, 1, 0, 1, "stp-d");
233 + lq_gpio_request(6, 1, 0, 1, "stp-sh");
234 +
235 + /* sane defaults */
236 + lq_stp_w32(0, LQ_STP_AR);
237 + lq_stp_w32(0, LQ_STP_CPU0);
238 + lq_stp_w32(0, LQ_STP_CPU1);
239 + lq_stp_w32(STP_CON0_SWU, LQ_STP_CON0);
240 + lq_stp_w32(0, LQ_STP_CON1);
241 +
242 + /* rising or falling edge */
243 + lq_stp_w32_mask(LQ_STP_EDGE_MASK, LQ_STP_FALLING, LQ_STP_CON0);
244 +
245 + /* per default stp 15-0 are set */
246 + lq_stp_w32_mask(0, LQ_STP_GROUP0, LQ_STP_CON1);
247 +
248 + /* stp are update periodically by the FPID */
249 + lq_stp_w32_mask(LQ_STP_UPD_MASK, LQ_STP_UPD_SRC_FPI, LQ_STP_CON1);
250 +
251 + /* set stp update speed */
252 + lq_stp_w32_mask(LQ_STP_MASK, LQ_STP_8HZ, LQ_STP_CON1);
253 +
254 + /* adsl 0 and 1 stp are updated by the arc */
255 + lq_stp_w32_mask(0, LQ_STP_ADSL_SRC, LQ_STP_CON0);
256 +
257 + lq_pmu_enable(PMU_LED);
258 + return 0;
259 +}
260 +
261 +static int
262 +lq_stp_probe(struct platform_device *pdev)
263 +{
264 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 + int ret = 0;
266 + if (!res)
267 + return -ENOENT;
268 + res = request_mem_region(res->start, resource_size(res),
269 + dev_name(&pdev->dev));
270 + if (!res)
271 + return -EBUSY;
272 + virt = ioremap_nocache(res->start, resource_size(res));
273 + if(!virt)
274 + {
275 + ret = -ENOMEM;
276 + goto err_release_mem_region;
277 + }
278 + ret = gpiochip_add(&lq_stp_chip);
279 + if(!ret)
280 + return lq_stp_hw_init();
281 +
282 + iounmap(virt);
283 +err_release_mem_region:
284 + release_mem_region(res->start, resource_size(res));
285 + return ret;
286 +}
287 +
288 +static struct platform_driver lq_stp_driver = {
289 + .probe = lq_stp_probe,
290 + .driver = {
291 + .name = "lq_stp",
292 + .owner = THIS_MODULE,
293 + },
294 +};
295 +
296 +int __init
297 +init_lq_stp(void)
298 +{
299 + int ret = platform_driver_register(&lq_stp_driver);
300 + if (ret)
301 + printk(KERN_INFO
302 + "lq_stp: error registering platfom driver");
303 + return ret;
304 +}
305 +
306 +postcore_initcall(init_lq_stp);
307 --- /dev/null
308 +++ b/arch/mips/lantiq/xway/mach-easy4010.c
309 @@ -0,0 +1,82 @@
310 +/*
311 + * This program is free software; you can redistribute it and/or modify it
312 + * under the terms of the GNU General Public License version 2 as published
313 + * by the Free Software Foundation.
314 + *
315 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
316 + */
317 +
318 +#include <linux/init.h>
319 +#include <linux/platform_device.h>
320 +#include <linux/leds.h>
321 +#include <linux/gpio.h>
322 +#include <linux/gpio_buttons.h>
323 +#include <linux/mtd/mtd.h>
324 +#include <linux/mtd/partitions.h>
325 +#include <linux/mtd/physmap.h>
326 +#include <linux/input.h>
327 +
328 +#include <machine.h>
329 +
330 +#include <xway.h>
331 +#include <lantiq_platform.h>
332 +
333 +#include "devices.h"
334 +
335 +#ifdef CONFIG_MTD_PARTITIONS
336 +static struct mtd_partition easy4010_partitions[] =
337 +{
338 + {
339 + .name = "uboot",
340 + .offset = 0x0,
341 + .size = 0x20000,
342 + },
343 + {
344 + .name = "uboot_env",
345 + .offset = 0x20000,
346 + .size = 0x10000,
347 + },
348 + {
349 + .name = "linux",
350 + .offset = 0x30000,
351 + .size = 0x3D0000,
352 + },
353 +};
354 +#endif
355 +
356 +static struct physmap_flash_data easy4010_flash_data = {
357 +#ifdef CONFIG_MTD_PARTITIONS
358 + .nr_parts = ARRAY_SIZE(easy4010_partitions),
359 + .parts = easy4010_partitions,
360 +#endif
361 +};
362 +
363 +static struct lq_pci_data lq_pci_data = {
364 + .clock = PCI_CLOCK_INT,
365 + .gpio = PCI_GNT1 | PCI_REQ1,
366 + .irq = {
367 + [14] = INT_NUM_IM0_IRL0 + 22,
368 + },
369 +};
370 +
371 +static struct lq_eth_data lq_eth_data = {
372 + .mii_mode = REV_MII_MODE,
373 +};
374 +
375 +static void __init
376 +easy4010_init(void)
377 +{
378 + lq_register_gpio();
379 + lq_register_gpio_stp();
380 + lq_register_asc(0);
381 + lq_register_asc(1);
382 + lq_register_nor(&easy4010_flash_data);
383 + lq_register_wdt();
384 + lq_register_pci(&lq_pci_data);
385 + lq_register_ethernet(&lq_eth_data);
386 +}
387 +
388 +MIPS_MACHINE(LANTIQ_MACH_EASY4010,
389 + "EASY4010",
390 + "EASY4010 Eval Board",
391 + easy4010_init);
392 --- /dev/null
393 +++ b/arch/mips/lantiq/xway/mach-easy50712.c
394 @@ -0,0 +1,82 @@
395 +/*
396 + * This program is free software; you can redistribute it and/or modify it
397 + * under the terms of the GNU General Public License version 2 as published
398 + * by the Free Software Foundation.
399 + *
400 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
401 + */
402 +
403 +#include <linux/init.h>
404 +#include <linux/platform_device.h>
405 +#include <linux/leds.h>
406 +#include <linux/gpio.h>
407 +#include <linux/gpio_buttons.h>
408 +#include <linux/mtd/mtd.h>
409 +#include <linux/mtd/partitions.h>
410 +#include <linux/mtd/physmap.h>
411 +#include <linux/input.h>
412 +
413 +#include <machine.h>
414 +
415 +#include <xway.h>
416 +#include <lantiq_platform.h>
417 +
418 +#include "devices.h"
419 +
420 +#ifdef CONFIG_MTD_PARTITIONS
421 +static struct mtd_partition easy50712_partitions[] =
422 +{
423 + {
424 + .name = "uboot",
425 + .offset = 0x0,
426 + .size = 0x20000,
427 + },
428 + {
429 + .name = "uboot_env",
430 + .offset = 0x20000,
431 + .size = 0x10000,
432 + },
433 + {
434 + .name = "linux",
435 + .offset = 0x30000,
436 + .size = 0x3D0000,
437 + },
438 +};
439 +#endif
440 +
441 +static struct physmap_flash_data easy50712_flash_data = {
442 +#ifdef CONFIG_MTD_PARTITIONS
443 + .nr_parts = ARRAY_SIZE(easy50712_partitions),
444 + .parts = easy50712_partitions,
445 +#endif
446 +};
447 +
448 +static struct lq_pci_data lq_pci_data = {
449 + .clock = PCI_CLOCK_INT,
450 + .gpio = PCI_GNT1 | PCI_REQ1,
451 + .irq = {
452 + [14] = INT_NUM_IM0_IRL0 + 22,
453 + },
454 +};
455 +
456 +static struct lq_eth_data lq_eth_data = {
457 + .mii_mode = REV_MII_MODE,
458 +};
459 +
460 +static void __init
461 +easy50712_init(void)
462 +{
463 + lq_register_asc(0);
464 + lq_register_asc(1);
465 + lq_register_gpio();
466 + lq_register_gpio_stp();
467 + lq_register_nor(&easy50712_flash_data);
468 + lq_register_wdt();
469 + lq_register_pci(&lq_pci_data);
470 + lq_register_ethernet(&lq_eth_data);
471 +}
472 +
473 +MIPS_MACHINE(LANTIQ_MACH_EASY50712,
474 + "EASY50712",
475 + "EASY50712 Eval Board",
476 + easy50712_init);
477 --- /dev/null
478 +++ b/arch/mips/lantiq/xway/mach-easy50812.c
479 @@ -0,0 +1,81 @@
480 +/*
481 + * This program is free software; you can redistribute it and/or modify it
482 + * under the terms of the GNU General Public License version 2 as published
483 + * by the Free Software Foundation.
484 + *
485 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
486 + */
487 +
488 +#include <linux/init.h>
489 +#include <linux/platform_device.h>
490 +#include <linux/leds.h>
491 +#include <linux/gpio.h>
492 +#include <linux/gpio_buttons.h>
493 +#include <linux/mtd/mtd.h>
494 +#include <linux/mtd/partitions.h>
495 +#include <linux/mtd/physmap.h>
496 +#include <linux/input.h>
497 +
498 +#include <machine.h>
499 +
500 +#include <xway.h>
501 +#include <lantiq_platform.h>
502 +
503 +#include "devices.h"
504 +
505 +#ifdef CONFIG_MTD_PARTITIONS
506 +static struct mtd_partition easy50812_partitions[] =
507 +{
508 + {
509 + .name = "uboot",
510 + .offset = 0x0,
511 + .size = 0x40000,
512 + },
513 + {
514 + .name = "uboot_env",
515 + .offset = 0x40000,
516 + .size = 0x10000,
517 + },
518 + {
519 + .name = "linux",
520 + .offset = 0x50000,
521 + .size = 0x3B0000,
522 + },
523 +};
524 +#endif
525 +
526 +static struct physmap_flash_data easy50812_flash_data = {
527 +#ifdef CONFIG_MTD_PARTITIONS
528 + .nr_parts = ARRAY_SIZE(easy50812_partitions),
529 + .parts = easy50812_partitions,
530 +#endif
531 +};
532 +
533 +static struct lq_pci_data lq_pci_data = {
534 + .clock = PCI_CLOCK_INT,
535 + .gpio = PCI_GNT1 | PCI_REQ1,
536 + .irq = {
537 + [14] = INT_NUM_IM0_IRL0 + 22,
538 + },
539 +};
540 +
541 +static struct lq_eth_data lq_eth_data = {
542 + .mii_mode = REV_MII_MODE,
543 +};
544 +
545 +static void __init
546 +easy50812_init(void)
547 +{
548 + lq_register_gpio();
549 + lq_register_asc(0);
550 + lq_register_asc(1);
551 + lq_register_nor(&easy50812_flash_data);
552 + lq_register_wdt();
553 + lq_register_pci(&lq_pci_data);
554 + lq_register_ethernet(&lq_eth_data);
555 +}
556 +
557 +MIPS_MACHINE(LANTIQ_MACH_EASY50812,
558 + "EASY50812",
559 + "EASY50812 Eval Board",
560 + easy50812_init);
561 --- /dev/null
562 +++ b/arch/mips/lantiq/xway/prom.c
563 @@ -0,0 +1,52 @@
564 +/*
565 + * This program is free software; you can redistribute it and/or modify it
566 + * under the terms of the GNU General Public License version 2 as published
567 + * by the Free Software Foundation.
568 + *
569 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
570 + */
571 +
572 +#include <linux/module.h>
573 +#include <linux/clk.h>
574 +#include <asm/bootinfo.h>
575 +#include <asm/time.h>
576 +
577 +#include <xway.h>
578 +
579 +#include "../prom.h"
580 +
581 +#define SOC_DANUBE "Danube"
582 +#define SOC_TWINPASS "Twinpass"
583 +#define SOC_AR9 "AR9"
584 +
585 +void __init
586 +lq_soc_detect(struct lq_soc_info *i)
587 +{
588 + i->partnum = (lq_r32(LQ_MPS_CHIPID) & 0x0FFFFFFF) >> 12;
589 + i->rev = (lq_r32(LQ_MPS_CHIPID) & 0xF0000000) >> 28;
590 + switch (i->partnum)
591 + {
592 + case SOC_ID_DANUBE1:
593 + case SOC_ID_DANUBE2:
594 + i->name = SOC_DANUBE;
595 + i->type = SOC_TYPE_DANUBE;
596 + break;
597 +
598 + case SOC_ID_TWINPASS:
599 + i->name = SOC_TWINPASS;
600 + i->type = SOC_TYPE_DANUBE;
601 + break;
602 +
603 + case SOC_ID_ARX188:
604 + case SOC_ID_ARX168:
605 + case SOC_ID_ARX182:
606 + i->name = SOC_AR9;
607 + i->type = SOC_TYPE_AR9;
608 + break;
609 +
610 + default:
611 + printk(KERN_ERR "unknown chiprev : 0x%08X\n", i->partnum);
612 + while(1) { };
613 + break;
614 + }
615 +}
616 --- /dev/null
617 +++ b/arch/mips/lantiq/xway/devices.c
618 @@ -0,0 +1,305 @@
619 +/*
620 + * This program is free software; you can redistribute it and/or modify it
621 + * under the terms of the GNU General Public License version 2 as published
622 + * by the Free Software Foundation.
623 + *
624 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
625 + */
626 +
627 +#include <linux/init.h>
628 +#include <linux/module.h>
629 +#include <linux/types.h>
630 +#include <linux/string.h>
631 +#include <linux/mtd/physmap.h>
632 +#include <linux/kernel.h>
633 +#include <linux/reboot.h>
634 +#include <linux/platform_device.h>
635 +#include <linux/leds.h>
636 +#include <linux/etherdevice.h>
637 +#include <linux/reboot.h>
638 +#include <linux/time.h>
639 +#include <linux/io.h>
640 +#include <linux/gpio.h>
641 +#include <linux/gpio_buttons.h>
642 +#include <linux/leds.h>
643 +
644 +#include <asm/bootinfo.h>
645 +#include <asm/irq.h>
646 +
647 +#include <xway.h>
648 +#include <xway_irq.h>
649 +#include <lantiq_platform.h>
650 +
651 +#define IRQ_RES(resname,irq) {.name=#resname,.start=(irq),.flags=IORESOURCE_IRQ}
652 +
653 +/* gpio leds */
654 +static struct gpio_led_platform_data lq_gpio_led_data;
655 +
656 +static struct platform_device lq_gpio_leds =
657 +{
658 + .name = "leds-gpio",
659 + .dev = {
660 + .platform_data = (void *) &lq_gpio_led_data,
661 + }
662 +};
663 +
664 +void __init
665 +lq_register_gpio_leds(struct gpio_led *leds, int cnt)
666 +{
667 + lq_gpio_led_data.leds = leds;
668 + lq_gpio_led_data.num_leds = cnt;
669 + platform_device_register(&lq_gpio_leds);
670 +}
671 +
672 +/* gpio buttons */
673 +static struct gpio_buttons_platform_data lq_gpio_buttons_platform_data;
674 +
675 +static struct platform_device lq_gpio_buttons_platform_device =
676 +{
677 + .name = "gpio-buttons",
678 + .id = 0,
679 + .dev = {
680 + .platform_data = (void *) &lq_gpio_buttons_platform_data,
681 + },
682 +};
683 +
684 +void __init
685 +lq_register_gpio_buttons(struct gpio_button *buttons, int cnt)
686 +{
687 + lq_gpio_buttons_platform_data.buttons = buttons;
688 + lq_gpio_buttons_platform_data.nbuttons = cnt;
689 + platform_device_register(&lq_gpio_buttons_platform_device);
690 +}
691 +
692 +/* serial to parallel conversion */
693 +static struct resource lq_stp_resource =
694 +{
695 + .name = "stp",
696 + .start = LQ_STP_BASE,
697 + .end = LQ_STP_BASE + LQ_STP_SIZE - 1,
698 + .flags = IORESOURCE_MEM,
699 +};
700 +
701 +void __init
702 +lq_register_gpio_stp(void)
703 +{
704 + platform_device_register_simple("lq_stp", 0, &lq_stp_resource, 1);
705 +}
706 +
707 +/* nor flash */
708 +static struct resource lq_nor_resource =
709 +{
710 + .name = "nor",
711 + .start = LQ_FLASH_START,
712 + .end = LQ_FLASH_START + LQ_FLASH_MAX - 1,
713 + .flags = IORESOURCE_MEM,
714 +};
715 +
716 +static struct platform_device lq_nor =
717 +{
718 + .name = "lq_nor",
719 + .resource = &lq_nor_resource,
720 + .num_resources = 1,
721 +};
722 +
723 +void __init
724 +lq_register_nor(struct physmap_flash_data *data)
725 +{
726 + lq_nor.dev.platform_data = data;
727 + platform_device_register(&lq_nor);
728 +}
729 +
730 +/* watchdog */
731 +static struct resource lq_wdt_resource =
732 +{
733 + .name = "watchdog",
734 + .start = LQ_WDT_BASE,
735 + .end = LQ_WDT_BASE + LQ_WDT_SIZE - 1,
736 + .flags = IORESOURCE_MEM,
737 +};
738 +
739 +void __init
740 +lq_register_wdt(void)
741 +{
742 + platform_device_register_simple("lq_wdt", 0, &lq_wdt_resource, 1);
743 +}
744 +
745 +/* gpio */
746 +static struct resource lq_gpio_resource[] = {
747 + {
748 + .name = "gpio0",
749 + .start = LQ_GPIO0_BASE_ADDR,
750 + .end = LQ_GPIO0_BASE_ADDR + LQ_GPIO_SIZE - 1,
751 + .flags = IORESOURCE_MEM,
752 + }, {
753 + .name = "gpio1",
754 + .start = LQ_GPIO1_BASE_ADDR,
755 + .end = LQ_GPIO1_BASE_ADDR + LQ_GPIO_SIZE - 1,
756 + .flags = IORESOURCE_MEM,
757 + }
758 +};
759 +
760 +void __init
761 +lq_register_gpio(void)
762 +{
763 + platform_device_register_simple("lq_gpio", 0, &lq_gpio_resource[0], 1);
764 + platform_device_register_simple("lq_gpio", 1, &lq_gpio_resource[1], 1);
765 +}
766 +
767 +/* pci */
768 +static struct platform_device lq_pci =
769 +{
770 + .name = "lq_pci",
771 + .num_resources = 0,
772 +};
773 +
774 +void __init
775 +lq_register_pci(struct lq_pci_data *data)
776 +{
777 + lq_pci.dev.platform_data = data;
778 + platform_device_register(&lq_pci);
779 +}
780 +
781 +/* ebu */
782 +static struct resource lq_ebu_resource =
783 +{
784 + .name = "gpio_ebu",
785 + .start = LQ_EBU_GPIO_START,
786 + .end = LQ_EBU_GPIO_START + LQ_EBU_GPIO_SIZE - 1,
787 + .flags = IORESOURCE_MEM,
788 +};
789 +
790 +void __init
791 +lq_register_gpio_ebu(unsigned int value)
792 +{
793 + platform_device_register_simple("lq_ebu", 0, &lq_ebu_resource, 1);
794 +}
795 +
796 +/* ethernet */
797 +unsigned char lq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
798 +
799 +static int __init
800 +lq_set_ethaddr(char *str)
801 +{
802 + sscanf(&str[8], "0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx",
803 + &lq_ethaddr[0], &lq_ethaddr[1], &lq_ethaddr[2],
804 + &lq_ethaddr[3], &lq_ethaddr[4], &lq_ethaddr[5]);
805 + return 0;
806 +}
807 +__setup("ethaddr=", lq_set_ethaddr);
808 +
809 +static struct resource lq_ethernet_resources =
810 +{
811 + .name = "etop",
812 + .start = LQ_PPE32_BASE_ADDR,
813 + .end = LQ_PPE32_BASE_ADDR + LQ_PPE32_SIZE - 1,
814 + .flags = IORESOURCE_MEM,
815 +};
816 +
817 +static struct platform_device lq_ethernet =
818 +{
819 + .name = "lq_etop",
820 + .resource = &lq_ethernet_resources,
821 + .num_resources = 1,
822 +};
823 +
824 +void __init
825 +lq_register_ethernet(struct lq_eth_data *eth)
826 +{
827 + if(!eth)
828 + return;
829 + if(!eth->mac)
830 + eth->mac = lq_ethaddr;
831 + if(!is_valid_ether_addr(eth->mac))
832 + random_ether_addr(eth->mac);
833 + lq_ethernet.dev.platform_data = eth;
834 + platform_device_register(&lq_ethernet);
835 +}
836 +
837 +/* tapi */
838 +static struct resource mps_resources[] = {
839 + {
840 + .name = "voice-mem",
841 + .flags = IORESOURCE_MEM,
842 + .start = 0x1f107000,
843 + .end = 0x1f1073ff,
844 + },
845 + {
846 + .name = "voice-mailbox",
847 + .flags = IORESOURCE_MEM,
848 + .start = 0x1f200000,
849 + .end = 0x1f2007ff,
850 + },
851 +};
852 +
853 +static struct platform_device mps_device = {
854 + .name = "mps",
855 + .resource = mps_resources,
856 + .num_resources = ARRAY_SIZE(mps_resources),
857 +};
858 +
859 +static struct platform_device vmmc_device = {
860 + .name = "vmmc",
861 + .dev = {
862 + .parent = &mps_device.dev,
863 + },
864 +};
865 +
866 +void __init
867 +lq_register_tapi(void)
868 +{
869 +#define CP1_SIZE (1 << 20)
870 + dma_addr_t dma;
871 + mps_device.dev.platform_data =
872 + (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
873 + platform_device_register(&mps_device);
874 + platform_device_register(&vmmc_device);
875 +}
876 +
877 +/* asc ports */
878 +static struct resource lq_asc0_resources[] =
879 +{
880 + {
881 + .start = LQ_ASC0_BASE,
882 + .end = LQ_ASC0_BASE + LQ_ASC_SIZE - 1,
883 + .flags = IORESOURCE_MEM,
884 + },
885 + IRQ_RES(tx, INT_NUM_IM3_IRL0),
886 + IRQ_RES(rx, INT_NUM_IM3_IRL0 + 1),
887 + IRQ_RES(err, INT_NUM_IM3_IRL0 + 2),
888 +};
889 +
890 +static struct resource lq_asc1_resources[] =
891 +{
892 + {
893 + .start = LQ_ASC1_BASE,
894 + .end = LQ_ASC1_BASE + LQ_ASC_SIZE - 1,
895 + .flags = IORESOURCE_MEM,
896 + },
897 + IRQ_RES(tx, INT_NUM_IM3_IRL0 + 8),
898 + IRQ_RES(rx, INT_NUM_IM3_IRL0 + 9),
899 + IRQ_RES(err, INT_NUM_IM3_IRL0 + 10),
900 +};
901 +
902 +void __init
903 +lq_register_asc(int port)
904 +{
905 + switch (port) {
906 + case 0:
907 + platform_device_register_simple("lq_asc", 0,
908 + lq_asc0_resources, ARRAY_SIZE(lq_asc0_resources));
909 + break;
910 + case 1:
911 + platform_device_register_simple("lq_asc", 1,
912 + lq_asc1_resources, ARRAY_SIZE(lq_asc1_resources));
913 + break;
914 + default:
915 + break;
916 + }
917 +}
918 +
919 +void __init
920 +lq_register_crypto(const char *name)
921 +{
922 + platform_device_register_simple(name, 0, 0, 0);
923 +}
924 --- /dev/null
925 +++ b/arch/mips/lantiq/xway/devices.h
926 @@ -0,0 +1,26 @@
927 +/*
928 + * This program is free software; you can redistribute it and/or modify it
929 + * under the terms of the GNU General Public License version 2 as published
930 + * by the Free Software Foundation.
931 + *
932 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
933 + */
934 +
935 +#ifndef _LQ_DEVICES_H__
936 +#define _LQ_DEVICES_H__
937 +
938 +#include <lantiq_platform.h>
939 +#include <xway_irq.h>
940 +
941 +extern void __init lq_register_gpio(void);
942 +extern void __init lq_register_gpio_stp(void);
943 +extern void __init lq_register_gpio_ebu(unsigned int value);
944 +extern void __init lq_register_gpio_leds(struct gpio_led *leds, int cnt);
945 +extern void __init lq_register_pci(struct lq_pci_data *data);
946 +extern void __init lq_register_nor(struct physmap_flash_data *data);
947 +extern void __init lq_register_wdt(void);
948 +extern void __init lq_register_ethernet(struct lq_eth_data *eth);
949 +extern void __init lq_register_asc(int port);
950 +extern void __init lq_register_gpio_buttons(struct gpio_button *buttons, int cnt);
951 +
952 +#endif
953 --- /dev/null
954 +++ b/arch/mips/lantiq/xway/dma.c
955 @@ -0,0 +1,701 @@
956 +#include <linux/module.h>
957 +#include <linux/init.h>
958 +#include <linux/sched.h>
959 +#include <linux/kernel.h>
960 +#include <linux/slab.h>
961 +#include <linux/string.h>
962 +#include <linux/timer.h>
963 +#include <linux/fs.h>
964 +#include <linux/errno.h>
965 +#include <linux/stat.h>
966 +#include <linux/mm.h>
967 +#include <linux/tty.h>
968 +#include <linux/selection.h>
969 +#include <linux/kmod.h>
970 +#include <linux/vmalloc.h>
971 +#include <linux/interrupt.h>
972 +#include <linux/delay.h>
973 +#include <linux/uaccess.h>
974 +#include <linux/errno.h>
975 +#include <linux/io.h>
976 +
977 +#include <xway.h>
978 +#include <xway_irq.h>
979 +#include <xway_dma.h>
980 +
981 +#define LQ_DMA_CS ((u32 *)(LQ_DMA_BASE_ADDR + 0x18))
982 +#define LQ_DMA_CIE ((u32 *)(LQ_DMA_BASE_ADDR + 0x2C))
983 +#define LQ_DMA_IRNEN ((u32 *)(LQ_DMA_BASE_ADDR + 0xf4))
984 +#define LQ_DMA_CCTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x1C))
985 +#define LQ_DMA_CIS ((u32 *)(LQ_DMA_BASE_ADDR + 0x28))
986 +#define LQ_DMA_CDLEN ((u32 *)(LQ_DMA_BASE_ADDR + 0x24))
987 +#define LQ_DMA_PS ((u32 *)(LQ_DMA_BASE_ADDR + 0x40))
988 +#define LQ_DMA_PCTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x44))
989 +#define LQ_DMA_CTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x10))
990 +#define LQ_DMA_CPOLL ((u32 *)(LQ_DMA_BASE_ADDR + 0x14))
991 +#define LQ_DMA_CDBA ((u32 *)(LQ_DMA_BASE_ADDR + 0x20))
992 +
993 +/*25 descriptors for each dma channel,4096/8/20=25.xx*/
994 +#define LQ_DMA_DESCRIPTOR_OFFSET 25
995 +
996 +#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
997 +#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
998 +#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
999 +#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
1000 +
1001 +extern void lq_mask_and_ack_irq(unsigned int irq_nr);
1002 +extern void lq_enable_irq(unsigned int irq_nr);
1003 +extern void lq_disable_irq(unsigned int irq_nr);
1004 +
1005 +u64 *g_desc_list;
1006 +struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
1007 +struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
1008 +
1009 +static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
1010 + { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
1011 +
1012 +struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
1013 + {"PPE", LQ_DMA_RX, 0, LQ_DMA_CH0_INT, 0},
1014 + {"PPE", LQ_DMA_TX, 0, LQ_DMA_CH1_INT, 0},
1015 + {"PPE", LQ_DMA_RX, 1, LQ_DMA_CH2_INT, 1},
1016 + {"PPE", LQ_DMA_TX, 1, LQ_DMA_CH3_INT, 1},
1017 + {"PPE", LQ_DMA_RX, 2, LQ_DMA_CH4_INT, 2},
1018 + {"PPE", LQ_DMA_TX, 2, LQ_DMA_CH5_INT, 2},
1019 + {"PPE", LQ_DMA_RX, 3, LQ_DMA_CH6_INT, 3},
1020 + {"PPE", LQ_DMA_TX, 3, LQ_DMA_CH7_INT, 3},
1021 + {"DEU", LQ_DMA_RX, 0, LQ_DMA_CH8_INT, 0},
1022 + {"DEU", LQ_DMA_TX, 0, LQ_DMA_CH9_INT, 0},
1023 + {"DEU", LQ_DMA_RX, 1, LQ_DMA_CH10_INT, 1},
1024 + {"DEU", LQ_DMA_TX, 1, LQ_DMA_CH11_INT, 1},
1025 + {"SPI", LQ_DMA_RX, 0, LQ_DMA_CH12_INT, 0},
1026 + {"SPI", LQ_DMA_TX, 0, LQ_DMA_CH13_INT, 0},
1027 + {"SDIO", LQ_DMA_RX, 0, LQ_DMA_CH14_INT, 0},
1028 + {"SDIO", LQ_DMA_TX, 0, LQ_DMA_CH15_INT, 0},
1029 + {"MCTRL0", LQ_DMA_RX, 0, LQ_DMA_CH16_INT, 0},
1030 + {"MCTRL0", LQ_DMA_TX, 0, LQ_DMA_CH17_INT, 0},
1031 + {"MCTRL1", LQ_DMA_RX, 1, LQ_DMA_CH18_INT, 1},
1032 + {"MCTRL1", LQ_DMA_TX, 1, LQ_DMA_CH19_INT, 1}
1033 +};
1034 +
1035 +struct dma_chan_map *chan_map = default_dma_map;
1036 +volatile u32 g_lq_dma_int_status;
1037 +volatile int g_lq_dma_in_process; /* 0=not in process, 1=in process */
1038 +
1039 +void do_dma_tasklet(unsigned long);
1040 +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
1041 +
1042 +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
1043 +{
1044 + u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
1045 +
1046 + *byte_offset = 0;
1047 +
1048 + return buffer;
1049 +}
1050 +
1051 +void common_buffer_free(u8 *dataptr, void *opt)
1052 +{
1053 + kfree(dataptr);
1054 +}
1055 +
1056 +void enable_ch_irq(struct dma_channel_info *pCh)
1057 +{
1058 + int chan_no = (int)(pCh - dma_chan);
1059 + unsigned long flag;
1060 +
1061 + local_irq_save(flag);
1062 + lq_w32(chan_no, LQ_DMA_CS);
1063 + lq_w32(0x4a, LQ_DMA_CIE);
1064 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1065 + local_irq_restore(flag);
1066 + lq_enable_irq(pCh->irq);
1067 +}
1068 +
1069 +void disable_ch_irq(struct dma_channel_info *pCh)
1070 +{
1071 + unsigned long flag;
1072 + int chan_no = (int) (pCh - dma_chan);
1073 +
1074 + local_irq_save(flag);
1075 + g_lq_dma_int_status &= ~(1 << chan_no);
1076 + lq_w32(chan_no, LQ_DMA_CS);
1077 + lq_w32(0, LQ_DMA_CIE);
1078 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN);
1079 + local_irq_restore(flag);
1080 + lq_mask_and_ack_irq(pCh->irq);
1081 +}
1082 +
1083 +void open_chan(struct dma_channel_info *pCh)
1084 +{
1085 + unsigned long flag;
1086 + int chan_no = (int)(pCh - dma_chan);
1087 +
1088 + local_irq_save(flag);
1089 + lq_w32(chan_no, LQ_DMA_CS);
1090 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 1, LQ_DMA_CCTRL);
1091 + if (pCh->dir == LQ_DMA_RX)
1092 + enable_ch_irq(pCh);
1093 + local_irq_restore(flag);
1094 +}
1095 +
1096 +void close_chan(struct dma_channel_info *pCh)
1097 +{
1098 + unsigned long flag;
1099 + int chan_no = (int) (pCh - dma_chan);
1100 +
1101 + local_irq_save(flag);
1102 + lq_w32(chan_no, LQ_DMA_CS);
1103 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1104 + disable_ch_irq(pCh);
1105 + local_irq_restore(flag);
1106 +}
1107 +
1108 +void reset_chan(struct dma_channel_info *pCh)
1109 +{
1110 + int chan_no = (int) (pCh - dma_chan);
1111 +
1112 + lq_w32(chan_no, LQ_DMA_CS);
1113 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1114 +}
1115 +
1116 +void rx_chan_intr_handler(int chan_no)
1117 +{
1118 + struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1119 + struct dma_channel_info *pCh = &dma_chan[chan_no];
1120 + struct rx_desc *rx_desc_p;
1121 + int tmp;
1122 + unsigned long flag;
1123 +
1124 + /*handle command complete interrupt */
1125 + rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
1126 + if (rx_desc_p->status.field.OWN == CPU_OWN
1127 + && rx_desc_p->status.field.C
1128 + && rx_desc_p->status.field.data_length < 1536){
1129 + /* Every thing is correct, then we inform the upper layer */
1130 + pDev->current_rx_chan = pCh->rel_chan_no;
1131 + if (pDev->intr_handler)
1132 + pDev->intr_handler(pDev, RCV_INT);
1133 + pCh->weight--;
1134 + } else {
1135 + local_irq_save(flag);
1136 + tmp = lq_r32(LQ_DMA_CS);
1137 + lq_w32(chan_no, LQ_DMA_CS);
1138 + lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1139 + lq_w32(tmp, LQ_DMA_CS);
1140 + g_lq_dma_int_status &= ~(1 << chan_no);
1141 + local_irq_restore(flag);
1142 + lq_enable_irq(dma_chan[chan_no].irq);
1143 + }
1144 +}
1145 +
1146 +inline void tx_chan_intr_handler(int chan_no)
1147 +{
1148 + struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1149 + struct dma_channel_info *pCh = &dma_chan[chan_no];
1150 + int tmp;
1151 + unsigned long flag;
1152 +
1153 + local_irq_save(flag);
1154 + tmp = lq_r32(LQ_DMA_CS);
1155 + lq_w32(chan_no, LQ_DMA_CS);
1156 + lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1157 + lq_w32(tmp, LQ_DMA_CS);
1158 + g_lq_dma_int_status &= ~(1 << chan_no);
1159 + local_irq_restore(flag);
1160 + pDev->current_tx_chan = pCh->rel_chan_no;
1161 + if (pDev->intr_handler)
1162 + pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
1163 +}
1164 +
1165 +void do_dma_tasklet(unsigned long unused)
1166 +{
1167 + int i;
1168 + int chan_no = 0;
1169 + int budget = DMA_INT_BUDGET;
1170 + int weight = 0;
1171 + unsigned long flag;
1172 +
1173 + while (g_lq_dma_int_status) {
1174 + if (budget-- < 0) {
1175 + tasklet_schedule(&dma_tasklet);
1176 + return;
1177 + }
1178 + chan_no = -1;
1179 + weight = 0;
1180 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1181 + if ((g_lq_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
1182 + if (dma_chan[i].weight > weight) {
1183 + chan_no = i;
1184 + weight = dma_chan[chan_no].weight;
1185 + }
1186 + }
1187 + }
1188 +
1189 + if (chan_no >= 0) {
1190 + if (chan_map[chan_no].dir == LQ_DMA_RX)
1191 + rx_chan_intr_handler(chan_no);
1192 + else
1193 + tx_chan_intr_handler(chan_no);
1194 + } else {
1195 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1196 + dma_chan[i].weight = dma_chan[i].default_weight;
1197 + }
1198 + }
1199 +
1200 + local_irq_save(flag);
1201 + g_lq_dma_in_process = 0;
1202 + if (g_lq_dma_int_status) {
1203 + g_lq_dma_in_process = 1;
1204 + tasklet_schedule(&dma_tasklet);
1205 + }
1206 + local_irq_restore(flag);
1207 +}
1208 +
1209 +irqreturn_t dma_interrupt(int irq, void *dev_id)
1210 +{
1211 + struct dma_channel_info *pCh;
1212 + int chan_no = 0;
1213 + int tmp;
1214 +
1215 + pCh = (struct dma_channel_info *)dev_id;
1216 + chan_no = (int)(pCh - dma_chan);
1217 + if (chan_no < 0 || chan_no > 19)
1218 + BUG();
1219 +
1220 + tmp = lq_r32(LQ_DMA_IRNEN);
1221 + lq_w32(0, LQ_DMA_IRNEN);
1222 + g_lq_dma_int_status |= 1 << chan_no;
1223 + lq_w32(tmp, LQ_DMA_IRNEN);
1224 + lq_mask_and_ack_irq(irq);
1225 +
1226 + if (!g_lq_dma_in_process) {
1227 + g_lq_dma_in_process = 1;
1228 + tasklet_schedule(&dma_tasklet);
1229 + }
1230 +
1231 + return IRQ_HANDLED;
1232 +}
1233 +
1234 +struct dma_device_info *dma_device_reserve(char *dev_name)
1235 +{
1236 + int i;
1237 +
1238 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1239 + if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
1240 + if (dma_devs[i].reserved)
1241 + return NULL;
1242 + dma_devs[i].reserved = 1;
1243 + break;
1244 + }
1245 + }
1246 +
1247 + return &dma_devs[i];
1248 +}
1249 +EXPORT_SYMBOL(dma_device_reserve);
1250 +
1251 +void dma_device_release(struct dma_device_info *dev)
1252 +{
1253 + dev->reserved = 0;
1254 +}
1255 +EXPORT_SYMBOL(dma_device_release);
1256 +
1257 +void dma_device_register(struct dma_device_info *dev)
1258 +{
1259 + int i, j;
1260 + int chan_no = 0;
1261 + u8 *buffer;
1262 + int byte_offset;
1263 + unsigned long flag;
1264 + struct dma_device_info *pDev;
1265 + struct dma_channel_info *pCh;
1266 + struct rx_desc *rx_desc_p;
1267 + struct tx_desc *tx_desc_p;
1268 +
1269 + for (i = 0; i < dev->max_tx_chan_num; i++) {
1270 + pCh = dev->tx_chan[i];
1271 + if (pCh->control == LQ_DMA_CH_ON) {
1272 + chan_no = (int)(pCh - dma_chan);
1273 + for (j = 0; j < pCh->desc_len; j++) {
1274 + tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1275 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1276 + }
1277 + local_irq_save(flag);
1278 + lq_w32(chan_no, LQ_DMA_CS);
1279 + /* check if the descriptor length is changed */
1280 + if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1281 + lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1282 +
1283 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1284 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1285 + while (lq_r32(LQ_DMA_CCTRL) & 2)
1286 + ;
1287 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1288 + lq_w32(0x30100, LQ_DMA_CCTRL); /* reset and enable channel,enable channel later */
1289 + local_irq_restore(flag);
1290 + }
1291 + }
1292 +
1293 + for (i = 0; i < dev->max_rx_chan_num; i++) {
1294 + pCh = dev->rx_chan[i];
1295 + if (pCh->control == LQ_DMA_CH_ON) {
1296 + chan_no = (int)(pCh - dma_chan);
1297 +
1298 + for (j = 0; j < pCh->desc_len; j++) {
1299 + rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
1300 + pDev = (struct dma_device_info *)(pCh->dma_dev);
1301 + buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
1302 + if (!buffer)
1303 + break;
1304 +
1305 + dma_cache_inv((unsigned long) buffer, pCh->packet_size);
1306 +
1307 + rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
1308 + rx_desc_p->status.word = 0;
1309 + rx_desc_p->status.field.byte_offset = byte_offset;
1310 + rx_desc_p->status.field.OWN = DMA_OWN;
1311 + rx_desc_p->status.field.data_length = pCh->packet_size;
1312 + }
1313 +
1314 + local_irq_save(flag);
1315 + lq_w32(chan_no, LQ_DMA_CS);
1316 + /* check if the descriptor length is changed */
1317 + if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1318 + lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1319 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1320 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1321 + while (lq_r32(LQ_DMA_CCTRL) & 2)
1322 + ;
1323 + lq_w32(0x0a, LQ_DMA_CIE); /* fix me, should enable all the interrupts here? */
1324 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1325 + lq_w32(0x30000, LQ_DMA_CCTRL);
1326 + local_irq_restore(flag);
1327 + lq_enable_irq(dma_chan[chan_no].irq);
1328 + }
1329 + }
1330 +}
1331 +EXPORT_SYMBOL(dma_device_register);
1332 +
1333 +void dma_device_unregister(struct dma_device_info *dev)
1334 +{
1335 + int i, j;
1336 + int chan_no;
1337 + struct dma_channel_info *pCh;
1338 + struct rx_desc *rx_desc_p;
1339 + struct tx_desc *tx_desc_p;
1340 + unsigned long flag;
1341 +
1342 + for (i = 0; i < dev->max_tx_chan_num; i++) {
1343 + pCh = dev->tx_chan[i];
1344 + if (pCh->control == LQ_DMA_CH_ON) {
1345 + chan_no = (int)(dev->tx_chan[i] - dma_chan);
1346 + local_irq_save(flag);
1347 + lq_w32(chan_no, LQ_DMA_CS);
1348 + pCh->curr_desc = 0;
1349 + pCh->prev_desc = 0;
1350 + pCh->control = LQ_DMA_CH_OFF;
1351 + lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1352 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1353 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1354 + while (lq_r32(LQ_DMA_CCTRL) & 1)
1355 + ;
1356 + local_irq_restore(flag);
1357 +
1358 + for (j = 0; j < pCh->desc_len; j++) {
1359 + tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1360 + if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
1361 + || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
1362 + dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
1363 + }
1364 + tx_desc_p->status.field.OWN = CPU_OWN;
1365 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1366 + }
1367 + /* TODO should free buffer that is not transferred by dma */
1368 + }
1369 + }
1370 +
1371 + for (i = 0; i < dev->max_rx_chan_num; i++) {
1372 + pCh = dev->rx_chan[i];
1373 + chan_no = (int)(dev->rx_chan[i] - dma_chan);
1374 + lq_disable_irq(pCh->irq);
1375 +
1376 + local_irq_save(flag);
1377 + g_lq_dma_int_status &= ~(1 << chan_no);
1378 + pCh->curr_desc = 0;
1379 + pCh->prev_desc = 0;
1380 + pCh->control = LQ_DMA_CH_OFF;
1381 +
1382 + lq_w32(chan_no, LQ_DMA_CS);
1383 + lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1384 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1385 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1386 + while (lq_r32(LQ_DMA_CCTRL) & 1)
1387 + ;
1388 +
1389 + local_irq_restore(flag);
1390 + for (j = 0; j < pCh->desc_len; j++) {
1391 + rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
1392 + if ((rx_desc_p->status.field.OWN == CPU_OWN
1393 + && rx_desc_p->status.field.C)
1394 + || (rx_desc_p->status.field.OWN == DMA_OWN
1395 + && rx_desc_p->status.field.data_length > 0)) {
1396 + dev->buffer_free((u8 *)
1397 + __va(rx_desc_p->Data_Pointer),
1398 + (void *) pCh->opt[j]);
1399 + }
1400 + }
1401 + }
1402 +}
1403 +EXPORT_SYMBOL(dma_device_unregister);
1404 +
1405 +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
1406 +{
1407 + u8 *buf;
1408 + int len;
1409 + int byte_offset = 0;
1410 + void *p = NULL;
1411 + struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
1412 + struct rx_desc *rx_desc_p;
1413 +
1414 + /* get the rx data first */
1415 + rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
1416 + if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
1417 + return 0;
1418 +
1419 + buf = (u8 *) __va(rx_desc_p->Data_Pointer);
1420 + *(u32 *)dataptr = (u32)buf;
1421 + len = rx_desc_p->status.field.data_length;
1422 +
1423 + if (opt)
1424 + *(int *)opt = (int)pCh->opt[pCh->curr_desc];
1425 +
1426 + /* replace with a new allocated buffer */
1427 + buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
1428 +
1429 + if (buf) {
1430 + dma_cache_inv((unsigned long) buf, pCh->packet_size);
1431 + pCh->opt[pCh->curr_desc] = p;
1432 + wmb();
1433 +
1434 + rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
1435 + rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
1436 + wmb();
1437 + } else {
1438 + *(u32 *) dataptr = 0;
1439 + if (opt)
1440 + *(int *) opt = 0;
1441 + len = 0;
1442 + }
1443 +
1444 + /* increase the curr_desc pointer */
1445 + pCh->curr_desc++;
1446 + if (pCh->curr_desc == pCh->desc_len)
1447 + pCh->curr_desc = 0;
1448 +
1449 + return len;
1450 +}
1451 +EXPORT_SYMBOL(dma_device_read);
1452 +
1453 +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
1454 +{
1455 + unsigned long flag;
1456 + u32 tmp, byte_offset;
1457 + struct dma_channel_info *pCh;
1458 + int chan_no;
1459 + struct tx_desc *tx_desc_p;
1460 + local_irq_save(flag);
1461 +
1462 + pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
1463 + chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
1464 +
1465 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1466 + while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
1467 + dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
1468 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1469 + pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
1470 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1471 + }
1472 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
1473 + /* Check whether this descriptor is available */
1474 + if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
1475 + /* if not, the tell the upper layer device */
1476 + dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1477 + local_irq_restore(flag);
1478 + printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
1479 +
1480 + return 0;
1481 + }
1482 + pCh->opt[pCh->curr_desc] = opt;
1483 + /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
1484 + byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
1485 + dma_cache_wback((unsigned long) dataptr, len);
1486 + wmb();
1487 + tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
1488 + wmb();
1489 + tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
1490 + wmb();
1491 +
1492 + pCh->curr_desc++;
1493 + if (pCh->curr_desc == pCh->desc_len)
1494 + pCh->curr_desc = 0;
1495 +
1496 + /*Check whether this descriptor is available */
1497 + tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
1498 + if (tx_desc_p->status.field.OWN == DMA_OWN) {
1499 + /*if not , the tell the upper layer device */
1500 + dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1501 + }
1502 +
1503 + lq_w32(chan_no, LQ_DMA_CS);
1504 + tmp = lq_r32(LQ_DMA_CCTRL);
1505 +
1506 + if (!(tmp & 1))
1507 + pCh->open(pCh);
1508 +
1509 + local_irq_restore(flag);
1510 +
1511 + return len;
1512 +}
1513 +EXPORT_SYMBOL(dma_device_write);
1514 +
1515 +int map_dma_chan(struct dma_chan_map *map)
1516 +{
1517 + int i, j;
1518 + int result;
1519 +
1520 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
1521 + strcpy(dma_devs[i].device_name, global_device_name[i]);
1522 +
1523 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1524 + dma_chan[i].irq = map[i].irq;
1525 + result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
1526 + if (result) {
1527 + printk(KERN_WARNING "error, cannot get dma_irq!\n");
1528 + free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
1529 +
1530 + return -EFAULT;
1531 + }
1532 + }
1533 +
1534 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1535 + dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */
1536 + dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */
1537 + dma_devs[i].max_rx_chan_num = 0;
1538 + dma_devs[i].max_tx_chan_num = 0;
1539 + dma_devs[i].buffer_alloc = &common_buffer_alloc;
1540 + dma_devs[i].buffer_free = &common_buffer_free;
1541 + dma_devs[i].intr_handler = NULL;
1542 + dma_devs[i].tx_burst_len = 4;
1543 + dma_devs[i].rx_burst_len = 4;
1544 + if (i == 0) {
1545 + lq_w32(0, LQ_DMA_PS);
1546 + lq_w32(lq_r32(LQ_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), LQ_DMA_PCTRL); /*enable dma drop */
1547 + }
1548 +
1549 + if (i == 1) {
1550 + lq_w32(1, LQ_DMA_PS);
1551 + lq_w32(0x14, LQ_DMA_PCTRL); /*deu port setting */
1552 + }
1553 +
1554 + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1555 + dma_chan[j].byte_offset = 0;
1556 + dma_chan[j].open = &open_chan;
1557 + dma_chan[j].close = &close_chan;
1558 + dma_chan[j].reset = &reset_chan;
1559 + dma_chan[j].enable_irq = &enable_ch_irq;
1560 + dma_chan[j].disable_irq = &disable_ch_irq;
1561 + dma_chan[j].rel_chan_no = map[j].rel_chan_no;
1562 + dma_chan[j].control = LQ_DMA_CH_OFF;
1563 + dma_chan[j].default_weight = LQ_DMA_CH_DEFAULT_WEIGHT;
1564 + dma_chan[j].weight = dma_chan[j].default_weight;
1565 + dma_chan[j].curr_desc = 0;
1566 + dma_chan[j].prev_desc = 0;
1567 + }
1568 +
1569 + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1570 + if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
1571 + if (map[j].dir == LQ_DMA_RX) {
1572 + dma_chan[j].dir = LQ_DMA_RX;
1573 + dma_devs[i].max_rx_chan_num++;
1574 + dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
1575 + dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
1576 + dma_chan[j].dma_dev = (void *)&dma_devs[i];
1577 + } else if (map[j].dir == LQ_DMA_TX) {
1578 + /*TX direction */
1579 + dma_chan[j].dir = LQ_DMA_TX;
1580 + dma_devs[i].max_tx_chan_num++;
1581 + dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
1582 + dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
1583 + dma_chan[j].dma_dev = (void *)&dma_devs[i];
1584 + } else {
1585 + printk(KERN_WARNING "WRONG DMA MAP!\n");
1586 + }
1587 + }
1588 + }
1589 + }
1590 +
1591 + return 0;
1592 +}
1593 +
1594 +void dma_chip_init(void)
1595 +{
1596 + int i;
1597 +
1598 + /* enable DMA from PMU */
1599 + lq_pmu_enable(PMU_DMA);
1600 +
1601 + /* reset DMA */
1602 + lq_w32(lq_r32(LQ_DMA_CTRL) | 1, LQ_DMA_CTRL);
1603 +
1604 + /* disable all interrupts */
1605 + lq_w32(0, LQ_DMA_IRNEN);
1606 +
1607 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1608 + lq_w32(i, LQ_DMA_CS);
1609 + lq_w32(0x2, LQ_DMA_CCTRL);
1610 + lq_w32(0x80000040, LQ_DMA_CPOLL);
1611 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~0x1, LQ_DMA_CCTRL);
1612 + }
1613 +}
1614 +
1615 +int lq_dma_init(void)
1616 +{
1617 + int i;
1618 +
1619 + dma_chip_init();
1620 +
1621 + if (map_dma_chan(default_dma_map))
1622 + BUG();
1623 +
1624 + g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
1625 +
1626 + if (g_desc_list == NULL) {
1627 + printk(KERN_WARNING "no memory for desriptor\n");
1628 + return -ENOMEM;
1629 + }
1630 +
1631 + memset(g_desc_list, 0, PAGE_SIZE);
1632 +
1633 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1634 + dma_chan[i].desc_base = (u32)g_desc_list + i * LQ_DMA_DESCRIPTOR_OFFSET * 8;
1635 + dma_chan[i].curr_desc = 0;
1636 + dma_chan[i].desc_len = LQ_DMA_DESCRIPTOR_OFFSET;
1637 +
1638 + lq_w32(i, LQ_DMA_CS);
1639 + lq_w32((u32)CPHYSADDR(dma_chan[i].desc_base), LQ_DMA_CDBA);
1640 + lq_w32(dma_chan[i].desc_len, LQ_DMA_CDLEN);
1641 + }
1642 + return 0;
1643 +}
1644 +
1645 +arch_initcall(lq_dma_init);
1646 +
1647 +void dma_cleanup(void)
1648 +{
1649 + int i;
1650 +
1651 + free_page(KSEG0ADDR((unsigned long) g_desc_list));
1652 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1653 + free_irq(dma_chan[i].irq, (void *)&dma_interrupt);
1654 +}
1655 +
1656 +MODULE_LICENSE("GPL");
1657 --- /dev/null
1658 +++ b/arch/mips/lantiq/xway/pmu.c
1659 @@ -0,0 +1,36 @@
1660 +/*
1661 + * This program is free software; you can redistribute it and/or modify it
1662 + * under the terms of the GNU General Public License version 2 as published
1663 + * by the Free Software Foundation.
1664 + *
1665 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1666 + */
1667 +
1668 +#include <linux/kernel.h>
1669 +#include <linux/module.h>
1670 +#include <linux/version.h>
1671 +
1672 +#include <xway.h>
1673 +
1674 +#define LQ_PMU_PWDCR ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
1675 +#define LQ_PMU_PWDSR ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
1676 +
1677 +void
1678 +lq_pmu_enable(unsigned int module)
1679 +{
1680 + int err = 1000000;
1681 +
1682 + lq_w32(lq_r32(LQ_PMU_PWDCR) & ~module, LQ_PMU_PWDCR);
1683 + while (--err && (lq_r32(LQ_PMU_PWDSR) & module));
1684 +
1685 + if (!err)
1686 + panic("activating PMU module failed!");
1687 +}
1688 +EXPORT_SYMBOL(lq_pmu_enable);
1689 +
1690 +void
1691 +lq_pmu_disable(unsigned int module)
1692 +{
1693 + lq_w32(lq_r32(LQ_PMU_PWDCR) | module, LQ_PMU_PWDCR);
1694 +}
1695 +EXPORT_SYMBOL(lq_pmu_disable);
1696 --- /dev/null
1697 +++ b/arch/mips/lantiq/xway/timer.c
1698 @@ -0,0 +1,828 @@
1699 +#include <linux/kernel.h>
1700 +#include <linux/module.h>
1701 +#include <linux/version.h>
1702 +#include <linux/types.h>
1703 +#include <linux/fs.h>
1704 +#include <linux/miscdevice.h>
1705 +#include <linux/init.h>
1706 +#include <linux/uaccess.h>
1707 +#include <linux/unistd.h>
1708 +#include <linux/errno.h>
1709 +#include <linux/interrupt.h>
1710 +#include <linux/sched.h>
1711 +
1712 +#include <asm/irq.h>
1713 +#include <asm/div64.h>
1714 +
1715 +#include <xway.h>
1716 +#include <xway_irq.h>
1717 +#include <lantiq_timer.h>
1718 +
1719 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
1720 +
1721 +#ifdef TIMER1A
1722 +#define FIRST_TIMER TIMER1A
1723 +#else
1724 +#define FIRST_TIMER 2
1725 +#endif
1726 +
1727 +/*
1728 + * GPTC divider is set or not.
1729 + */
1730 +#define GPTU_CLC_RMC_IS_SET 0
1731 +
1732 +/*
1733 + * Timer Interrupt (IRQ)
1734 + */
1735 +/* Must be adjusted when ICU driver is available */
1736 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
1737 +
1738 +/*
1739 + * Bits Operation
1740 + */
1741 +#define GET_BITS(x, msb, lsb) \
1742 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
1743 +#define SET_BITS(x, msb, lsb, value) \
1744 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
1745 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
1746 +
1747 +/*
1748 + * GPTU Register Mapping
1749 + */
1750 +#define LQ_GPTU (KSEG1 + 0x1E100A00)
1751 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
1752 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
1753 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1754 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1755 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1756 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1757 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
1758 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
1759 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
1760 +
1761 +/*
1762 + * Clock Control Register
1763 + */
1764 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
1765 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
1766 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
1767 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
1768 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
1769 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
1770 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
1771 +
1772 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
1773 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
1774 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
1775 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
1776 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
1777 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
1778 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
1779 +
1780 +/*
1781 + * ID Register
1782 + */
1783 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
1784 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
1785 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
1786 +
1787 +/*
1788 + * Control Register of Timer/Counter nX
1789 + * n is the index of block (1 based index)
1790 + * X is either A or B
1791 + */
1792 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
1793 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
1794 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
1795 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
1796 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
1797 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
1798 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
1799 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
1800 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
1801 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
1802 +
1803 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
1804 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
1805 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
1806 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
1807 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
1808 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
1809 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
1810 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
1811 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
1812 +
1813 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
1814 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
1815 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
1816 +
1817 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1818 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1819 +
1820 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
1821 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
1822 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
1823 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
1824 +#define TIMER_FLAG_NONE_EDGE 0x0000
1825 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
1826 +#define TIMER_FLAG_REAL 0x0000
1827 +#define TIMER_FLAG_INVERT 0x0040
1828 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
1829 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
1830 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
1831 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
1832 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
1833 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
1834 +
1835 +struct timer_dev_timer {
1836 + unsigned int f_irq_on;
1837 + unsigned int irq;
1838 + unsigned int flag;
1839 + unsigned long arg1;
1840 + unsigned long arg2;
1841 +};
1842 +
1843 +struct timer_dev {
1844 + struct mutex gptu_mutex;
1845 + unsigned int number_of_timers;
1846 + unsigned int occupation;
1847 + unsigned int f_gptu_on;
1848 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
1849 +};
1850 +
1851 +static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
1852 +static int gptu_open(struct inode *, struct file *);
1853 +static int gptu_release(struct inode *, struct file *);
1854 +
1855 +static struct file_operations gptu_fops = {
1856 + .owner = THIS_MODULE,
1857 + .ioctl = gptu_ioctl,
1858 + .open = gptu_open,
1859 + .release = gptu_release
1860 +};
1861 +
1862 +static struct miscdevice gptu_miscdev = {
1863 + .minor = MISC_DYNAMIC_MINOR,
1864 + .name = "gptu",
1865 + .fops = &gptu_fops,
1866 +};
1867 +
1868 +static struct timer_dev timer_dev;
1869 +
1870 +static irqreturn_t timer_irq_handler(int irq, void *p)
1871 +{
1872 + unsigned int timer;
1873 + unsigned int flag;
1874 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
1875 +
1876 + timer = irq - TIMER_INTERRUPT;
1877 + if (timer < timer_dev.number_of_timers
1878 + && dev_timer == &timer_dev.timer[timer]) {
1879 + /* Clear interrupt. */
1880 + lq_w32(1 << timer, LQ_GPTU_IRNCR);
1881 +
1882 + /* Call user hanler or signal. */
1883 + flag = dev_timer->flag;
1884 + if (!(timer & 0x01)
1885 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1886 + /* 16-bit timer or timer A of 32-bit timer */
1887 + switch (TIMER_FLAG_MASK_HANDLE(flag)) {
1888 + case TIMER_FLAG_CALLBACK_IN_IRQ:
1889 + case TIMER_FLAG_CALLBACK_IN_HB:
1890 + if (dev_timer->arg1)
1891 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
1892 + break;
1893 + case TIMER_FLAG_SIGNAL:
1894 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
1895 + break;
1896 + }
1897 + }
1898 + }
1899 + return IRQ_HANDLED;
1900 +}
1901 +
1902 +static inline void lq_enable_gptu(void)
1903 +{
1904 + lq_pmu_enable(PMU_GPT);
1905 +
1906 + /* Set divider as 1, disable write protection for SPEN, enable module. */
1907 + *LQ_GPTU_CLC =
1908 + GPTU_CLC_SMC_SET(0x00) |
1909 + GPTU_CLC_RMC_SET(0x01) |
1910 + GPTU_CLC_FSOE_SET(0) |
1911 + GPTU_CLC_SBWE_SET(1) |
1912 + GPTU_CLC_EDIS_SET(0) |
1913 + GPTU_CLC_SPEN_SET(0) |
1914 + GPTU_CLC_DISR_SET(0);
1915 +}
1916 +
1917 +static inline void lq_disable_gptu(void)
1918 +{
1919 + lq_w32(0x00, LQ_GPTU_IRNEN);
1920 + lq_w32(0xfff, LQ_GPTU_IRNCR);
1921 +
1922 + /* Set divider as 0, enable write protection for SPEN, disable module. */
1923 + *LQ_GPTU_CLC =
1924 + GPTU_CLC_SMC_SET(0x00) |
1925 + GPTU_CLC_RMC_SET(0x00) |
1926 + GPTU_CLC_FSOE_SET(0) |
1927 + GPTU_CLC_SBWE_SET(0) |
1928 + GPTU_CLC_EDIS_SET(0) |
1929 + GPTU_CLC_SPEN_SET(0) |
1930 + GPTU_CLC_DISR_SET(1);
1931 +
1932 + lq_pmu_disable(PMU_GPT);
1933 +}
1934 +
1935 +int lq_request_timer(unsigned int timer, unsigned int flag,
1936 + unsigned long value, unsigned long arg1, unsigned long arg2)
1937 +{
1938 + int ret = 0;
1939 + unsigned int con_reg, irnen_reg;
1940 + int n, X;
1941 +
1942 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
1943 + return -EINVAL;
1944 +
1945 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
1946 + timer, flag, value);
1947 +
1948 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
1949 + value &= 0xFFFF;
1950 + else
1951 + timer &= ~0x01;
1952 +
1953 + mutex_lock(&timer_dev.gptu_mutex);
1954 +
1955 + /*
1956 + * Allocate timer.
1957 + */
1958 + if (timer < FIRST_TIMER) {
1959 + unsigned int mask;
1960 + unsigned int shift;
1961 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
1962 + unsigned int offset = TIMER2A;
1963 +
1964 + /*
1965 + * Pick up a free timer.
1966 + */
1967 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1968 + mask = 1 << offset;
1969 + shift = 1;
1970 + } else {
1971 + mask = 3 << offset;
1972 + shift = 2;
1973 + }
1974 + for (timer = offset;
1975 + timer < offset + timer_dev.number_of_timers;
1976 + timer += shift, mask <<= shift)
1977 + if (!(timer_dev.occupation & mask)) {
1978 + timer_dev.occupation |= mask;
1979 + break;
1980 + }
1981 + if (timer >= offset + timer_dev.number_of_timers) {
1982 + printk("failed![%d]\n", __LINE__);
1983 + mutex_unlock(&timer_dev.gptu_mutex);
1984 + return -EINVAL;
1985 + } else
1986 + ret = timer;
1987 + } else {
1988 + register unsigned int mask;
1989 +
1990 + /*
1991 + * Check if the requested timer is free.
1992 + */
1993 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
1994 + if ((timer_dev.occupation & mask)) {
1995 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
1996 + __LINE__, mask, timer_dev.occupation);
1997 + mutex_unlock(&timer_dev.gptu_mutex);
1998 + return -EBUSY;
1999 + } else {
2000 + timer_dev.occupation |= mask;
2001 + ret = 0;
2002 + }
2003 + }
2004 +
2005 + /*
2006 + * Prepare control register value.
2007 + */
2008 + switch (TIMER_FLAG_MASK_EDGE(flag)) {
2009 + default:
2010 + case TIMER_FLAG_NONE_EDGE:
2011 + con_reg = GPTU_CON_EDGE_SET(0x00);
2012 + break;
2013 + case TIMER_FLAG_RISE_EDGE:
2014 + con_reg = GPTU_CON_EDGE_SET(0x01);
2015 + break;
2016 + case TIMER_FLAG_FALL_EDGE:
2017 + con_reg = GPTU_CON_EDGE_SET(0x02);
2018 + break;
2019 + case TIMER_FLAG_ANY_EDGE:
2020 + con_reg = GPTU_CON_EDGE_SET(0x03);
2021 + break;
2022 + }
2023 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
2024 + con_reg |=
2025 + TIMER_FLAG_MASK_SRC(flag) ==
2026 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
2027 + GPTU_CON_SRC_EXT_SET(0);
2028 + else
2029 + con_reg |=
2030 + TIMER_FLAG_MASK_SRC(flag) ==
2031 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
2032 + GPTU_CON_SRC_EG_SET(0);
2033 + con_reg |=
2034 + TIMER_FLAG_MASK_SYNC(flag) ==
2035 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
2036 + GPTU_CON_SYNC_SET(1);
2037 + con_reg |=
2038 + TIMER_FLAG_MASK_INVERT(flag) ==
2039 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2040 + con_reg |=
2041 + TIMER_FLAG_MASK_SIZE(flag) ==
2042 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
2043 + GPTU_CON_EXT_SET(1);
2044 + con_reg |=
2045 + TIMER_FLAG_MASK_STOP(flag) ==
2046 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2047 + con_reg |=
2048 + TIMER_FLAG_MASK_TYPE(flag) ==
2049 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
2050 + GPTU_CON_CNT_SET(1);
2051 + con_reg |=
2052 + TIMER_FLAG_MASK_DIR(flag) ==
2053 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2054 +
2055 + /*
2056 + * Fill up running data.
2057 + */
2058 + timer_dev.timer[timer - FIRST_TIMER].flag = flag;
2059 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
2060 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
2061 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2062 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
2063 +
2064 + /*
2065 + * Enable GPTU module.
2066 + */
2067 + if (!timer_dev.f_gptu_on) {
2068 + lq_enable_gptu();
2069 + timer_dev.f_gptu_on = 1;
2070 + }
2071 +
2072 + /*
2073 + * Enable IRQ.
2074 + */
2075 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
2076 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
2077 + timer_dev.timer[timer - FIRST_TIMER].arg1 =
2078 + (unsigned long) find_task_by_vpid((int) arg1);
2079 +
2080 + irnen_reg = 1 << (timer - FIRST_TIMER);
2081 +
2082 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
2083 + || (TIMER_FLAG_MASK_HANDLE(flag) ==
2084 + TIMER_FLAG_CALLBACK_IN_IRQ
2085 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
2086 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2087 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
2088 + }
2089 + } else
2090 + irnen_reg = 0;
2091 +
2092 + /*
2093 + * Write config register, reload value and enable interrupt.
2094 + */
2095 + n = timer >> 1;
2096 + X = timer & 0x01;
2097 + *LQ_GPTU_CON(n, X) = con_reg;
2098 + *LQ_GPTU_RELOAD(n, X) = value;
2099 + /* printk("reload value = %d\n", (u32)value); */
2100 + *LQ_GPTU_IRNEN |= irnen_reg;
2101 +
2102 + mutex_unlock(&timer_dev.gptu_mutex);
2103 + printk("successful!\n");
2104 + return ret;
2105 +}
2106 +EXPORT_SYMBOL(lq_request_timer);
2107 +
2108 +int lq_free_timer(unsigned int timer)
2109 +{
2110 + unsigned int flag;
2111 + unsigned int mask;
2112 + int n, X;
2113 +
2114 + if (!timer_dev.f_gptu_on)
2115 + return -EINVAL;
2116 +
2117 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2118 + return -EINVAL;
2119 +
2120 + mutex_lock(&timer_dev.gptu_mutex);
2121 +
2122 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2123 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2124 + timer &= ~0x01;
2125 +
2126 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2127 + if (((timer_dev.occupation & mask) ^ mask)) {
2128 + mutex_unlock(&timer_dev.gptu_mutex);
2129 + return -EINVAL;
2130 + }
2131 +
2132 + n = timer >> 1;
2133 + X = timer & 0x01;
2134 +
2135 + if (GPTU_CON_EN(n, X))
2136 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2137 +
2138 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
2139 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
2140 +
2141 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
2142 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2143 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
2144 + }
2145 +
2146 + timer_dev.occupation &= ~mask;
2147 + if (!timer_dev.occupation && timer_dev.f_gptu_on) {
2148 + lq_disable_gptu();
2149 + timer_dev.f_gptu_on = 0;
2150 + }
2151 +
2152 + mutex_unlock(&timer_dev.gptu_mutex);
2153 +
2154 + return 0;
2155 +}
2156 +EXPORT_SYMBOL(lq_free_timer);
2157 +
2158 +int lq_start_timer(unsigned int timer, int is_resume)
2159 +{
2160 + unsigned int flag;
2161 + unsigned int mask;
2162 + int n, X;
2163 +
2164 + if (!timer_dev.f_gptu_on)
2165 + return -EINVAL;
2166 +
2167 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2168 + return -EINVAL;
2169 +
2170 + mutex_lock(&timer_dev.gptu_mutex);
2171 +
2172 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2173 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2174 + timer &= ~0x01;
2175 +
2176 + mask = (TIMER_FLAG_MASK_SIZE(flag) ==
2177 + TIMER_FLAG_16BIT ? 1 : 3) << timer;
2178 + if (((timer_dev.occupation & mask) ^ mask)) {
2179 + mutex_unlock(&timer_dev.gptu_mutex);
2180 + return -EINVAL;
2181 + }
2182 +
2183 + n = timer >> 1;
2184 + X = timer & 0x01;
2185 +
2186 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
2187 +
2188 + mutex_unlock(&timer_dev.gptu_mutex);
2189 +
2190 + return 0;
2191 +}
2192 +EXPORT_SYMBOL(lq_start_timer);
2193 +
2194 +int lq_stop_timer(unsigned int timer)
2195 +{
2196 + unsigned int flag;
2197 + unsigned int mask;
2198 + int n, X;
2199 +
2200 + if (!timer_dev.f_gptu_on)
2201 + return -EINVAL;
2202 +
2203 + if (timer < FIRST_TIMER
2204 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2205 + return -EINVAL;
2206 +
2207 + mutex_lock(&timer_dev.gptu_mutex);
2208 +
2209 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2210 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2211 + timer &= ~0x01;
2212 +
2213 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2214 + if (((timer_dev.occupation & mask) ^ mask)) {
2215 + mutex_unlock(&timer_dev.gptu_mutex);
2216 + return -EINVAL;
2217 + }
2218 +
2219 + n = timer >> 1;
2220 + X = timer & 0x01;
2221 +
2222 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2223 +
2224 + mutex_unlock(&timer_dev.gptu_mutex);
2225 +
2226 + return 0;
2227 +}
2228 +EXPORT_SYMBOL(lq_stop_timer);
2229 +
2230 +int lq_reset_counter_flags(u32 timer, u32 flags)
2231 +{
2232 + unsigned int oflag;
2233 + unsigned int mask, con_reg;
2234 + int n, X;
2235 +
2236 + if (!timer_dev.f_gptu_on)
2237 + return -EINVAL;
2238 +
2239 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2240 + return -EINVAL;
2241 +
2242 + mutex_lock(&timer_dev.gptu_mutex);
2243 +
2244 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
2245 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
2246 + timer &= ~0x01;
2247 +
2248 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2249 + if (((timer_dev.occupation & mask) ^ mask)) {
2250 + mutex_unlock(&timer_dev.gptu_mutex);
2251 + return -EINVAL;
2252 + }
2253 +
2254 + switch (TIMER_FLAG_MASK_EDGE(flags)) {
2255 + default:
2256 + case TIMER_FLAG_NONE_EDGE:
2257 + con_reg = GPTU_CON_EDGE_SET(0x00);
2258 + break;
2259 + case TIMER_FLAG_RISE_EDGE:
2260 + con_reg = GPTU_CON_EDGE_SET(0x01);
2261 + break;
2262 + case TIMER_FLAG_FALL_EDGE:
2263 + con_reg = GPTU_CON_EDGE_SET(0x02);
2264 + break;
2265 + case TIMER_FLAG_ANY_EDGE:
2266 + con_reg = GPTU_CON_EDGE_SET(0x03);
2267 + break;
2268 + }
2269 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
2270 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
2271 + else
2272 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
2273 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
2274 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2275 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
2276 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2277 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
2278 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2279 +
2280 + timer_dev.timer[timer - FIRST_TIMER].flag = flags;
2281 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
2282 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
2283 +
2284 + n = timer >> 1;
2285 + X = timer & 0x01;
2286 +
2287 + *LQ_GPTU_CON(n, X) = con_reg;
2288 + smp_wmb();
2289 + printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
2290 + mutex_unlock(&timer_dev.gptu_mutex);
2291 + return 0;
2292 +}
2293 +EXPORT_SYMBOL(lq_reset_counter_flags);
2294 +
2295 +int lq_get_count_value(unsigned int timer, unsigned long *value)
2296 +{
2297 + unsigned int flag;
2298 + unsigned int mask;
2299 + int n, X;
2300 +
2301 + if (!timer_dev.f_gptu_on)
2302 + return -EINVAL;
2303 +
2304 + if (timer < FIRST_TIMER
2305 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2306 + return -EINVAL;
2307 +
2308 + mutex_lock(&timer_dev.gptu_mutex);
2309 +
2310 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2311 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2312 + timer &= ~0x01;
2313 +
2314 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2315 + if (((timer_dev.occupation & mask) ^ mask)) {
2316 + mutex_unlock(&timer_dev.gptu_mutex);
2317 + return -EINVAL;
2318 + }
2319 +
2320 + n = timer >> 1;
2321 + X = timer & 0x01;
2322 +
2323 + *value = *LQ_GPTU_COUNT(n, X);
2324 +
2325 + mutex_unlock(&timer_dev.gptu_mutex);
2326 +
2327 + return 0;
2328 +}
2329 +EXPORT_SYMBOL(lq_get_count_value);
2330 +
2331 +u32 lq_cal_divider(unsigned long freq)
2332 +{
2333 + u64 module_freq, fpi = lq_get_fpi_bus_clock(2);
2334 + u32 clock_divider = 1;
2335 + module_freq = fpi * 1000;
2336 + do_div(module_freq, clock_divider * freq);
2337 + return module_freq;
2338 +}
2339 +EXPORT_SYMBOL(lq_cal_divider);
2340 +
2341 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
2342 + int is_ext_src, unsigned int handle_flag, unsigned long arg1,
2343 + unsigned long arg2)
2344 +{
2345 + unsigned long divider;
2346 + unsigned int flag;
2347 +
2348 + divider = lq_cal_divider(freq);
2349 + if (divider == 0)
2350 + return -EINVAL;
2351 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
2352 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
2353 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
2354 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
2355 + | TIMER_FLAG_MASK_HANDLE(handle_flag);
2356 +
2357 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
2358 + timer, freq, divider);
2359 + return lq_request_timer(timer, flag, divider, arg1, arg2);
2360 +}
2361 +EXPORT_SYMBOL(lq_set_timer);
2362 +
2363 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
2364 + unsigned long arg1, unsigned long arg2)
2365 +{
2366 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
2367 + return lq_request_timer(timer, flag, reload, arg1, arg2);
2368 +}
2369 +EXPORT_SYMBOL(lq_set_counter);
2370 +
2371 +static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
2372 + unsigned long arg)
2373 +{
2374 + int ret;
2375 + struct gptu_ioctl_param param;
2376 +
2377 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
2378 + return -EFAULT;
2379 + copy_from_user(&param, (void *) arg, sizeof(param));
2380 +
2381 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
2382 + || GPTU_SET_COUNTER) && param.timer < 2)
2383 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
2384 + && !access_ok(VERIFY_WRITE, arg,
2385 + sizeof(struct gptu_ioctl_param)))
2386 + return -EFAULT;
2387 +
2388 + switch (cmd) {
2389 + case GPTU_REQUEST_TIMER:
2390 + ret = lq_request_timer(param.timer, param.flag, param.value,
2391 + (unsigned long) param.pid,
2392 + (unsigned long) param.sig);
2393 + if (ret > 0) {
2394 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2395 + timer, &ret, sizeof(&ret));
2396 + ret = 0;
2397 + }
2398 + break;
2399 + case GPTU_FREE_TIMER:
2400 + ret = lq_free_timer(param.timer);
2401 + break;
2402 + case GPTU_START_TIMER:
2403 + ret = lq_start_timer(param.timer, param.flag);
2404 + break;
2405 + case GPTU_STOP_TIMER:
2406 + ret = lq_stop_timer(param.timer);
2407 + break;
2408 + case GPTU_GET_COUNT_VALUE:
2409 + ret = lq_get_count_value(param.timer, &param.value);
2410 + if (!ret)
2411 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2412 + value, &param.value,
2413 + sizeof(param.value));
2414 + break;
2415 + case GPTU_CALCULATE_DIVIDER:
2416 + param.value = lq_cal_divider(param.value);
2417 + if (param.value == 0)
2418 + ret = -EINVAL;
2419 + else {
2420 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2421 + value, &param.value,
2422 + sizeof(param.value));
2423 + ret = 0;
2424 + }
2425 + break;
2426 + case GPTU_SET_TIMER:
2427 + ret = lq_set_timer(param.timer, param.value,
2428 + TIMER_FLAG_MASK_STOP(param.flag) !=
2429 + TIMER_FLAG_ONCE ? 1 : 0,
2430 + TIMER_FLAG_MASK_SRC(param.flag) ==
2431 + TIMER_FLAG_EXT_SRC ? 1 : 0,
2432 + TIMER_FLAG_MASK_HANDLE(param.flag) ==
2433 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
2434 + TIMER_FLAG_NO_HANDLE,
2435 + (unsigned long) param.pid,
2436 + (unsigned long) param.sig);
2437 + if (ret > 0) {
2438 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2439 + timer, &ret, sizeof(&ret));
2440 + ret = 0;
2441 + }
2442 + break;
2443 + case GPTU_SET_COUNTER:
2444 + lq_set_counter(param.timer, param.flag, param.value, 0, 0);
2445 + if (ret > 0) {
2446 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2447 + timer, &ret, sizeof(&ret));
2448 + ret = 0;
2449 + }
2450 + break;
2451 + default:
2452 + ret = -ENOTTY;
2453 + }
2454 +
2455 + return ret;
2456 +}
2457 +
2458 +static int gptu_open(struct inode *inode, struct file *file)
2459 +{
2460 + return 0;
2461 +}
2462 +
2463 +static int gptu_release(struct inode *inode, struct file *file)
2464 +{
2465 + return 0;
2466 +}
2467 +
2468 +int __init lq_gptu_init(void)
2469 +{
2470 + int ret;
2471 + unsigned int i;
2472 +
2473 + lq_w32(0, LQ_GPTU_IRNEN);
2474 + lq_w32(0xfff, LQ_GPTU_IRNCR);
2475 +
2476 + memset(&timer_dev, 0, sizeof(timer_dev));
2477 + mutex_init(&timer_dev.gptu_mutex);
2478 +
2479 + lq_enable_gptu();
2480 + timer_dev.number_of_timers = GPTU_ID_CFG * 2;
2481 + lq_disable_gptu();
2482 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
2483 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
2484 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
2485 +
2486 + ret = misc_register(&gptu_miscdev);
2487 + if (ret) {
2488 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
2489 + return ret;
2490 + } else {
2491 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
2492 + }
2493 +
2494 + for (i = 0; i < timer_dev.number_of_timers; i++) {
2495 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
2496 + if (ret) {
2497 + for (; i >= 0; i--)
2498 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
2499 + misc_deregister(&gptu_miscdev);
2500 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
2501 + return ret;
2502 + } else {
2503 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
2504 + disable_irq(timer_dev.timer[i].irq);
2505 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
2506 + }
2507 + }
2508 +
2509 + return 0;
2510 +}
2511 +
2512 +void __exit lq_gptu_exit(void)
2513 +{
2514 + unsigned int i;
2515 +
2516 + for (i = 0; i < timer_dev.number_of_timers; i++) {
2517 + if (timer_dev.timer[i].f_irq_on)
2518 + disable_irq(timer_dev.timer[i].irq);
2519 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
2520 + }
2521 + lq_disable_gptu();
2522 + misc_deregister(&gptu_miscdev);
2523 +}
2524 +
2525 +module_init(lq_gptu_init);
2526 +module_exit(lq_gptu_exit);
2527 --- /dev/null
2528 +++ b/arch/mips/lantiq/xway/timer.h
2529 @@ -0,0 +1,155 @@
2530 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2531 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2532 +
2533 +
2534 +/******************************************************************************
2535 + Copyright (c) 2002, Infineon Technologies. All rights reserved.
2536 +
2537 + No Warranty
2538 + Because the program is licensed free of charge, there is no warranty for
2539 + the program, to the extent permitted by applicable law. Except when
2540 + otherwise stated in writing the copyright holders and/or other parties
2541 + provide the program "as is" without warranty of any kind, either
2542 + expressed or implied, including, but not limited to, the implied
2543 + warranties of merchantability and fitness for a particular purpose. The
2544 + entire risk as to the quality and performance of the program is with
2545 + you. should the program prove defective, you assume the cost of all
2546 + necessary servicing, repair or correction.
2547 +
2548 + In no event unless required by applicable law or agreed to in writing
2549 + will any copyright holder, or any other party who may modify and/or
2550 + redistribute the program as permitted above, be liable to you for
2551 + damages, including any general, special, incidental or consequential
2552 + damages arising out of the use or inability to use the program
2553 + (including but not limited to loss of data or data being rendered
2554 + inaccurate or losses sustained by you or third parties or a failure of
2555 + the program to operate with any other programs), even if such holder or
2556 + other party has been advised of the possibility of such damages.
2557 +******************************************************************************/
2558 +
2559 +
2560 +/*
2561 + * ####################################
2562 + * Definition
2563 + * ####################################
2564 + */
2565 +
2566 +/*
2567 + * Available Timer/Counter Index
2568 + */
2569 +#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
2570 +#define TIMER_ANY 0x00
2571 +#define TIMER1A TIMER(1, 0)
2572 +#define TIMER1B TIMER(1, 1)
2573 +#define TIMER2A TIMER(2, 0)
2574 +#define TIMER2B TIMER(2, 1)
2575 +#define TIMER3A TIMER(3, 0)
2576 +#define TIMER3B TIMER(3, 1)
2577 +
2578 +/*
2579 + * Flag of Timer/Counter
2580 + * These flags specify the way in which timer is configured.
2581 + */
2582 +/* Bit size of timer/counter. */
2583 +#define TIMER_FLAG_16BIT 0x0000
2584 +#define TIMER_FLAG_32BIT 0x0001
2585 +/* Switch between timer and counter. */
2586 +#define TIMER_FLAG_TIMER 0x0000
2587 +#define TIMER_FLAG_COUNTER 0x0002
2588 +/* Stop or continue when overflowing/underflowing. */
2589 +#define TIMER_FLAG_ONCE 0x0000
2590 +#define TIMER_FLAG_CYCLIC 0x0004
2591 +/* Count up or counter down. */
2592 +#define TIMER_FLAG_UP 0x0000
2593 +#define TIMER_FLAG_DOWN 0x0008
2594 +/* Count on specific level or edge. */
2595 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
2596 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
2597 +#define TIMER_FLAG_RISE_EDGE 0x0010
2598 +#define TIMER_FLAG_FALL_EDGE 0x0020
2599 +#define TIMER_FLAG_ANY_EDGE 0x0030
2600 +/* Signal is syncronous to module clock or not. */
2601 +#define TIMER_FLAG_UNSYNC 0x0000
2602 +#define TIMER_FLAG_SYNC 0x0080
2603 +/* Different interrupt handle type. */
2604 +#define TIMER_FLAG_NO_HANDLE 0x0000
2605 +#if defined(__KERNEL__)
2606 + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
2607 +#endif // defined(__KERNEL__)
2608 +#define TIMER_FLAG_SIGNAL 0x0300
2609 +/* Internal clock source or external clock source */
2610 +#define TIMER_FLAG_INT_SRC 0x0000
2611 +#define TIMER_FLAG_EXT_SRC 0x1000
2612 +
2613 +
2614 +/*
2615 + * ioctl Command
2616 + */
2617 +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
2618 +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
2619 +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
2620 +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
2621 +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
2622 +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
2623 +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
2624 +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
2625 +
2626 +/*
2627 + * Data Type Used to Call ioctl
2628 + */
2629 +struct gptu_ioctl_param {
2630 + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
2631 + * GPTU_SET_COUNTER, this field is ID of expected *
2632 + * timer/counter. If it's zero, a timer/counter would *
2633 + * be dynamically allocated and ID would be stored in *
2634 + * this field. *
2635 + * In command GPTU_GET_COUNT_VALUE, this field is *
2636 + * ignored. *
2637 + * In other command, this field is ID of timer/counter *
2638 + * allocated. */
2639 + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
2640 + * GPTU_SET_COUNTER, this field contains flags to *
2641 + * specify how to configure timer/counter. *
2642 + * In command GPTU_START_TIMER, zero indicate start *
2643 + * and non-zero indicate resume timer/counter. *
2644 + * In other command, this field is ignored. */
2645 + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
2646 + * init/reload value. *
2647 + * In command GPTU_SET_TIMER, this field contains *
2648 + * frequency (0.001Hz) of timer. *
2649 + * In command GPTU_GET_COUNT_VALUE, current count *
2650 + * value would be stored in this field. *
2651 + * In command GPTU_CALCULATE_DIVIDER, this field *
2652 + * contains frequency wanted, and after calculation, *
2653 + * divider would be stored in this field to overwrite *
2654 + * the frequency. *
2655 + * In other command, this field is ignored. */
2656 + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
2657 + * if signal is required, this field contains process *
2658 + * ID to which signal would be sent. *
2659 + * In other command, this field is ignored. */
2660 + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
2661 + * if signal is required, this field contains signal *
2662 + * number which would be sent. *
2663 + * In other command, this field is ignored. */
2664 +};
2665 +
2666 +/*
2667 + * ####################################
2668 + * Data Type
2669 + * ####################################
2670 + */
2671 +typedef void (*timer_callback)(unsigned long arg);
2672 +
2673 +extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
2674 +extern int ifxmips_free_timer(unsigned int);
2675 +extern int ifxmips_start_timer(unsigned int, int);
2676 +extern int ifxmips_stop_timer(unsigned int);
2677 +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
2678 +extern int ifxmips_get_count_value(unsigned int, unsigned long *);
2679 +extern u32 ifxmips_cal_divider(unsigned long);
2680 +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
2681 +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
2682 + u32 reload, unsigned long arg1, unsigned long arg2);
2683 +
2684 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
2685 --- /dev/null
2686 +++ b/arch/mips/lantiq/xway/Makefile
2687 @@ -0,0 +1,5 @@
2688 +obj-y := pmu.o prom.o dma.o timer.o reset.o clk-xway.o
2689 +obj-y += gpio.o gpio_ebu.o gpio_leds.o devices.o
2690 +obj-$(CONFIG_LANTIQ_MACH_EASY50812) += mach-easy50812.o
2691 +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
2692 +obj-$(CONFIG_LANTIQ_MACH_EASY4010) += mach-easy4010.o
2693 --- /dev/null
2694 +++ b/arch/mips/lantiq/xway/clk-xway.c
2695 @@ -0,0 +1,219 @@
2696 +/*
2697 + * This program is free software; you can redistribute it and/or modify it
2698 + * under the terms of the GNU General Public License version 2 as published
2699 + * by the Free Software Foundation.
2700 + *
2701 + * Copyright (C) 2007 Xu Liang, infineon
2702 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2703 + */
2704 +
2705 +#include <linux/io.h>
2706 +#include <linux/module.h>
2707 +#include <linux/init.h>
2708 +#include <linux/clk.h>
2709 +
2710 +#include <asm/time.h>
2711 +#include <asm/irq.h>
2712 +#include <asm/div64.h>
2713 +
2714 +#include <xway.h>
2715 +
2716 +static unsigned int lq_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
2717 +#define DDR_HZ lq_ram_clocks[lq_r32(LQ_CGU_SYS) & 0x3]
2718 +
2719 +#define BASIC_FREQUENCY_1 35328000
2720 +#define BASIC_FREQUENCY_2 36000000
2721 +#define BASIS_REQUENCY_USB 12000000
2722 +
2723 +#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
2724 +
2725 +#define CGU_PLL0_PHASE_DIVIDER_ENABLE (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 31))
2726 +#define CGU_PLL0_BYPASS (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 30))
2727 +#define CGU_PLL0_CFG_DSMSEL (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 28))
2728 +#define CGU_PLL0_CFG_FRAC_EN (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 27))
2729 +#define CGU_PLL1_SRC (lq_r32(LQ_CGU_PLL1_CFG) & (1 << 31))
2730 +#define CGU_PLL2_PHASE_DIVIDER_ENABLE (lq_r32(LQ_CGU_PLL2_CFG) & (1 << 20))
2731 +#define CGU_SYS_FPI_SEL (1 << 6)
2732 +#define CGU_SYS_DDR_SEL 0x3
2733 +#define CGU_PLL0_SRC (1 << 29)
2734 +
2735 +#define CGU_PLL0_CFG_PLLK GET_BITS(*LQ_CGU_PLL0_CFG, 26, 17)
2736 +#define CGU_PLL0_CFG_PLLN GET_BITS(*LQ_CGU_PLL0_CFG, 12, 6)
2737 +#define CGU_PLL0_CFG_PLLM GET_BITS(*LQ_CGU_PLL0_CFG, 5, 2)
2738 +#define CGU_PLL2_SRC GET_BITS(*LQ_CGU_PLL2_CFG, 18, 17)
2739 +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*LQ_CGU_PLL2_CFG, 16, 13)
2740 +
2741 +#define LQ_GPTU_GPT_CLC ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
2742 +#define LQ_CGU_PLL0_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x0004))
2743 +#define LQ_CGU_PLL1_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x0008))
2744 +#define LQ_CGU_PLL2_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x000C))
2745 +#define LQ_CGU_SYS ((u32 *)(LQ_CGU_BASE_ADDR + 0x0010))
2746 +#define LQ_CGU_UPDATE ((u32 *)(LQ_CGU_BASE_ADDR + 0x0014))
2747 +#define LQ_CGU_IF_CLK ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
2748 +#define LQ_CGU_OSC_CON ((u32 *)(LQ_CGU_BASE_ADDR + 0x001C))
2749 +#define LQ_CGU_SMD ((u32 *)(LQ_CGU_BASE_ADDR + 0x0020))
2750 +#define LQ_CGU_CT1SR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0028))
2751 +#define LQ_CGU_CT2SR ((u32 *)(LQ_CGU_BASE_ADDR + 0x002C))
2752 +#define LQ_CGU_PCMCR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0030))
2753 +#define LQ_CGU_PCI_CR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
2754 +#define LQ_CGU_PD_PC ((u32 *)(LQ_CGU_BASE_ADDR + 0x0038))
2755 +#define LQ_CGU_FMR ((u32 *)(LQ_CGU_BASE_ADDR + 0x003C))
2756 +
2757 +static unsigned int lq_get_pll0_fdiv(void);
2758 +
2759 +static inline unsigned int
2760 +get_input_clock(int pll)
2761 +{
2762 + switch (pll) {
2763 + case 0:
2764 + if (lq_r32(LQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
2765 + return BASIS_REQUENCY_USB;
2766 + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2767 + return BASIC_FREQUENCY_1;
2768 + else
2769 + return BASIC_FREQUENCY_2;
2770 + case 1:
2771 + if (CGU_PLL1_SRC)
2772 + return BASIS_REQUENCY_USB;
2773 + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2774 + return BASIC_FREQUENCY_1;
2775 + else
2776 + return BASIC_FREQUENCY_2;
2777 + case 2:
2778 + switch (CGU_PLL2_SRC) {
2779 + case 0:
2780 + return lq_get_pll0_fdiv();
2781 + case 1:
2782 + return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
2783 + BASIC_FREQUENCY_1 :
2784 + BASIC_FREQUENCY_2;
2785 + case 2:
2786 + return BASIS_REQUENCY_USB;
2787 + }
2788 + default:
2789 + return 0;
2790 + }
2791 +}
2792 +
2793 +static inline unsigned int
2794 +cal_dsm(int pll, unsigned int num, unsigned int den)
2795 +{
2796 + u64 res, clock = get_input_clock(pll);
2797 + res = num * clock;
2798 + do_div(res, den);
2799 + return res;
2800 +}
2801 +
2802 +static inline unsigned int
2803 +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
2804 +{
2805 + unsigned int num = ((N + 1) << 10) + K;
2806 + unsigned int den = (M + 1) << 10;
2807 + return cal_dsm(pll, num, den);
2808 +}
2809 +
2810 +static inline unsigned int
2811 +ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
2812 +{
2813 + unsigned int num = ((N + 1) << 11) + K + 512;
2814 + unsigned int den = (M + 1) << 11;
2815 + return cal_dsm(pll, num, den);
2816 +}
2817 +
2818 +static inline unsigned int
2819 +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
2820 +{
2821 + unsigned int num = K >= 512 ?
2822 + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
2823 + unsigned int den = (M + 1) << 12;
2824 + return cal_dsm(pll, num, den);
2825 +}
2826 +
2827 +static inline unsigned int
2828 +dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
2829 + unsigned int dsmsel, unsigned int phase_div_en)
2830 +{
2831 + if (!dsmsel)
2832 + return mash_dsm(pll, M, N, K);
2833 + else if (!phase_div_en)
2834 + return mash_dsm(pll, M, N, K);
2835 + else
2836 + return ssff_dsm_2(pll, M, N, K);
2837 +}
2838 +
2839 +static inline unsigned int
2840 +lq_get_pll0_fosc(void)
2841 +{
2842 + if (CGU_PLL0_BYPASS)
2843 + return get_input_clock(0);
2844 + else
2845 + return !CGU_PLL0_CFG_FRAC_EN
2846 + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
2847 + CGU_PLL0_PHASE_DIVIDER_ENABLE)
2848 + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
2849 + CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
2850 +}
2851 +
2852 +static unsigned int
2853 +lq_get_pll0_fdiv(void)
2854 +{
2855 + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
2856 + return (lq_get_pll0_fosc() + (div >> 1)) / div;
2857 +}
2858 +
2859 +unsigned int
2860 +lq_get_io_region_clock(void)
2861 +{
2862 + unsigned int ret = lq_get_pll0_fosc();
2863 + switch (lq_r32(LQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
2864 + default:
2865 + case 0:
2866 + return (ret + 1) / 2;
2867 + case 1:
2868 + return (ret * 2 + 2) / 5;
2869 + case 2:
2870 + return (ret + 1) / 3;
2871 + case 3:
2872 + return (ret + 2) / 4;
2873 + }
2874 +}
2875 +EXPORT_SYMBOL(lq_get_io_region_clock);
2876 +
2877 +unsigned int
2878 +lq_get_fpi_bus_clock(int fpi)
2879 +{
2880 + unsigned int ret = lq_get_io_region_clock();
2881 + if ((fpi == 2) && (lq_r32(LQ_CGU_SYS) & CGU_SYS_FPI_SEL))
2882 + ret >>= 1;
2883 + return ret;
2884 +}
2885 +EXPORT_SYMBOL(lq_get_fpi_bus_clock);
2886 +
2887 +unsigned int
2888 +lq_get_cpu_hz(void)
2889 +{
2890 + switch (lq_r32(LQ_CGU_SYS) & 0xc)
2891 + {
2892 + case 0:
2893 + return CLOCK_333M;
2894 + case 4:
2895 + return DDR_HZ;
2896 + case 8:
2897 + return DDR_HZ << 1;
2898 + default:
2899 + return DDR_HZ >> 1;
2900 + }
2901 +}
2902 +EXPORT_SYMBOL(lq_get_cpu_hz);
2903 +
2904 +unsigned int
2905 +lq_get_fpi_hz(void)
2906 +{
2907 + unsigned int ddr_clock = DDR_HZ;
2908 + if (lq_r32(LQ_CGU_SYS) & 0x40)
2909 + return ddr_clock >> 1;
2910 + return ddr_clock;
2911 +}
2912 +EXPORT_SYMBOL(lq_get_fpi_hz);
2913 +
2914 +
2915 --- /dev/null
2916 +++ b/arch/mips/lantiq/xway/gpio.c
2917 @@ -0,0 +1,206 @@
2918 +/*
2919 + * This program is free software; you can redistribute it and/or modify it
2920 + * under the terms of the GNU General Public License version 2 as published
2921 + * by the Free Software Foundation.
2922 + *
2923 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2924 + */
2925 +
2926 +#include <linux/slab.h>
2927 +#include <linux/module.h>
2928 +#include <linux/platform_device.h>
2929 +#include <linux/gpio.h>
2930 +
2931 +#include <lantiq.h>
2932 +
2933 +#define LQ_GPIO0_BASE_ADDR 0x1E100B10
2934 +#define LQ_GPIO1_BASE_ADDR 0x1E100B40
2935 +#define LQ_GPIO_SIZE 0x30
2936 +
2937 +#define LQ_GPIO_OUT 0x00
2938 +#define LQ_GPIO_IN 0x04
2939 +#define LQ_GPIO_DIR 0x08
2940 +#define LQ_GPIO_ALTSEL0 0x0C
2941 +#define LQ_GPIO_ALTSEL1 0x10
2942 +#define LQ_GPIO_OD 0x14
2943 +
2944 +#define PINS_PER_PORT 16
2945 +
2946 +#define lq_gpio_getbit(m, r, p) !!(lq_r32(m + r) & (1 << p))
2947 +#define lq_gpio_setbit(m, r, p) lq_w32_mask(0, (1 << p), m + r)
2948 +#define lq_gpio_clearbit(m, r, p) lq_w32_mask((1 << p), 0, m + r)
2949 +
2950 +struct lq_gpio
2951 +{
2952 + void __iomem *membase;
2953 + struct gpio_chip chip;
2954 +};
2955 +
2956 +int
2957 +gpio_to_irq(unsigned int gpio)
2958 +{
2959 + return -EINVAL;
2960 +}
2961 +EXPORT_SYMBOL(gpio_to_irq);
2962 +
2963 +int
2964 +lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val)
2965 +{
2966 + void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2967 + if(pin >= (2 * PINS_PER_PORT))
2968 + return -EINVAL;
2969 + if(pin >= PINS_PER_PORT)
2970 + {
2971 + pin -= PINS_PER_PORT;
2972 + membase += LQ_GPIO_SIZE;
2973 + }
2974 + if(val)
2975 + lq_w32_mask(0, (1 << pin), membase + reg);
2976 + else
2977 + lq_w32_mask((1 << pin), 0, membase + reg);
2978 + return 0;
2979 +}
2980 +EXPORT_SYMBOL(lq_gpio_setconfig);
2981 +
2982 +int
2983 +lq_gpio_request(unsigned int pin, unsigned int alt0,
2984 + unsigned int alt1, unsigned int dir, const char *name)
2985 +{
2986 + void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2987 + if(pin >= (2 * PINS_PER_PORT))
2988 + return -EINVAL;
2989 + if(gpio_request(pin, name))
2990 + {
2991 + printk("failed to register %s gpio\n", name);
2992 + return -EBUSY;
2993 + }
2994 + if(dir)
2995 + gpio_direction_output(pin, 1);
2996 + else
2997 + gpio_direction_input(pin);
2998 + if(pin >= PINS_PER_PORT)
2999 + {
3000 + pin -= PINS_PER_PORT;
3001 + membase += LQ_GPIO_SIZE;
3002 + }
3003 + if(alt0)
3004 + lq_gpio_setbit(membase, LQ_GPIO_ALTSEL0, pin);
3005 + else
3006 + lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL0, pin);
3007 + if(alt1)
3008 + lq_gpio_setbit(membase, LQ_GPIO_ALTSEL1, pin);
3009 + else
3010 + lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL1, pin);
3011 + return 0;
3012 +}
3013 +EXPORT_SYMBOL(lq_gpio_request);
3014 +
3015 +static void
3016 +lq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
3017 +{
3018 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3019 + if(value)
3020 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
3021 + else
3022 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
3023 +}
3024 +
3025 +static int
3026 +lq_gpio_get(struct gpio_chip *chip, unsigned int offset)
3027 +{
3028 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3029 + return lq_gpio_getbit(lq_gpio->membase, LQ_GPIO_IN, offset);
3030 +}
3031 +
3032 +static int
3033 +lq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
3034 +{
3035 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3036 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3037 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3038 + return 0;
3039 +}
3040 +
3041 +static int
3042 +lq_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
3043 +{
3044 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3045 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3046 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3047 + lq_gpio_set(chip, offset, value);
3048 + return 0;
3049 +}
3050 +
3051 +static int
3052 +lq_gpio_req(struct gpio_chip *chip, unsigned offset)
3053 +{
3054 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3055 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL0, offset);
3056 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL1, offset);
3057 + return 0;
3058 +}
3059 +
3060 +static int
3061 +lq_gpio_probe(struct platform_device *pdev)
3062 +{
3063 + struct lq_gpio *lq_gpio = kzalloc(sizeof(struct lq_gpio), GFP_KERNEL);
3064 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3065 + int ret = 0;
3066 + if(!res)
3067 + {
3068 + ret = -ENOENT;
3069 + goto err_free;
3070 + }
3071 + res = request_mem_region(res->start, resource_size(res),
3072 + dev_name(&pdev->dev));
3073 + if(!res)
3074 + {
3075 + ret = -EBUSY;
3076 + goto err_free;
3077 + }
3078 + lq_gpio->membase = ioremap_nocache(res->start, resource_size(res));
3079 + if(!lq_gpio->membase)
3080 + {
3081 + ret = -ENOMEM;
3082 + goto err_release_mem_region;
3083 + }
3084 + lq_gpio->chip.label = "lq_gpio";
3085 + lq_gpio->chip.direction_input = lq_gpio_direction_input;
3086 + lq_gpio->chip.direction_output = lq_gpio_direction_output;
3087 + lq_gpio->chip.get = lq_gpio_get;
3088 + lq_gpio->chip.set = lq_gpio_set;
3089 + lq_gpio->chip.request = lq_gpio_req;
3090 + lq_gpio->chip.base = PINS_PER_PORT * pdev->id;
3091 + lq_gpio->chip.ngpio = PINS_PER_PORT;
3092 + platform_set_drvdata(pdev, lq_gpio);
3093 + ret = gpiochip_add(&lq_gpio->chip);
3094 + if(!ret)
3095 + return 0;
3096 +
3097 + iounmap(lq_gpio->membase);
3098 +err_release_mem_region:
3099 + release_mem_region(res->start, resource_size(res));
3100 +err_free:
3101 + kfree(lq_gpio);
3102 + return ret;
3103 +}
3104 +
3105 +static struct platform_driver
3106 +lq_gpio_driver = {
3107 + .probe = lq_gpio_probe,
3108 + .driver = {
3109 + .name = "lq_gpio",
3110 + .owner = THIS_MODULE,
3111 + },
3112 +};
3113 +
3114 +int __init
3115 +lq_gpio_init(void)
3116 +{
3117 + int ret = platform_driver_register(&lq_gpio_driver);
3118 + if(ret)
3119 + printk(KERN_INFO "lq_gpio : Error registering platfom driver!");
3120 + return ret;
3121 +}
3122 +
3123 +postcore_initcall(lq_gpio_init);
3124 --- /dev/null
3125 +++ b/arch/mips/lantiq/xway/reset.c
3126 @@ -0,0 +1,53 @@
3127 +/*
3128 + * This program is free software; you can redistribute it and/or modify it
3129 + * under the terms of the GNU General Public License version 2 as published
3130 + * by the Free Software Foundation.
3131 + *
3132 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
3133 + */
3134 +
3135 +#include <linux/init.h>
3136 +#include <linux/io.h>
3137 +#include <linux/pm.h>
3138 +#include <asm/reboot.h>
3139 +
3140 +#include <xway.h>
3141 +
3142 +#define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
3143 +#define LQ_RCU_RST_ALL 0x40000000
3144 +
3145 +static void
3146 +lq_machine_restart(char *command)
3147 +{
3148 + printk(KERN_NOTICE "System restart\n");
3149 + local_irq_disable();
3150 + lq_w32(lq_r32(LQ_RCU_RST) | LQ_RCU_RST_ALL, LQ_RCU_RST);
3151 + for(;;);
3152 +}
3153 +
3154 +static void
3155 +lq_machine_halt(void)
3156 +{
3157 + printk(KERN_NOTICE "System halted.\n");
3158 + local_irq_disable();
3159 + for(;;);
3160 +}
3161 +
3162 +static void
3163 +lq_machine_power_off(void)
3164 +{
3165 + printk(KERN_NOTICE "Please turn off the power now.\n");
3166 + local_irq_disable();
3167 + for(;;);
3168 +}
3169 +
3170 +static int __init
3171 +mips_reboot_setup(void)
3172 +{
3173 + _machine_restart = lq_machine_restart;
3174 + _machine_halt = lq_machine_halt;
3175 + pm_power_off = lq_machine_power_off;
3176 + return 0;
3177 +}
3178 +
3179 +arch_initcall(mips_reboot_setup);
Personal OpenWRT clone
This page took 0.24085 seconds and 5 git commands to generate.