target/linux/ar71xx/files/drivers/spi/rb4xx_spi.c

   1 /*
   2  * SPI controller driver for the Mikrotik RB4xx boards
   3  *
   4  * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This file was based on the patches for Linux 2.6.27.39 published by
   7  * MikroTik for their RouterBoard 4xx series devices.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/workqueue.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/spi/spi.h>
  22
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24
  25 #define DRV_NAME        "rb4xx-spi"
  26 #define DRV_DESC        "Mikrotik RB4xx SPI controller driver"
  27 #define DRV_VERSION     "0.1.0"
  28
  29 #define SPI_CTRL_FASTEST        0x40
  30 #define SPI_FLASH_HZ            33333334
  31 #define SPI_CPLD_HZ             33333334
  32
  33 #define CPLD_CMD_READ_FAST      0x0b
  34
  35 #undef RB4XX_SPI_DEBUG
  36
  37 struct rb4xx_spi {
  38         void __iomem            *base;
  39         struct spi_master       *master;
  40
  41         unsigned                spi_ctrl_flash;
  42         unsigned                spi_ctrl_fread;
  43
  44         spinlock_t              lock;
  45         struct list_head        queue;
  46         int                     busy:1;
  47         int                     cs_wait;
  48 };
  49
  50 static unsigned spi_clk_low = SPI_IOC_CS1;
  51
  52 #ifdef RB4XX_SPI_DEBUG
  53 static inline void do_spi_delay(void)
  54 {
  55         ndelay(20000);
  56 }
  57 #else
  58 static inline void do_spi_delay(void) { }
  59 #endif
  60
  61 static inline void do_spi_init(struct spi_device *spi)
  62 {
  63         unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1;
  64
  65         if (!(spi->mode & SPI_CS_HIGH))
  66                 cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0;
  67
  68         spi_clk_low = cs;
  69 }
  70
  71 static inline void do_spi_finish(void __iomem *base)
  72 {
  73         do_spi_delay();
  74         __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC);
  75 }
  76
  77 static inline void do_spi_clk(void __iomem *base, int bit)
  78 {
  79         unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0);
  80
  81         do_spi_delay();
  82         __raw_writel(bval, base + SPI_REG_IOC);
  83         do_spi_delay();
  84         __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
  85 }
  86
  87 static void do_spi_byte(void __iomem *base, unsigned char byte)
  88 {
  89         do_spi_clk(base, byte >> 7);
  90         do_spi_clk(base, byte >> 6);
  91         do_spi_clk(base, byte >> 5);
  92         do_spi_clk(base, byte >> 4);
  93         do_spi_clk(base, byte >> 3);
  94         do_spi_clk(base, byte >> 2);
  95         do_spi_clk(base, byte >> 1);
  96         do_spi_clk(base, byte);
  97
  98         pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
  99                (unsigned)byte,
 100                (unsigned char)__raw_readl(base + SPI_REG_RDS));
 101 }
 102
 103 static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
 104                                    unsigned bit2)
 105 {
 106         unsigned bval = (spi_clk_low |
 107                          ((bit1 & 1) ? SPI_IOC_DO : 0) |
 108                          ((bit2 & 1) ? SPI_IOC_CS2 : 0));
 109         do_spi_delay();
 110         __raw_writel(bval, base + SPI_REG_IOC);
 111         do_spi_delay();
 112         __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
 113 }
 114
 115 static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
 116 {
 117         do_spi_clk_fast(base, byte >> 7, byte >> 6);
 118         do_spi_clk_fast(base, byte >> 5, byte >> 4);
 119         do_spi_clk_fast(base, byte >> 3, byte >> 2);
 120         do_spi_clk_fast(base, byte >> 1, byte >> 0);
 121
 122         pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
 123                (unsigned)byte,
 124                (unsigned char) __raw_readl(base + SPI_REG_RDS));
 125 }
 126
 127 static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
 128 {
 129         const unsigned char *rxv_ptr = NULL;
 130         const unsigned char *tx_ptr = t->tx_buf;
 131         unsigned char *rx_ptr = t->rx_buf;
 132         unsigned i;
 133
 134         pr_debug("spi_txrx len %u tx %u rx %u\n",
 135                t->len,
 136                (t->tx_buf ? 1 : 0),
 137                (t->rx_buf ? 1 : 0));
 138
 139         if (t->verify) {
 140                 rxv_ptr = tx_ptr;
 141                 tx_ptr = NULL;
 142         }
 143
 144         for (i = 0; i < t->len; ++i) {
 145                 unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
 146
 147                 if (t->fast_write)
 148                         do_spi_byte_fast(base, sdata);
 149                 else
 150                         do_spi_byte(base, sdata);
 151
 152                 if (rx_ptr) {
 153                         rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff;
 154                 } else if (rxv_ptr) {
 155                         unsigned char c = __raw_readl(base + SPI_REG_RDS);
 156                         if (rxv_ptr[i] != c)
 157                                 return i;
 158                 }
 159         }
 160
 161         return i;
 162 }
 163
 164 static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
 165                                struct spi_message *m)
 166 {
 167         struct spi_transfer *t;
 168         const unsigned char *tx_ptr;
 169         unsigned addr;
 170         void __iomem *base = rbspi->base;
 171
 172         /* check for exactly two transfers */
 173         if (list_empty(&m->transfers) ||
 174             list_is_last(m->transfers.next, &m->transfers) ||
 175             !list_is_last(m->transfers.next->next, &m->transfers)) {
 176                 return -1;
 177         }
 178
 179         /* first transfer contains command and address  */
 180         t = list_entry(m->transfers.next,
 181                        struct spi_transfer, transfer_list);
 182
 183         if (t->len != 5 || t->tx_buf == NULL)
 184                 return -1;
 185
 186         tx_ptr = t->tx_buf;
 187         if (tx_ptr[0] != CPLD_CMD_READ_FAST)
 188                 return -1;
 189
 190         addr = tx_ptr[1];
 191         addr = tx_ptr[2] | (addr << 8);
 192         addr = tx_ptr[3] | (addr << 8);
 193         addr += (unsigned) base;
 194
 195         m->actual_length += t->len;
 196
 197         /* second transfer contains data itself */
 198         t = list_entry(m->transfers.next->next,
 199                        struct spi_transfer, transfer_list);
 200
 201         if (t->tx_buf && !t->verify)
 202                 return -1;
 203
 204         __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
 205         __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL);
 206         __raw_writel(0, base + SPI_REG_FS);
 207
 208         if (t->rx_buf) {
 209                 memcpy(t->rx_buf, (const void *)addr, t->len);
 210         } else if (t->tx_buf) {
 211                 unsigned char buf[t->len];
 212                 memcpy(buf, (const void *)addr, t->len);
 213                 if (memcmp(t->tx_buf, buf, t->len) != 0)
 214                         m->status = -EMSGSIZE;
 215         }
 216         m->actual_length += t->len;
 217
 218         if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
 219                 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
 220                 __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
 221                 __raw_writel(0, base + SPI_REG_FS);
 222         }
 223
 224         return 0;
 225 }
 226
 227 static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
 228 {
 229         struct spi_transfer *t = NULL;
 230         void __iomem *base = rbspi->base;
 231
 232         m->status = 0;
 233         if (list_empty(&m->transfers))
 234                 return -1;
 235
 236         if (m->fast_read)
 237                 if (rb4xx_spi_read_fast(rbspi, m) == 0)
 238                         return -1;
 239
 240         __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
 241         __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL);
 242         do_spi_init(m->spi);
 243
 244         list_for_each_entry(t, &m->transfers, transfer_list) {
 245                 int len;
 246
 247                 len = rb4xx_spi_txrx(base, t);
 248                 if (len != t->len) {
 249                         m->status = -EMSGSIZE;
 250                         break;
 251                 }
 252                 m->actual_length += len;
 253
 254                 if (t->cs_change) {
 255                         if (list_is_last(&t->transfer_list, &m->transfers)) {
 256                                 /* wait for continuation */
 257                                 return m->spi->chip_select;
 258                         }
 259                         do_spi_finish(base);
 260                         ndelay(100);
 261                 }
 262         }
 263
 264         do_spi_finish(base);
 265         __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
 266         __raw_writel(0, base + SPI_REG_FS);
 267         return -1;
 268 }
 269
 270 static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
 271                                            unsigned long *flags)
 272 {
 273         int cs = rbspi->cs_wait;
 274
 275         rbspi->busy = 1;
 276         while (!list_empty(&rbspi->queue)) {
 277                 struct spi_message *m;
 278
 279                 list_for_each_entry(m, &rbspi->queue, queue)
 280                         if (cs < 0 || cs == m->spi->chip_select)
 281                                 break;
 282
 283                 if (&m->queue == &rbspi->queue)
 284                         break;
 285
 286                 list_del_init(&m->queue);
 287                 spin_unlock_irqrestore(&rbspi->lock, *flags);
 288
 289                 cs = rb4xx_spi_msg(rbspi, m);
 290                 m->complete(m->context);
 291
 292                 spin_lock_irqsave(&rbspi->lock, *flags);
 293         }
 294
 295         rbspi->cs_wait = cs;
 296         rbspi->busy = 0;
 297
 298         if (cs >= 0) {
 299                 /* TODO: add timer to unlock cs after 1s inactivity */
 300         }
 301 }
 302
 303 static int rb4xx_spi_transfer(struct spi_device *spi,
 304                               struct spi_message *m)
 305 {
 306         struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
 307         unsigned long flags;
 308
 309         m->actual_length = 0;
 310         m->status = -EINPROGRESS;
 311
 312         spin_lock_irqsave(&rbspi->lock, flags);
 313         list_add_tail(&m->queue, &rbspi->queue);
 314         if (rbspi->busy ||
 315             (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
 316                 /* job will be done later */
 317                 spin_unlock_irqrestore(&rbspi->lock, flags);
 318                 return 0;
 319         }
 320
 321         /* process job in current context */
 322         rb4xx_spi_process_queue_locked(rbspi, &flags);
 323         spin_unlock_irqrestore(&rbspi->lock, flags);
 324
 325         return 0;
 326 }
 327
 328 static int rb4xx_spi_setup(struct spi_device *spi)
 329 {
 330         struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
 331         unsigned long flags;
 332
 333         if (spi->mode & ~(SPI_CS_HIGH)) {
 334                 dev_err(&spi->dev, "mode %x not supported\n",
 335                         (unsigned) spi->mode);
 336                 return -EINVAL;
 337         }
 338
 339         if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
 340                 dev_err(&spi->dev, "bits_per_word %u not supported\n",
 341                         (unsigned) spi->bits_per_word);
 342                 return -EINVAL;
 343         }
 344
 345         spin_lock_irqsave(&rbspi->lock, flags);
 346         if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
 347                 rbspi->cs_wait = -1;
 348                 rb4xx_spi_process_queue_locked(rbspi, &flags);
 349         }
 350         spin_unlock_irqrestore(&rbspi->lock, flags);
 351
 352         return 0;
 353 }
 354
 355 static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
 356 {
 357         unsigned div;
 358
 359         div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
 360
 361         /*
 362          * CPU has a bug at (div == 0) - first bit read is random
 363          */
 364         if (div == 0)
 365                 ++div;
 366
 367         if (name) {
 368                 unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
 369                 unsigned div_real = 2 * (div + 1);
 370                 pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
 371                        name,
 372                        ahb_khz / div_real,
 373                        ahb_khz, div_real);
 374         }
 375
 376         return SPI_CTRL_FASTEST + div;
 377 }
 378
 379 static int rb4xx_spi_probe(struct platform_device *pdev)
 380 {
 381         struct spi_master *master;
 382         struct rb4xx_spi *rbspi;
 383         struct resource *r;
 384         int err = 0;
 385
 386         master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
 387         if (master == NULL) {
 388                 dev_err(&pdev->dev, "no memory for spi_master\n");
 389                 err = -ENOMEM;
 390                 goto err_out;
 391         }
 392
 393         master->bus_num = 0;
 394         master->num_chipselect = 3;
 395         master->setup = rb4xx_spi_setup;
 396         master->transfer = rb4xx_spi_transfer;
 397
 398         rbspi = spi_master_get_devdata(master);
 399         platform_set_drvdata(pdev, rbspi);
 400
 401         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 402         if (r == NULL) {
 403                 err = -ENOENT;
 404                 goto err_put_master;
 405         }
 406
 407         rbspi->base = ioremap(r->start, r->end - r->start + 1);
 408         if (!rbspi->base) {
 409                 err = -ENXIO;
 410                 goto err_put_master;
 411         }
 412
 413         rbspi->master = master;
 414         rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH");
 415         rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD");
 416         rbspi->cs_wait = -1;
 417
 418         spin_lock_init(&rbspi->lock);
 419         INIT_LIST_HEAD(&rbspi->queue);
 420
 421         err = spi_register_master(master);
 422         if (err) {
 423                 dev_err(&pdev->dev, "failed to register SPI master\n");
 424                 goto err_iounmap;
 425         }
 426
 427         return 0;
 428
 429 err_iounmap:
 430         iounmap(rbspi->base);
 431 err_put_master:
 432         platform_set_drvdata(pdev, NULL);
 433         spi_master_put(master);
 434 err_out:
 435         return err;
 436 }
 437
 438 static int rb4xx_spi_remove(struct platform_device *pdev)
 439 {
 440         struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
 441
 442         iounmap(rbspi->base);
 443         platform_set_drvdata(pdev, NULL);
 444         spi_master_put(rbspi->master);
 445
 446         return 0;
 447 }
 448
 449 static struct platform_driver rb4xx_spi_drv = {
 450         .probe          = rb4xx_spi_probe,
 451         .remove         = rb4xx_spi_remove,
 452         .driver         = {
 453                 .name   = DRV_NAME,
 454                 .owner  = THIS_MODULE,
 455         },
 456 };
 457
 458 static int __init rb4xx_spi_init(void)
 459 {
 460         return platform_driver_register(&rb4xx_spi_drv);
 461 }
 462 subsys_initcall(rb4xx_spi_init);
 463
 464 static void __exit rb4xx_spi_exit(void)
 465 {
 466         platform_driver_unregister(&rb4xx_spi_drv);
 467 }
 468
 469 module_exit(rb4xx_spi_exit);
 470
 471 MODULE_DESCRIPTION(DRV_DESC);
 472 MODULE_VERSION(DRV_VERSION);
 473 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 474 MODULE_LICENSE("GPL v2");