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ar71xx: allow to attach the internal switch for AR934x
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
62
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
68
69 #define AR7240_REG_TAG_PRIORITY 0x70
70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
73
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
77
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
86
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
95
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
97
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_S 0
100 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
101 #define AR7240_PORT_STATUS_SPEED_10 0
102 #define AR7240_PORT_STATUS_SPEED_100 1
103 #define AR7240_PORT_STATUS_SPEED_1000 2
104 #define AR7240_PORT_STATUS_TXMAC BIT(2)
105 #define AR7240_PORT_STATUS_RXMAC BIT(3)
106 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
107 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
108 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
109 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
110 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
111 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
112
113 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
114 #define AR7240_PORT_CTRL_STATE_M BITM(3)
115 #define AR7240_PORT_CTRL_STATE_DISABLED 0
116 #define AR7240_PORT_CTRL_STATE_BLOCK 1
117 #define AR7240_PORT_CTRL_STATE_LISTEN 2
118 #define AR7240_PORT_CTRL_STATE_LEARN 3
119 #define AR7240_PORT_CTRL_STATE_FORWARD 4
120 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
121 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
122 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
123 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
124 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
125 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
126 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
127 #define AR7240_PORT_CTRL_HEADER BIT(11)
128 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
129 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
130 #define AR7240_PORT_CTRL_LEARN BIT(14)
131 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
132 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
133 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
134
135 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
136
137 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
138 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
139 #define AR7240_PORT_VLAN_MODE_S 30
140 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
141 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
142 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
143 #define AR7240_PORT_VLAN_MODE_SECURE 3
144
145
146 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
147
148 #define AR7240_STATS_RXBROAD 0x00
149 #define AR7240_STATS_RXPAUSE 0x04
150 #define AR7240_STATS_RXMULTI 0x08
151 #define AR7240_STATS_RXFCSERR 0x0c
152 #define AR7240_STATS_RXALIGNERR 0x10
153 #define AR7240_STATS_RXRUNT 0x14
154 #define AR7240_STATS_RXFRAGMENT 0x18
155 #define AR7240_STATS_RX64BYTE 0x1c
156 #define AR7240_STATS_RX128BYTE 0x20
157 #define AR7240_STATS_RX256BYTE 0x24
158 #define AR7240_STATS_RX512BYTE 0x28
159 #define AR7240_STATS_RX1024BYTE 0x2c
160 #define AR7240_STATS_RX1518BYTE 0x30
161 #define AR7240_STATS_RXMAXBYTE 0x34
162 #define AR7240_STATS_RXTOOLONG 0x38
163 #define AR7240_STATS_RXGOODBYTE 0x3c
164 #define AR7240_STATS_RXBADBYTE 0x44
165 #define AR7240_STATS_RXOVERFLOW 0x4c
166 #define AR7240_STATS_FILTERED 0x50
167 #define AR7240_STATS_TXBROAD 0x54
168 #define AR7240_STATS_TXPAUSE 0x58
169 #define AR7240_STATS_TXMULTI 0x5c
170 #define AR7240_STATS_TXUNDERRUN 0x60
171 #define AR7240_STATS_TX64BYTE 0x64
172 #define AR7240_STATS_TX128BYTE 0x68
173 #define AR7240_STATS_TX256BYTE 0x6c
174 #define AR7240_STATS_TX512BYTE 0x70
175 #define AR7240_STATS_TX1024BYTE 0x74
176 #define AR7240_STATS_TX1518BYTE 0x78
177 #define AR7240_STATS_TXMAXBYTE 0x7c
178 #define AR7240_STATS_TXOVERSIZE 0x80
179 #define AR7240_STATS_TXBYTE 0x84
180 #define AR7240_STATS_TXCOLLISION 0x8c
181 #define AR7240_STATS_TXABORTCOL 0x90
182 #define AR7240_STATS_TXMULTICOL 0x94
183 #define AR7240_STATS_TXSINGLECOL 0x98
184 #define AR7240_STATS_TXEXCDEFER 0x9c
185 #define AR7240_STATS_TXDEFER 0xa0
186 #define AR7240_STATS_TXLATECOL 0xa4
187
188 #define AR7240_PORT_CPU 0
189 #define AR7240_NUM_PORTS 6
190 #define AR7240_NUM_PHYS 5
191
192 #define AR7240_PHY_ID1 0x004d
193 #define AR7240_PHY_ID2 0xd041
194
195 #define AR7240_MAX_VLANS 16
196
197 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
198
199 struct ar7240sw {
200 struct mii_bus *mii_bus;
201 struct ag71xx_switch_platform_data *swdata;
202 struct switch_dev swdev;
203 int num_ports;
204 bool vlan;
205 u16 vlan_id[AR7240_MAX_VLANS];
206 u8 vlan_table[AR7240_MAX_VLANS];
207 u8 vlan_tagged;
208 u16 pvid[AR7240_NUM_PORTS];
209 char buf[80];
210 };
211
212 struct ar7240sw_hw_stat {
213 char string[ETH_GSTRING_LEN];
214 int sizeof_stat;
215 int reg;
216 };
217
218 static DEFINE_MUTEX(reg_mutex);
219
220 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
221 {
222 return BIT(port);
223 }
224
225 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
226 {
227 return BIT(as->swdev.ports) - 1;
228 }
229
230 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
231 {
232 return ar7240sw_port_mask_all(as) & ~BIT(port);
233 }
234
235 static inline u16 mk_phy_addr(u32 reg)
236 {
237 return 0x17 & ((reg >> 4) | 0x10);
238 }
239
240 static inline u16 mk_phy_reg(u32 reg)
241 {
242 return (reg << 1) & 0x1e;
243 }
244
245 static inline u16 mk_high_addr(u32 reg)
246 {
247 return (reg >> 7) & 0x1ff;
248 }
249
250 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
251 {
252 unsigned long flags;
253 u16 phy_addr;
254 u16 phy_reg;
255 u32 hi, lo;
256
257 reg = (reg & 0xfffffffc) >> 2;
258 phy_addr = mk_phy_addr(reg);
259 phy_reg = mk_phy_reg(reg);
260
261 local_irq_save(flags);
262 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
263 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
264 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
265 local_irq_restore(flags);
266
267 return (hi << 16) | lo;
268 }
269
270 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
271 {
272 unsigned long flags;
273 u16 phy_addr;
274 u16 phy_reg;
275
276 reg = (reg & 0xfffffffc) >> 2;
277 phy_addr = mk_phy_addr(reg);
278 phy_reg = mk_phy_reg(reg);
279
280 local_irq_save(flags);
281 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
282 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
283 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
284 local_irq_restore(flags);
285 }
286
287 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
288 {
289 u32 ret;
290
291 mutex_lock(&reg_mutex);
292 ret = __ar7240sw_reg_read(mii, reg_addr);
293 mutex_unlock(&reg_mutex);
294
295 return ret;
296 }
297
298 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
299 {
300 mutex_lock(&reg_mutex);
301 __ar7240sw_reg_write(mii, reg_addr, reg_val);
302 mutex_unlock(&reg_mutex);
303 }
304
305 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
306 {
307 u32 t;
308
309 mutex_lock(&reg_mutex);
310 t = __ar7240sw_reg_read(mii, reg);
311 t &= ~mask;
312 t |= val;
313 __ar7240sw_reg_write(mii, reg, t);
314 mutex_unlock(&reg_mutex);
315
316 return t;
317 }
318
319 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
320 {
321 u32 t;
322
323 mutex_lock(&reg_mutex);
324 t = __ar7240sw_reg_read(mii, reg);
325 t |= val;
326 __ar7240sw_reg_write(mii, reg, t);
327 mutex_unlock(&reg_mutex);
328 }
329
330 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
331 unsigned timeout)
332 {
333 int i;
334
335 for (i = 0; i < timeout; i++) {
336 u32 t;
337
338 t = __ar7240sw_reg_read(mii, reg);
339 if ((t & mask) == val)
340 return 0;
341
342 msleep(1);
343 }
344
345 return -ETIMEDOUT;
346 }
347
348 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
349 unsigned timeout)
350 {
351 int ret;
352
353 mutex_lock(&reg_mutex);
354 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
355 mutex_unlock(&reg_mutex);
356 return ret;
357 }
358
359 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
360 unsigned reg_addr)
361 {
362 u32 t, val = 0xffff;
363 int err;
364
365 if (phy_addr >= AR7240_NUM_PHYS)
366 return 0xffff;
367
368 mutex_lock(&reg_mutex);
369 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
370 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
371 AR7240_MDIO_CTRL_MASTER_EN |
372 AR7240_MDIO_CTRL_BUSY |
373 AR7240_MDIO_CTRL_CMD_READ;
374
375 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
376 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
377 AR7240_MDIO_CTRL_BUSY, 0, 5);
378 if (!err)
379 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
380 mutex_unlock(&reg_mutex);
381
382 return val & AR7240_MDIO_CTRL_DATA_M;
383 }
384
385 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
386 unsigned reg_addr, u16 reg_val)
387 {
388 u32 t;
389 int ret;
390
391 if (phy_addr >= AR7240_NUM_PHYS)
392 return -EINVAL;
393
394 mutex_lock(&reg_mutex);
395 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
396 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
397 AR7240_MDIO_CTRL_MASTER_EN |
398 AR7240_MDIO_CTRL_BUSY |
399 AR7240_MDIO_CTRL_CMD_WRITE |
400 reg_val;
401
402 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
403 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
404 AR7240_MDIO_CTRL_BUSY, 0, 5);
405 mutex_unlock(&reg_mutex);
406
407 return ret;
408 }
409
410 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
411 {
412 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
413 AR7240_PORT_CTRL_STATE_DISABLED);
414 }
415
416 static void ar7240sw_setup(struct ar7240sw *as)
417 {
418 struct mii_bus *mii = as->mii_bus;
419
420 /* Enable CPU port, and disable mirror port */
421 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
422 AR7240_CPU_PORT_EN |
423 (15 << AR7240_MIRROR_PORT_S));
424
425 /* Setup TAG priority mapping */
426 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
427
428 /* Enable ARP frame acknowledge, aging, MAC replacing */
429 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
430 0x2b /* 5 min age time */ |
431 AR7240_AT_CTRL_AGE_EN |
432 AR7240_AT_CTRL_ARP_EN |
433 AR7240_AT_CTRL_LEARN_CHANGE);
434
435 /* Enable Broadcast frames transmitted to the CPU */
436 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
437 AR7240_FLOOD_MASK_BROAD_TO_CPU);
438
439 /* setup MTU */
440 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
441 1536);
442
443 /* setup Service TAG */
444 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
445 }
446
447 static int ar7240sw_reset(struct ar7240sw *as)
448 {
449 struct mii_bus *mii = as->mii_bus;
450 int ret;
451 int i;
452
453 /* Set all ports to disabled state. */
454 for (i = 0; i < AR7240_NUM_PORTS; i++)
455 ar7240sw_disable_port(as, i);
456
457 /* Wait for transmit queues to drain. */
458 msleep(2);
459
460 /* Reset the switch. */
461 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
462 AR7240_MASK_CTRL_SOFT_RESET);
463
464 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
465 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
466
467 ar7240sw_setup(as);
468 return ret;
469 }
470
471 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
472 {
473 struct mii_bus *mii = as->mii_bus;
474 u32 ctrl;
475 u32 vlan;
476
477 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
478 AR7240_PORT_CTRL_SINGLE_VLAN;
479
480 if (port == AR7240_PORT_CPU) {
481 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
482 AR7240_PORT_STATUS_SPEED_1000 |
483 AR7240_PORT_STATUS_TXFLOW |
484 AR7240_PORT_STATUS_RXFLOW |
485 AR7240_PORT_STATUS_TXMAC |
486 AR7240_PORT_STATUS_RXMAC |
487 AR7240_PORT_STATUS_DUPLEX);
488 } else {
489 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
490 AR7240_PORT_STATUS_LINK_AUTO);
491 }
492
493 /* Set the default VID for this port */
494 if (as->vlan) {
495 vlan = as->vlan_id[as->pvid[port]];
496 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
497 AR7240_PORT_VLAN_MODE_S;
498 } else {
499 vlan = port;
500 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
501 AR7240_PORT_VLAN_MODE_S;
502 }
503
504 if (as->vlan && (as->vlan_tagged & BIT(port))) {
505 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
506 AR7240_PORT_CTRL_VLAN_MODE_S;
507 } else {
508 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
509 AR7240_PORT_CTRL_VLAN_MODE_S;
510 }
511
512 if (!portmask) {
513 if (port == AR7240_PORT_CPU)
514 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
515 else
516 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
517 }
518
519 /* allow the port to talk to all other ports, but exclude its
520 * own ID to prevent frames from being reflected back to the
521 * port that they came from */
522 portmask &= ar7240sw_port_mask_but(as, port);
523
524 /* set default VID and and destination ports for this VLAN */
525 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
526
527 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
528 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
529 }
530
531 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
532 {
533 struct mii_bus *mii = as->mii_bus;
534 u32 t;
535
536 t = (addr[4] << 8) | addr[5];
537 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
538
539 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
540 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
541
542 return 0;
543 }
544
545 static int
546 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
547 struct switch_val *val)
548 {
549 struct ar7240sw *as = sw_to_ar7240(dev);
550 as->vlan_id[val->port_vlan] = val->value.i;
551 return 0;
552 }
553
554 static int
555 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
556 struct switch_val *val)
557 {
558 struct ar7240sw *as = sw_to_ar7240(dev);
559 val->value.i = as->vlan_id[val->port_vlan];
560 return 0;
561 }
562
563 static int
564 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
565 {
566 struct ar7240sw *as = sw_to_ar7240(dev);
567
568 /* make sure no invalid PVIDs get set */
569
570 if (vlan >= dev->vlans)
571 return -EINVAL;
572
573 as->pvid[port] = vlan;
574 return 0;
575 }
576
577 static int
578 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
579 {
580 struct ar7240sw *as = sw_to_ar7240(dev);
581 *vlan = as->pvid[port];
582 return 0;
583 }
584
585 static int
586 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
587 {
588 struct ar7240sw *as = sw_to_ar7240(dev);
589 u8 ports = as->vlan_table[val->port_vlan];
590 int i;
591
592 val->len = 0;
593 for (i = 0; i < as->swdev.ports; i++) {
594 struct switch_port *p;
595
596 if (!(ports & (1 << i)))
597 continue;
598
599 p = &val->value.ports[val->len++];
600 p->id = i;
601 if (as->vlan_tagged & (1 << i))
602 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
603 else
604 p->flags = 0;
605 }
606 return 0;
607 }
608
609 static int
610 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
611 {
612 struct ar7240sw *as = sw_to_ar7240(dev);
613 u8 *vt = &as->vlan_table[val->port_vlan];
614 int i, j;
615
616 *vt = 0;
617 for (i = 0; i < val->len; i++) {
618 struct switch_port *p = &val->value.ports[i];
619
620 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
621 as->vlan_tagged |= (1 << p->id);
622 else {
623 as->vlan_tagged &= ~(1 << p->id);
624 as->pvid[p->id] = val->port_vlan;
625
626 /* make sure that an untagged port does not
627 * appear in other vlans */
628 for (j = 0; j < AR7240_MAX_VLANS; j++) {
629 if (j == val->port_vlan)
630 continue;
631 as->vlan_table[j] &= ~(1 << p->id);
632 }
633 }
634
635 *vt |= 1 << p->id;
636 }
637 return 0;
638 }
639
640 static int
641 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
642 struct switch_val *val)
643 {
644 struct ar7240sw *as = sw_to_ar7240(dev);
645 as->vlan = !!val->value.i;
646 return 0;
647 }
648
649 static int
650 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
651 struct switch_val *val)
652 {
653 struct ar7240sw *as = sw_to_ar7240(dev);
654 val->value.i = as->vlan;
655 return 0;
656 }
657
658 static const char *
659 ar7240_speed_str(u32 status)
660 {
661 u32 speed;
662
663 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
664 AR7240_PORT_STATUS_SPEED_M;
665 switch (speed) {
666 case AR7240_PORT_STATUS_SPEED_10:
667 return "10baseT";
668 case AR7240_PORT_STATUS_SPEED_100:
669 return "100baseT";
670 case AR7240_PORT_STATUS_SPEED_1000:
671 return "1000baseT";
672 }
673
674 return "unknown";
675 }
676
677 static int
678 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
679 struct switch_val *val)
680 {
681 struct ar7240sw *as = sw_to_ar7240(dev);
682 struct mii_bus *mii = as->mii_bus;
683 u32 len;
684 u32 status;
685 int port;
686
687 port = val->port_vlan;
688
689 memset(as->buf, '\0', sizeof(as->buf));
690 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
691
692 if (status & AR7240_PORT_STATUS_LINK_UP) {
693 len = snprintf(as->buf, sizeof(as->buf),
694 "port:%d link:up speed:%s %s-duplex %s%s%s",
695 port,
696 ar7240_speed_str(status),
697 (status & AR7240_PORT_STATUS_DUPLEX) ?
698 "full" : "half",
699 (status & AR7240_PORT_STATUS_TXFLOW) ?
700 "txflow ": "",
701 (status & AR7240_PORT_STATUS_RXFLOW) ?
702 "rxflow " : "",
703 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
704 "auto ": "");
705 } else {
706 len = snprintf(as->buf, sizeof(as->buf),
707 "port:%d link:down", port);
708 }
709
710 val->value.s = as->buf;
711 val->len = len;
712
713 return 0;
714 }
715
716 static void
717 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
718 {
719 struct mii_bus *mii = as->mii_bus;
720
721 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
722 return;
723
724 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
725 val &= AR7240_VTUDATA_MEMBER;
726 val |= AR7240_VTUDATA_VALID;
727 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
728 }
729 op |= AR7240_VTU_ACTIVE;
730 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
731 }
732
733 static int
734 ar7240_hw_apply(struct switch_dev *dev)
735 {
736 struct ar7240sw *as = sw_to_ar7240(dev);
737 u8 portmask[AR7240_NUM_PORTS];
738 int i, j;
739
740 /* flush all vlan translation unit entries */
741 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
742
743 memset(portmask, 0, sizeof(portmask));
744 if (as->vlan) {
745 /* calculate the port destination masks and load vlans
746 * into the vlan translation unit */
747 for (j = 0; j < AR7240_MAX_VLANS; j++) {
748 u8 vp = as->vlan_table[j];
749
750 if (!vp)
751 continue;
752
753 for (i = 0; i < as->swdev.ports; i++) {
754 u8 mask = (1 << i);
755 if (vp & mask)
756 portmask[i] |= vp & ~mask;
757 }
758
759 ar7240_vtu_op(as,
760 AR7240_VTU_OP_LOAD |
761 (as->vlan_id[j] << AR7240_VTU_VID_S),
762 as->vlan_table[j]);
763 }
764 } else {
765 /* vlan disabled:
766 * isolate all ports, but connect them to the cpu port */
767 for (i = 0; i < as->swdev.ports; i++) {
768 if (i == AR7240_PORT_CPU)
769 continue;
770
771 portmask[i] = 1 << AR7240_PORT_CPU;
772 portmask[AR7240_PORT_CPU] |= (1 << i);
773 }
774 }
775
776 /* update the port destination mask registers and tag settings */
777 for (i = 0; i < as->swdev.ports; i++)
778 ar7240sw_setup_port(as, i, portmask[i]);
779
780 return 0;
781 }
782
783 static int
784 ar7240_reset_switch(struct switch_dev *dev)
785 {
786 struct ar7240sw *as = sw_to_ar7240(dev);
787 ar7240sw_reset(as);
788 return 0;
789 }
790
791 static struct switch_attr ar7240_globals[] = {
792 {
793 .type = SWITCH_TYPE_INT,
794 .name = "enable_vlan",
795 .description = "Enable VLAN mode",
796 .set = ar7240_set_vlan,
797 .get = ar7240_get_vlan,
798 .max = 1
799 },
800 };
801
802 static struct switch_attr ar7240_port[] = {
803 {
804 .type = SWITCH_TYPE_STRING,
805 .name = "link",
806 .description = "Get port link information",
807 .max = 1,
808 .set = NULL,
809 .get = ar7240_port_get_link,
810 },
811 };
812
813 static struct switch_attr ar7240_vlan[] = {
814 {
815 .type = SWITCH_TYPE_INT,
816 .name = "vid",
817 .description = "VLAN ID",
818 .set = ar7240_set_vid,
819 .get = ar7240_get_vid,
820 .max = 4094,
821 },
822 };
823
824 static const struct switch_dev_ops ar7240_ops = {
825 .attr_global = {
826 .attr = ar7240_globals,
827 .n_attr = ARRAY_SIZE(ar7240_globals),
828 },
829 .attr_port = {
830 .attr = ar7240_port,
831 .n_attr = ARRAY_SIZE(ar7240_port),
832 },
833 .attr_vlan = {
834 .attr = ar7240_vlan,
835 .n_attr = ARRAY_SIZE(ar7240_vlan),
836 },
837 .get_port_pvid = ar7240_get_pvid,
838 .set_port_pvid = ar7240_set_pvid,
839 .get_vlan_ports = ar7240_get_ports,
840 .set_vlan_ports = ar7240_set_ports,
841 .apply_config = ar7240_hw_apply,
842 .reset_switch = ar7240_reset_switch,
843 };
844
845 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
846 {
847 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
848 struct mii_bus *mii = ag->mii_bus;
849 struct ar7240sw *as;
850 struct switch_dev *swdev;
851 u32 ctrl;
852 u16 phy_id1;
853 u16 phy_id2;
854 u8 ver;
855 int i;
856
857 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
858 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
859 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
860 pr_err("%s: unknown phy id '%04x:%04x'\n",
861 ag->dev->name, phy_id1, phy_id2);
862 return NULL;
863 }
864
865 as = kzalloc(sizeof(*as), GFP_KERNEL);
866 if (!as)
867 return NULL;
868
869 as->mii_bus = mii;
870 as->swdata = pdata->switch_data;
871
872 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
873 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
874 if (ver != 1) {
875 pr_err("%s: unsupported chip, ctrl=%08x\n",
876 ag->dev->name, ctrl);
877 return NULL;
878 }
879
880 swdev = &as->swdev;
881 swdev->name = "AR7240 built-in switch";
882 swdev->ports = AR7240_NUM_PORTS - 1;
883 swdev->cpu_port = AR7240_PORT_CPU;
884 swdev->vlans = AR7240_MAX_VLANS;
885 swdev->ops = &ar7240_ops;
886
887 if (register_switch(&as->swdev, ag->dev) < 0) {
888 kfree(as);
889 return NULL;
890 }
891
892 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
893
894 /* initialize defaults */
895 for (i = 0; i < AR7240_MAX_VLANS; i++)
896 as->vlan_id[i] = i;
897
898 as->vlan_table[0] = ar7240sw_port_mask_all(as);
899
900 return as;
901 }
902
903 static void link_function(struct work_struct *work) {
904 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
905 unsigned long flags;
906 int i;
907 int status = 0;
908
909 for (i = 0; i < 4; i++) {
910 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
911 if(link & BMSR_LSTATUS) {
912 status = 1;
913 break;
914 }
915 }
916
917 spin_lock_irqsave(&ag->lock, flags);
918 if(status != ag->link) {
919 ag->link = status;
920 ag71xx_link_adjust(ag);
921 }
922 spin_unlock_irqrestore(&ag->lock, flags);
923
924 schedule_delayed_work(&ag->link_work, HZ / 2);
925 }
926
927 void ag71xx_ar7240_start(struct ag71xx *ag)
928 {
929 struct ar7240sw *as = ag->phy_priv;
930
931 ar7240sw_reset(as);
932
933 ag->speed = SPEED_1000;
934 ag->duplex = 1;
935
936 ar7240_set_addr(as, ag->dev->dev_addr);
937 ar7240_hw_apply(&as->swdev);
938
939 schedule_delayed_work(&ag->link_work, HZ / 10);
940 }
941
942 void ag71xx_ar7240_stop(struct ag71xx *ag)
943 {
944 cancel_delayed_work_sync(&ag->link_work);
945 }
946
947 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
948 {
949 struct ar7240sw *as;
950
951 as = ar7240_probe(ag);
952 if (!as)
953 return -ENODEV;
954
955 ag->phy_priv = as;
956 ar7240sw_reset(as);
957
958 INIT_DELAYED_WORK(&ag->link_work, link_function);
959
960 return 0;
961 }
962
963 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
964 {
965 struct ar7240sw *as = ag->phy_priv;
966
967 if (!as)
968 return;
969
970 unregister_switch(&as->swdev);
971 kfree(as);
972 ag->phy_priv = NULL;
973 }
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