openwrt/target/linux/package/switch/src/switch-adm.c

   1 /*
   2  * ADMTEK Adm6996 switch configuration module
   3  *
   4  * Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19  * 02110-1301, USA.
  20  */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/init.h>
  25 #include <linux/if.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/sockios.h>
  28 #include <linux/delay.h>
  29 #include <asm/uaccess.h>
  30
  31 #include "switch-core.h"
  32 #include "gpio.h"
  33
  34 #define DRIVER_NAME "adm6996"
  35
  36 static int eecs = 2;
  37 static int eesk = 3;
  38 static int eedi = 5;
  39 static int eerc = 6;
  40 static int force = 0;
  41
  42 MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
  43 MODULE_LICENSE("GPL");
  44 MODULE_PARM(eecs, "i");
  45 MODULE_PARM(eesk, "i");
  46 MODULE_PARM(eedi, "i");
  47 MODULE_PARM(eerc, "i");
  48 MODULE_PARM(force, "i");
  49
  50 /* Minimum timing constants */
  51 #define EECK_EDGE_TIME  3   /* 3us - max(adm 2.5us, 93c 1us) */
  52 #define EEDI_SETUP_TIME 1   /* 1us - max(adm 10ns, 93c 400ns) */
  53 #define EECS_SETUP_TIME 1   /* 1us - max(adm no, 93c 200ns) */
  54
  55 /* Handy macros for writing fixed length values */
  56 #define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
  57 #define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
  58 #define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
  59
  60
  61 extern int getintvar(char **vars, char *name);
  62
  63
  64 static void adm_write(int cs, char *buf, unsigned int bits)
  65 {
  66         int i, len = (bits + 7) / 8;
  67         __u8 mask;
  68
  69         gpioout(eecs, (cs ? eecs : 0));
  70         udelay(EECK_EDGE_TIME);
  71
  72         /* Byte assemble from MSB to LSB */
  73         for (i = 0; i < len; i++) {
  74                 /* Bit bang from MSB to LSB */
  75                 for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
  76                         /* Clock low */
  77                         gpioout(eesk, 0);
  78                         udelay(EECK_EDGE_TIME);
  79
  80                         /* Output on rising edge */
  81                         gpioout(eedi, ((mask & buf[i]) ? eedi : 0));
  82                         udelay(EEDI_SETUP_TIME);
  83
  84                         /* Clock high */
  85                         gpioout(eesk, eesk);
  86                         udelay(EECK_EDGE_TIME);
  87                 }
  88         }
  89
  90         /* Clock low */
  91         gpioout(eesk, 0);
  92         udelay(EECK_EDGE_TIME);
  93
  94         if (cs)
  95                 gpioout(eecs, 0);
  96 }
  97
  98
  99 static void adm_read(int cs, char *buf, unsigned int bits)
 100 {
 101         int i, len = (bits + 7) / 8;
 102         __u8 mask;
 103
 104         gpioout(eecs, (cs ? eecs : 0));
 105         udelay(EECK_EDGE_TIME);
 106
 107         /* Byte assemble from MSB to LSB */
 108         for (i = 0; i < len; i++) {
 109                 __u8 byte;
 110
 111                 /* Bit bang from MSB to LSB */
 112                 for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {
 113                         __u8 gp;
 114
 115                         /* Clock low */
 116                         gpioout(eesk, 0);
 117                         udelay(EECK_EDGE_TIME);
 118
 119                         /* Input on rising edge */
 120                         gp = gpioin();
 121                         if (gp & eedi)
 122                                 byte |= mask;
 123
 124                         /* Clock high */
 125                         gpioout(eesk, eesk);
 126                         udelay(EECK_EDGE_TIME);
 127                 }
 128
 129                 *buf++ = byte;
 130         }
 131
 132         /* Clock low */
 133         gpioout(eesk, 0);
 134         udelay(EECK_EDGE_TIME);
 135
 136         if (cs)
 137                 gpioout(eecs, 0);
 138 }
 139
 140
 141 /* Enable outputs with specified value to the chip */
 142 static void adm_enout(__u8 pins, __u8 val)
 143 {
 144         /* Prepare GPIO output value */
 145         gpioout(pins, val);
 146
 147         /* Enable GPIO outputs */
 148         gpioouten(pins, pins);
 149         udelay(EECK_EDGE_TIME);
 150 }
 151
 152
 153 /* Disable outputs to the chip */
 154 static void adm_disout(__u8 pins)
 155 {
 156         /* Disable GPIO outputs */
 157         gpioouten(pins, 0);
 158         udelay(EECK_EDGE_TIME);
 159 }
 160
 161
 162 /* Advance clock(s) */
 163 static void adm_adclk(int clocks)
 164 {
 165         int i;
 166         for (i = 0; i < clocks; i++) {
 167                 /* Clock high */
 168                 gpioout(eesk, eesk);
 169                 udelay(EECK_EDGE_TIME);
 170
 171                 /* Clock low */
 172                 gpioout(eesk, 0);
 173                 udelay(EECK_EDGE_TIME);
 174         }
 175 }
 176
 177 static __u32 adm_rreg(__u8 table, __u8 addr)
 178 {
 179         /* cmd: 01 10 T DD R RRRRRR */
 180         __u8 bits[6] = {
 181                 0xFF, 0xFF, 0xFF, 0xFF,
 182                 (0x06 << 4) | ((table & 0x01) << 3 | (addr&64)>>6),
 183                 ((addr&62)<<2)
 184         };
 185
 186         __u8 rbits[4];
 187
 188         /* Enable GPIO outputs with all pins to 0 */
 189         adm_enout((__u8)(eecs | eesk | eedi), 0);
 190
 191         adm_write(0, bits, 46);
 192         adm_disout((__u8)(eedi));
 193         adm_adclk(2);
 194         adm_read (0, rbits, 32);
 195
 196         /* Extra clock(s) required per datasheet */
 197         adm_adclk(2);
 198
 199         /* Disable GPIO outputs */
 200         adm_disout((__u8)(eecs | eesk));
 201
 202         if (!table) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
 203                 return (addr & 0x01 ?  (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));
 204         else
 205                 return (rbits[0]<<24) | (rbits[1]<<16) | (rbits[2]<<8) | rbits[3];
 206 }
 207
 208
 209
 210 /* Write chip configuration register */
 211 /* Follow 93c66 timing and chip's min EEPROM timing requirement */
 212 void
 213 adm_wreg(__u8 addr, __u16 val)
 214 {
 215         /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
 216         __u8 bits[4] = {
 217                 (0x05 << 5) | (addr >> 3),
 218                 (addr << 5) | (__u8)(val >> 11),
 219                 (__u8)(val >> 3),
 220                 (__u8)(val << 5)
 221         };
 222
 223         /* Enable GPIO outputs with all pins to 0 */
 224         adm_enout((__u8)(eecs | eesk | eedi), 0);
 225
 226         /* Write cmd. Total 27 bits */
 227         adm_write(1, bits, 27);
 228
 229         /* Extra clock(s) required per datasheet */
 230         adm_adclk(2);
 231
 232         /* Disable GPIO outputs */
 233         adm_disout((__u8)(eecs | eesk | eedi));
 234 }
 235
 236
 237 /* Port configuration registers */
 238 static int port_conf[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
 239
 240 /* Bits in VLAN port mapping */
 241 static int vlan_ports[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
 242
 243 static int handle_vlan_port_read(char *buf, int nr)
 244 {
 245         int ports, i, c, len = 0;
 246
 247         if ((nr < 0) || (nr > 15))
 248                 return 0;
 249
 250         /* Get VLAN port map */
 251         ports = adm_rreg(0, 0x13 + nr);
 252
 253         for (i = 0; i <= 5; i++) {
 254                 if (ports & vlan_ports[i]) {
 255                         c = adm_rreg(0, port_conf[i]);
 256                         len += sprintf(buf + len, (c & (1 << 4) ? "%dt\t" : (i == 5 ? "%du\t" : "%d\t")), i);
 257                 }
 258         }
 259         len += sprintf(buf + len, "\n");
 260
 261         return len;
 262 }
 263
 264 static int handle_vlan_port_write(char *buf, int nr)
 265 {
 266         int i, c, ports;
 267         int map = switch_parse_vlan(buf);
 268
 269         if (map == -1)
 270                 return -1;
 271
 272         ports = adm_rreg(0, 0x13 + nr);
 273         for (i = 0; i <= 5; i++) {
 274                 if (map & (1 << i)) {
 275                         ports |= vlan_ports[i];
 276
 277                         c = adm_rreg(0, port_conf[i]);
 278
 279                         /* Tagging */
 280                         if (map & (1 << (8 + i)))
 281                                 c |= (1 << 4);
 282                         else
 283                                 c &= ~(1 << 4);
 284
 285                         c = (c & ~(0xf << 10)) | (nr << 10);
 286
 287                         adm_wreg(port_conf[i], (__u16) c);
 288                 } else {
 289                         ports &= ~(vlan_ports[i]);
 290                 }
 291         }
 292         adm_wreg(0x13 + nr, (__u16) ports);
 293
 294         return 0;
 295 }
 296
 297 static int handle_port_enable_read(char *buf, int nr)
 298 {
 299         return sprintf(buf, "%d\n", ((adm_rreg(0, port_conf[nr]) & (1 << 5)) ? 0 : 1));
 300 }
 301
 302 static int handle_port_enable_write(char *buf, int nr)
 303 {
 304         int reg = adm_rreg(0, port_conf[nr]);
 305
 306         if (buf[0] == '0')
 307                 reg |= (1 << 5);
 308         else if (buf[0] == '1')
 309                 reg &= ~(1 << 5);
 310         else return -1;
 311
 312         adm_wreg(port_conf[nr], (__u16) reg);
 313         return 0;
 314 }
 315
 316 static int handle_port_media_read(char *buf, int nr)
 317 {
 318         int len;
 319         int media = 0;
 320         int reg = adm_rreg(0, port_conf[nr]);
 321
 322         if (reg & (1 << 1))
 323                 media |= SWITCH_MEDIA_AUTO;
 324         if (reg & (1 << 2))
 325                 media |= SWITCH_MEDIA_100;
 326         if (reg & (1 << 3))
 327                 media |= SWITCH_MEDIA_FD;
 328
 329         len = switch_print_media(buf, media);
 330         return len + sprintf(buf + len, "\n");
 331 }
 332
 333 static int handle_port_media_write(char *buf, int nr)
 334 {
 335         int media = switch_parse_media(buf);
 336         int reg = adm_rreg(0, port_conf[nr]);
 337
 338         if (media < 0)
 339                 return -1;
 340
 341         reg &= ~((1 << 1) | (1 << 2) | (1 << 3));
 342         if (media & SWITCH_MEDIA_AUTO)
 343                 reg |= 1 << 1;
 344         if (media & SWITCH_MEDIA_100)
 345                 reg |= 1 << 2;
 346         if (media & SWITCH_MEDIA_FD)
 347                 reg |= 1 << 3;
 348
 349         adm_wreg(port_conf[nr], reg);
 350
 351         return 0;
 352 }
 353
 354 static int handle_vlan_enable_read(char *buf, int nr)
 355 {
 356         return sprintf(buf, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
 357 }
 358
 359 static int handle_vlan_enable_write(char *buf, int nr)
 360 {
 361         int reg = adm_rreg(0, 0x11);
 362
 363         if (buf[0] == '1')
 364                 reg |= (1 << 5);
 365         else if (buf[0] == '0')
 366                 reg &= ~(1 << 5);
 367         else return -1;
 368
 369         adm_wreg(0x11, (__u16) reg);
 370         return 0;
 371 }
 372
 373 static int handle_reset(char *buf, int nr)
 374 {
 375         int i;
 376
 377         /*
 378          * Reset sequence: RC high->low(100ms)->high(30ms)
 379          *
 380          * WAR: Certain boards don't have the correct power on
 381          * reset logic therefore we must explicitly perform the
 382          * sequence in software.
 383          */
 384         /* Keep RC high for at least 20ms */
 385         adm_enout(eerc, eerc);
 386         for (i = 0; i < 20; i ++)
 387                 udelay(1000);
 388         /* Keep RC low for at least 100ms */
 389         adm_enout(eerc, 0);
 390         for (i = 0; i < 100; i++)
 391                 udelay(1000);
 392         /* Set default configuration */
 393         adm_enout((__u8)(eesk | eedi), eesk);
 394         /* Keep RC high for at least 30ms */
 395         adm_enout(eerc, eerc);
 396         for (i = 0; i < 30; i++)
 397                 udelay(1000);
 398         /* Leave RC high and disable GPIO outputs */
 399         adm_disout((__u8)(eecs | eesk | eedi));
 400
 401         /* set up initial configuration for ports */
 402         for (i = 0; i <= 5; i++) {
 403                 int cfg = 0x8000 | /* Auto MDIX */
 404                         (((i == 5) ? 1 : 0) << 4) | /* Tagging */
 405                         0xf; /* full duplex, 100Mbps, auto neg, flow ctrl */
 406                 adm_wreg(port_conf[i], cfg);
 407         }
 408
 409         /* vlan mode select register (0x11): vlan on, mac clone */
 410         adm_wreg(0x11, 0xff30);
 411
 412         return 0;
 413 }
 414
 415 static int handle_registers(char *buf, int nr)
 416 {
 417         int i, len = 0;
 418
 419         for (i = 0; i <= 0x33; i++) {
 420                 len += sprintf(buf + len, "0x%02x: 0x%04x\n", i, adm_rreg(0, i));
 421         }
 422
 423         return len;
 424 }
 425
 426 static int handle_counters(char *buf, int nr)
 427 {
 428         int i, len = 0;
 429
 430         for (i = 0; i <= 0x3c; i++) {
 431                 len += sprintf(buf + len, "0x%02x: 0x%08x\n", i, adm_rreg(1, i));
 432         }
 433
 434         return len;
 435 }
 436
 437 static int detect_adm()
 438 {
 439         int ret = 0;
 440
 441 #if defined(BCMGPIO2) || defined(BCMGPIO)
 442 #ifdef LINUX_2_4
 443         int boardflags = getintvar(NULL, "boardflags");
 444 #else
 445         extern int boardflags;
 446 #endif
 447         if ((boardflags & 0x80) || force)
 448                 ret = 1;
 449         else
 450                 printk("BFL_ENETADM not set in boardflags. Use force=1 to ignore.\n");
 451 #else
 452         ret = 1;
 453 #endif
 454
 455         return ret;
 456 }
 457
 458 static int __init adm_init()
 459 {
 460         switch_config cfg[] = {
 461                 {"registers", handle_registers, NULL},
 462                 {"counters", handle_counters, NULL},
 463                 {"reset", NULL, handle_reset},
 464                 {"enable_vlan", handle_vlan_enable_read, handle_vlan_enable_write},
 465                 {NULL, NULL, NULL}
 466         };
 467         switch_config port[] = {
 468                 {"enabled", handle_port_enable_read, handle_port_enable_write},
 469                 {"media", handle_port_media_read, handle_port_media_write},
 470                 {NULL, NULL, NULL}
 471         };
 472         switch_config vlan[] = {
 473                 {"ports", handle_vlan_port_read, handle_vlan_port_write},
 474                 {NULL, NULL, NULL}
 475         };
 476         switch_driver driver = {
 477                 name: DRIVER_NAME,
 478                 ports: 6,
 479                 vlans: 16,
 480                 driver_handlers: cfg,
 481                 port_handlers: port,
 482                 vlan_handlers: vlan,
 483         };
 484
 485         eecs = (1 << eecs);
 486         eesk = (1 << eesk);
 487         eedi = (1 << eedi);
 488
 489         if (!detect_adm())
 490                 return -ENODEV;
 491
 492         return switch_register_driver(&driver);
 493 }
 494
 495 static void __exit adm_exit()
 496 {
 497         switch_unregister_driver(DRIVER_NAME);
 498 }
 499
 500
 501 module_init(adm_init);
 502 module_exit(adm_exit);