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ath9k: do not strip MMIC for key miss frames
[openwrt.git] / package / mac80211 / patches / 300-pending_work.patch
1 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
2 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
3 @@ -170,33 +170,104 @@ static bool ar9002_hw_get_isr(struct ath
4 return true;
5 }
6
7 -static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
8 - bool is_firstseg, bool is_lastseg,
9 - const void *ds0, dma_addr_t buf_addr,
10 - unsigned int qcu)
11 +static void
12 +ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
13 {
14 struct ar5416_desc *ads = AR5416DESC(ds);
15 + u32 ctl1, ctl6;
16
17 - ads->ds_data = buf_addr;
18 -
19 - if (is_firstseg) {
20 - ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
21 - } else if (is_lastseg) {
22 - ads->ds_ctl0 = 0;
23 - ads->ds_ctl1 = seglen;
24 - ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
25 - ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
26 - } else {
27 - ads->ds_ctl0 = 0;
28 - ads->ds_ctl1 = seglen | AR_TxMore;
29 - ads->ds_ctl2 = 0;
30 - ads->ds_ctl3 = 0;
31 - }
32 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
33 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
34 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
35 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
36 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
37 +
38 + ACCESS_ONCE(ads->ds_link) = i->link;
39 + ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];
40 +
41 + ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore);
42 + ctl6 = SM(i->keytype, AR_EncrType);
43 +
44 + if (AR_SREV_9285(ah)) {
45 + ads->ds_ctl8 = 0;
46 + ads->ds_ctl9 = 0;
47 + ads->ds_ctl10 = 0;
48 + ads->ds_ctl11 = 0;
49 + }
50 +
51 + if ((i->is_first || i->is_last) &&
52 + i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
53 + ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
54 + | set11nTries(i->rates, 1)
55 + | set11nTries(i->rates, 2)
56 + | set11nTries(i->rates, 3)
57 + | (i->dur_update ? AR_DurUpdateEna : 0)
58 + | SM(0, AR_BurstDur);
59 +
60 + ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
61 + | set11nRate(i->rates, 1)
62 + | set11nRate(i->rates, 2)
63 + | set11nRate(i->rates, 3);
64 + } else {
65 + ACCESS_ONCE(ads->ds_ctl2) = 0;
66 + ACCESS_ONCE(ads->ds_ctl3) = 0;
67 + }
68 +
69 + if (!i->is_first) {
70 + ACCESS_ONCE(ads->ds_ctl0) = 0;
71 + ACCESS_ONCE(ads->ds_ctl1) = ctl1;
72 + ACCESS_ONCE(ads->ds_ctl6) = ctl6;
73 + return;
74 + }
75 +
76 + ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
77 + | SM(i->type, AR_FrameType)
78 + | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
79 + | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
80 + | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
81 +
82 + switch (i->aggr) {
83 + case AGGR_BUF_FIRST:
84 + ctl6 |= SM(i->aggr_len, AR_AggrLen);
85 + /* fall through */
86 + case AGGR_BUF_MIDDLE:
87 + ctl1 |= AR_IsAggr | AR_MoreAggr;
88 + ctl6 |= SM(i->ndelim, AR_PadDelim);
89 + break;
90 + case AGGR_BUF_LAST:
91 + ctl1 |= AR_IsAggr;
92 + break;
93 + case AGGR_BUF_NONE:
94 + break;
95 + }
96 +
97 + ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
98 + | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
99 + | SM(i->txpower, AR_XmitPower)
100 + | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
101 + | (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
102 + | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
103 + | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
104 + | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
105 + (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
106 +
107 + ACCESS_ONCE(ads->ds_ctl1) = ctl1;
108 + ACCESS_ONCE(ads->ds_ctl6) = ctl6;
109 +
110 + if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST)
111 + return;
112 +
113 + ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
114 + | set11nPktDurRTSCTS(i->rates, 1);
115 +
116 + ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
117 + | set11nPktDurRTSCTS(i->rates, 3);
118 +
119 + ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
120 + | set11nRateFlags(i->rates, 1)
121 + | set11nRateFlags(i->rates, 2)
122 + | set11nRateFlags(i->rates, 3)
123 + | SM(i->rtscts_rate, AR_RTSCTSRate);
124 }
125
126 static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
127 @@ -271,145 +342,6 @@ static int ar9002_hw_proc_txdesc(struct
128 return 0;
129 }
130
131 -static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
132 - u32 pktLen, enum ath9k_pkt_type type,
133 - u32 txPower, u8 keyIx,
134 - enum ath9k_key_type keyType, u32 flags)
135 -{
136 - struct ar5416_desc *ads = AR5416DESC(ds);
137 -
138 - if (txPower > 63)
139 - txPower = 63;
140 -
141 - ads->ds_ctl0 = (pktLen & AR_FrameLen)
142 - | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
143 - | SM(txPower, AR_XmitPower)
144 - | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
145 - | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
146 - | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
147 -
148 - ads->ds_ctl1 =
149 - (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
150 - | SM(type, AR_FrameType)
151 - | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
152 - | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
153 - | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
154 -
155 - ads->ds_ctl6 = SM(keyType, AR_EncrType);
156 -
157 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
158 - ads->ds_ctl8 = 0;
159 - ads->ds_ctl9 = 0;
160 - ads->ds_ctl10 = 0;
161 - ads->ds_ctl11 = 0;
162 - }
163 -}
164 -
165 -static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
166 -{
167 - struct ar5416_desc *ads = AR5416DESC(ds);
168 -
169 - if (val)
170 - ads->ds_ctl0 |= AR_ClrDestMask;
171 - else
172 - ads->ds_ctl0 &= ~AR_ClrDestMask;
173 -}
174 -
175 -static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
176 - void *lastds,
177 - u32 durUpdateEn, u32 rtsctsRate,
178 - u32 rtsctsDuration,
179 - struct ath9k_11n_rate_series series[],
180 - u32 nseries, u32 flags)
181 -{
182 - struct ar5416_desc *ads = AR5416DESC(ds);
183 - struct ar5416_desc *last_ads = AR5416DESC(lastds);
184 - u32 ds_ctl0;
185 -
186 - if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
187 - ds_ctl0 = ads->ds_ctl0;
188 -
189 - if (flags & ATH9K_TXDESC_RTSENA) {
190 - ds_ctl0 &= ~AR_CTSEnable;
191 - ds_ctl0 |= AR_RTSEnable;
192 - } else {
193 - ds_ctl0 &= ~AR_RTSEnable;
194 - ds_ctl0 |= AR_CTSEnable;
195 - }
196 -
197 - ads->ds_ctl0 = ds_ctl0;
198 - } else {
199 - ads->ds_ctl0 =
200 - (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
201 - }
202 -
203 - ads->ds_ctl2 = set11nTries(series, 0)
204 - | set11nTries(series, 1)
205 - | set11nTries(series, 2)
206 - | set11nTries(series, 3)
207 - | (durUpdateEn ? AR_DurUpdateEna : 0)
208 - | SM(0, AR_BurstDur);
209 -
210 - ads->ds_ctl3 = set11nRate(series, 0)
211 - | set11nRate(series, 1)
212 - | set11nRate(series, 2)
213 - | set11nRate(series, 3);
214 -
215 - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
216 - | set11nPktDurRTSCTS(series, 1);
217 -
218 - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
219 - | set11nPktDurRTSCTS(series, 3);
220 -
221 - ads->ds_ctl7 = set11nRateFlags(series, 0)
222 - | set11nRateFlags(series, 1)
223 - | set11nRateFlags(series, 2)
224 - | set11nRateFlags(series, 3)
225 - | SM(rtsctsRate, AR_RTSCTSRate);
226 - last_ads->ds_ctl2 = ads->ds_ctl2;
227 - last_ads->ds_ctl3 = ads->ds_ctl3;
228 -}
229 -
230 -static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
231 - u32 aggrLen)
232 -{
233 - struct ar5416_desc *ads = AR5416DESC(ds);
234 -
235 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
236 - ads->ds_ctl6 &= ~AR_AggrLen;
237 - ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
238 -}
239 -
240 -static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
241 - u32 numDelims)
242 -{
243 - struct ar5416_desc *ads = AR5416DESC(ds);
244 - unsigned int ctl6;
245 -
246 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
247 -
248 - ctl6 = ads->ds_ctl6;
249 - ctl6 &= ~AR_PadDelim;
250 - ctl6 |= SM(numDelims, AR_PadDelim);
251 - ads->ds_ctl6 = ctl6;
252 -}
253 -
254 -static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
255 -{
256 - struct ar5416_desc *ads = AR5416DESC(ds);
257 -
258 - ads->ds_ctl1 |= AR_IsAggr;
259 - ads->ds_ctl1 &= ~AR_MoreAggr;
260 - ads->ds_ctl6 &= ~AR_PadDelim;
261 -}
262 -
263 -static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
264 -{
265 - struct ar5416_desc *ads = AR5416DESC(ds);
266 -
267 - ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
268 -}
269 -
270 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
271 u32 size, u32 flags)
272 {
273 @@ -433,13 +365,6 @@ void ar9002_hw_attach_mac_ops(struct ath
274 ops->rx_enable = ar9002_hw_rx_enable;
275 ops->set_desc_link = ar9002_hw_set_desc_link;
276 ops->get_isr = ar9002_hw_get_isr;
277 - ops->fill_txdesc = ar9002_hw_fill_txdesc;
278 + ops->set_txdesc = ar9002_set_txdesc;
279 ops->proc_txdesc = ar9002_hw_proc_txdesc;
280 - ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
281 - ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
282 - ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
283 - ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
284 - ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
285 - ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
286 - ops->set_clrdmask = ar9002_hw_set_clrdmask;
287 }
288 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
289 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
290 @@ -652,8 +652,9 @@ static void ar9003_hw_detect_outlier(int
291 outlier_idx = max_idx;
292 else
293 outlier_idx = min_idx;
294 +
295 + mp_coeff[outlier_idx] = mp_avg;
296 }
297 - mp_coeff[outlier_idx] = mp_avg;
298 }
299
300 static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
301 @@ -884,6 +885,7 @@ static bool ar9003_hw_init_cal(struct at
302 if (txiqcal_done)
303 ar9003_hw_tx_iq_cal_post_proc(ah);
304
305 + ath9k_hw_loadnf(ah, chan);
306 ath9k_hw_start_nfcal(ah, true);
307
308 /* Initialize list pointers */
309 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
310 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
311 @@ -21,6 +21,132 @@ static void ar9003_hw_rx_enable(struct a
312 REG_WRITE(hw, AR_CR, 0);
313 }
314
315 +static void
316 +ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
317 +{
318 + struct ar9003_txc *ads = ds;
319 + int checksum = 0;
320 + u32 val, ctl12, ctl17;
321 +
322 + val = (ATHEROS_VENDOR_ID << AR_DescId_S) |
323 + (1 << AR_TxRxDesc_S) |
324 + (1 << AR_CtrlStat_S) |
325 + (i->qcu << AR_TxQcuNum_S) | 0x17;
326 +
327 + checksum += val;
328 + ACCESS_ONCE(ads->info) = val;
329 +
330 + checksum += i->link;
331 + ACCESS_ONCE(ads->link) = i->link;
332 +
333 + checksum += i->buf_addr[0];
334 + ACCESS_ONCE(ads->data0) = i->buf_addr[0];
335 + checksum += i->buf_addr[1];
336 + ACCESS_ONCE(ads->data1) = i->buf_addr[1];
337 + checksum += i->buf_addr[2];
338 + ACCESS_ONCE(ads->data2) = i->buf_addr[2];
339 + checksum += i->buf_addr[3];
340 + ACCESS_ONCE(ads->data3) = i->buf_addr[3];
341 +
342 + checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen);
343 + ACCESS_ONCE(ads->ctl3) = val;
344 + checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen);
345 + ACCESS_ONCE(ads->ctl5) = val;
346 + checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen);
347 + ACCESS_ONCE(ads->ctl7) = val;
348 + checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen);
349 + ACCESS_ONCE(ads->ctl9) = val;
350 +
351 + checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff);
352 + ACCESS_ONCE(ads->ctl10) = checksum;
353 +
354 + if (i->is_first || i->is_last) {
355 + ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0)
356 + | set11nTries(i->rates, 1)
357 + | set11nTries(i->rates, 2)
358 + | set11nTries(i->rates, 3)
359 + | (i->dur_update ? AR_DurUpdateEna : 0)
360 + | SM(0, AR_BurstDur);
361 +
362 + ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0)
363 + | set11nRate(i->rates, 1)
364 + | set11nRate(i->rates, 2)
365 + | set11nRate(i->rates, 3);
366 + } else {
367 + ACCESS_ONCE(ads->ctl13) = 0;
368 + ACCESS_ONCE(ads->ctl14) = 0;
369 + }
370 +
371 + ads->ctl20 = 0;
372 + ads->ctl21 = 0;
373 + ads->ctl22 = 0;
374 +
375 + ctl17 = SM(i->keytype, AR_EncrType);
376 + if (!i->is_first) {
377 + ACCESS_ONCE(ads->ctl11) = 0;
378 + ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore;
379 + ACCESS_ONCE(ads->ctl15) = 0;
380 + ACCESS_ONCE(ads->ctl16) = 0;
381 + ACCESS_ONCE(ads->ctl17) = ctl17;
382 + ACCESS_ONCE(ads->ctl18) = 0;
383 + ACCESS_ONCE(ads->ctl19) = 0;
384 + return;
385 + }
386 +
387 + ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen)
388 + | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
389 + | SM(i->txpower, AR_XmitPower)
390 + | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
391 + | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
392 + | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0)
393 + | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
394 + | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
395 + (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
396 +
397 + ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ?
398 + SM(i->keyix, AR_DestIdx) : 0)
399 + | SM(i->type, AR_FrameType)
400 + | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
401 + | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
402 + | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
403 +
404 + ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
405 + switch (i->aggr) {
406 + case AGGR_BUF_FIRST:
407 + ctl17 |= SM(i->aggr_len, AR_AggrLen);
408 + /* fall through */
409 + case AGGR_BUF_MIDDLE:
410 + ctl12 |= AR_IsAggr | AR_MoreAggr;
411 + ctl17 |= SM(i->ndelim, AR_PadDelim);
412 + break;
413 + case AGGR_BUF_LAST:
414 + ctl12 |= AR_IsAggr;
415 + break;
416 + case AGGR_BUF_NONE:
417 + break;
418 + }
419 +
420 + val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S;
421 + ctl12 |= SM(val, AR_PAPRDChainMask);
422 +
423 + ACCESS_ONCE(ads->ctl12) = ctl12;
424 + ACCESS_ONCE(ads->ctl17) = ctl17;
425 +
426 + ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0)
427 + | set11nPktDurRTSCTS(i->rates, 1);
428 +
429 + ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2)
430 + | set11nPktDurRTSCTS(i->rates, 3);
431 +
432 + ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0)
433 + | set11nRateFlags(i->rates, 1)
434 + | set11nRateFlags(i->rates, 2)
435 + | set11nRateFlags(i->rates, 3)
436 + | SM(i->rtscts_rate, AR_RTSCTSRate);
437 +
438 + ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding;
439 +}
440 +
441 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
442 {
443 int checksum;
444 @@ -185,47 +311,6 @@ static bool ar9003_hw_get_isr(struct ath
445 return true;
446 }
447
448 -static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
449 - bool is_firstseg, bool is_lastseg,
450 - const void *ds0, dma_addr_t buf_addr,
451 - unsigned int qcu)
452 -{
453 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
454 - unsigned int descid = 0;
455 -
456 - ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
457 - (1 << AR_TxRxDesc_S) |
458 - (1 << AR_CtrlStat_S) |
459 - (qcu << AR_TxQcuNum_S) | 0x17;
460 -
461 - ads->data0 = buf_addr;
462 - ads->data1 = 0;
463 - ads->data2 = 0;
464 - ads->data3 = 0;
465 -
466 - ads->ctl3 = (seglen << AR_BufLen_S);
467 - ads->ctl3 &= AR_BufLen;
468 -
469 - /* Fill in pointer checksum and descriptor id */
470 - ads->ctl10 = ar9003_calc_ptr_chksum(ads);
471 - ads->ctl10 |= (descid << AR_TxDescId_S);
472 -
473 - if (is_firstseg) {
474 - ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
475 - } else if (is_lastseg) {
476 - ads->ctl11 = 0;
477 - ads->ctl12 = 0;
478 - ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
479 - ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
480 - } else {
481 - /* XXX Intermediate descriptor in a multi-descriptor frame.*/
482 - ads->ctl11 = 0;
483 - ads->ctl12 = AR_TxMore;
484 - ads->ctl13 = 0;
485 - ads->ctl14 = 0;
486 - }
487 -}
488 -
489 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
490 struct ath_tx_status *ts)
491 {
492 @@ -310,161 +395,6 @@ static int ar9003_hw_proc_txdesc(struct
493 return 0;
494 }
495
496 -static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
497 - u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
498 - u8 keyIx, enum ath9k_key_type keyType, u32 flags)
499 -{
500 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
501 -
502 - if (txpower > ah->txpower_limit)
503 - txpower = ah->txpower_limit;
504 -
505 - if (txpower > 63)
506 - txpower = 63;
507 -
508 - ads->ctl11 = (pktlen & AR_FrameLen)
509 - | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
510 - | SM(txpower, AR_XmitPower)
511 - | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
512 - | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
513 - | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
514 -
515 - ads->ctl12 =
516 - (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
517 - | SM(type, AR_FrameType)
518 - | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
519 - | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
520 - | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
521 -
522 - ads->ctl17 = SM(keyType, AR_EncrType) |
523 - (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
524 - ads->ctl18 = 0;
525 - ads->ctl19 = AR_Not_Sounding;
526 -
527 - ads->ctl20 = 0;
528 - ads->ctl21 = 0;
529 - ads->ctl22 = 0;
530 -}
531 -
532 -static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
533 -{
534 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
535 -
536 - if (val)
537 - ads->ctl11 |= AR_ClrDestMask;
538 - else
539 - ads->ctl11 &= ~AR_ClrDestMask;
540 -}
541 -
542 -static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
543 - void *lastds,
544 - u32 durUpdateEn, u32 rtsctsRate,
545 - u32 rtsctsDuration,
546 - struct ath9k_11n_rate_series series[],
547 - u32 nseries, u32 flags)
548 -{
549 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
550 - struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
551 - u_int32_t ctl11;
552 -
553 - if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
554 - ctl11 = ads->ctl11;
555 -
556 - if (flags & ATH9K_TXDESC_RTSENA) {
557 - ctl11 &= ~AR_CTSEnable;
558 - ctl11 |= AR_RTSEnable;
559 - } else {
560 - ctl11 &= ~AR_RTSEnable;
561 - ctl11 |= AR_CTSEnable;
562 - }
563 -
564 - ads->ctl11 = ctl11;
565 - } else {
566 - ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
567 - }
568 -
569 - ads->ctl13 = set11nTries(series, 0)
570 - | set11nTries(series, 1)
571 - | set11nTries(series, 2)
572 - | set11nTries(series, 3)
573 - | (durUpdateEn ? AR_DurUpdateEna : 0)
574 - | SM(0, AR_BurstDur);
575 -
576 - ads->ctl14 = set11nRate(series, 0)
577 - | set11nRate(series, 1)
578 - | set11nRate(series, 2)
579 - | set11nRate(series, 3);
580 -
581 - ads->ctl15 = set11nPktDurRTSCTS(series, 0)
582 - | set11nPktDurRTSCTS(series, 1);
583 -
584 - ads->ctl16 = set11nPktDurRTSCTS(series, 2)
585 - | set11nPktDurRTSCTS(series, 3);
586 -
587 - ads->ctl18 = set11nRateFlags(series, 0)
588 - | set11nRateFlags(series, 1)
589 - | set11nRateFlags(series, 2)
590 - | set11nRateFlags(series, 3)
591 - | SM(rtsctsRate, AR_RTSCTSRate);
592 - ads->ctl19 = AR_Not_Sounding;
593 -
594 - last_ads->ctl13 = ads->ctl13;
595 - last_ads->ctl14 = ads->ctl14;
596 -}
597 -
598 -static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
599 - u32 aggrLen)
600 -{
601 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
602 -
603 - ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
604 -
605 - ads->ctl17 &= ~AR_AggrLen;
606 - ads->ctl17 |= SM(aggrLen, AR_AggrLen);
607 -}
608 -
609 -static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
610 - u32 numDelims)
611 -{
612 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
613 - unsigned int ctl17;
614 -
615 - ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
616 -
617 - /*
618 - * We use a stack variable to manipulate ctl6 to reduce uncached
619 - * read modify, modfiy, write.
620 - */
621 - ctl17 = ads->ctl17;
622 - ctl17 &= ~AR_PadDelim;
623 - ctl17 |= SM(numDelims, AR_PadDelim);
624 - ads->ctl17 = ctl17;
625 -}
626 -
627 -static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
628 -{
629 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
630 -
631 - ads->ctl12 |= AR_IsAggr;
632 - ads->ctl12 &= ~AR_MoreAggr;
633 - ads->ctl17 &= ~AR_PadDelim;
634 -}
635 -
636 -static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
637 -{
638 - struct ar9003_txc *ads = (struct ar9003_txc *) ds;
639 -
640 - ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
641 -}
642 -
643 -void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
644 -{
645 - struct ar9003_txc *ads = ds;
646 -
647 - ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
648 -}
649 -EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc);
650 -
651 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
652 {
653 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
654 @@ -472,15 +402,8 @@ void ar9003_hw_attach_mac_ops(struct ath
655 ops->rx_enable = ar9003_hw_rx_enable;
656 ops->set_desc_link = ar9003_hw_set_desc_link;
657 ops->get_isr = ar9003_hw_get_isr;
658 - ops->fill_txdesc = ar9003_hw_fill_txdesc;
659 + ops->set_txdesc = ar9003_set_txdesc;
660 ops->proc_txdesc = ar9003_hw_proc_txdesc;
661 - ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
662 - ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
663 - ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
664 - ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
665 - ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
666 - ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
667 - ops->set_clrdmask = ar9003_hw_set_clrdmask;
668 }
669
670 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
671 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
672 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
673 @@ -87,17 +87,14 @@ struct ath_config {
674 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
675 * @BUF_AGGR: Indicates whether the buffer can be aggregated
676 * (used in aggregation scheduling)
677 - * @BUF_XRETRY: To denote excessive retries of the buffer
678 */
679 enum buffer_type {
680 BUF_AMPDU = BIT(0),
681 BUF_AGGR = BIT(1),
682 - BUF_XRETRY = BIT(2),
683 };
684
685 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
686 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
687 -#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
688
689 #define ATH_TXSTATUS_RING_SIZE 64
690
691 @@ -216,6 +213,7 @@ struct ath_frame_info {
692 struct ath_buf_state {
693 u8 bf_type;
694 u8 bfs_paprd;
695 + u8 ndelim;
696 u16 seqno;
697 unsigned long bfs_paprd_timestamp;
698 };
699 @@ -230,7 +228,6 @@ struct ath_buf {
700 dma_addr_t bf_daddr; /* physical addr of desc */
701 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
702 bool bf_stale;
703 - u16 bf_flags;
704 struct ath_buf_state bf_state;
705 };
706
707 @@ -277,8 +274,7 @@ struct ath_tx_control {
708 };
709
710 #define ATH_TX_ERROR 0x01
711 -#define ATH_TX_XRETRY 0x02
712 -#define ATH_TX_BAR 0x04
713 +#define ATH_TX_BAR 0x02
714
715 /**
716 * @txq_map: Index is mac80211 queue number. This is
717 --- a/drivers/net/wireless/ath/ath9k/beacon.c
718 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
719 @@ -73,44 +73,39 @@ static void ath_beacon_setup(struct ath_
720 struct sk_buff *skb = bf->bf_mpdu;
721 struct ath_hw *ah = sc->sc_ah;
722 struct ath_common *common = ath9k_hw_common(ah);
723 - struct ath_desc *ds;
724 - struct ath9k_11n_rate_series series[4];
725 - int flags, ctsrate = 0, ctsduration = 0;
726 + struct ath_tx_info info;
727 struct ieee80211_supported_band *sband;
728 + u8 chainmask = ah->txchainmask;
729 u8 rate = 0;
730
731 ath9k_reset_beacon_status(sc);
732
733 - ds = bf->bf_desc;
734 - flags = ATH9K_TXDESC_NOACK;
735 -
736 - ds->ds_link = 0;
737 -
738 sband = &sc->sbands[common->hw->conf.channel->band];
739 rate = sband->bitrates[rateidx].hw_value;
740 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
741 rate |= sband->bitrates[rateidx].hw_value_short;
742
743 - ath9k_hw_set11n_txdesc(ah, ds, skb->len + FCS_LEN,
744 - ATH9K_PKT_TYPE_BEACON,
745 - MAX_RATE_POWER,
746 - ATH9K_TXKEYIX_INVALID,
747 - ATH9K_KEY_TYPE_CLEAR,
748 - flags);
749 -
750 - /* NB: beacon's BufLen must be a multiple of 4 bytes */
751 - ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4),
752 - true, true, ds, bf->bf_buf_addr,
753 - sc->beacon.beaconq);
754 -
755 - memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
756 - series[0].Tries = 1;
757 - series[0].Rate = rate;
758 - series[0].ChSel = ath_txchainmask_reduction(sc,
759 - ah->txchainmask, series[0].Rate);
760 - series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
761 - ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
762 - series, 4, 0);
763 + memset(&info, 0, sizeof(info));
764 + info.pkt_len = skb->len + FCS_LEN;
765 + info.type = ATH9K_PKT_TYPE_BEACON;
766 + info.txpower = MAX_RATE_POWER;
767 + info.keyix = ATH9K_TXKEYIX_INVALID;
768 + info.keytype = ATH9K_KEY_TYPE_CLEAR;
769 + info.flags = ATH9K_TXDESC_NOACK;
770 +
771 + info.buf_addr[0] = bf->bf_buf_addr;
772 + info.buf_len[0] = roundup(skb->len, 4);
773 +
774 + info.is_first = true;
775 + info.is_last = true;
776 +
777 + info.qcu = sc->beacon.beaconq;
778 +
779 + info.rates[0].Tries = 1;
780 + info.rates[0].Rate = rate;
781 + info.rates[0].ChSel = ath_txchainmask_reduction(sc, chainmask, rate);
782 +
783 + ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
784 }
785
786 static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
787 @@ -517,6 +512,7 @@ static void ath_beacon_config_ap(struct
788 /* Set the computed AP beacon timers */
789
790 ath9k_hw_disable_interrupts(ah);
791 + sc->sc_flags |= SC_OP_TSF_RESET;
792 ath9k_beacon_init(sc, nexttbtt, intval);
793 sc->beacon.bmisscnt = 0;
794 ath9k_hw_set_interrupts(ah, ah->imask);
795 --- a/drivers/net/wireless/ath/ath9k/debug.c
796 +++ b/drivers/net/wireless/ath/ath9k/debug.c
797 @@ -826,7 +826,8 @@ static ssize_t read_file_misc(struct fil
798 }
799
800 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
801 - struct ath_tx_status *ts, struct ath_txq *txq)
802 + struct ath_tx_status *ts, struct ath_txq *txq,
803 + unsigned int flags)
804 {
805 #define TX_SAMP_DBG(c) (sc->debug.bb_mac_samp[sc->debug.sampidx].ts\
806 [sc->debug.tsidx].c)
807 @@ -836,12 +837,12 @@ void ath_debug_stat_tx(struct ath_softc
808 sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len;
809
810 if (bf_isampdu(bf)) {
811 - if (bf_isxretried(bf))
812 + if (flags & ATH_TX_BAR)
813 TX_STAT_INC(qnum, a_xretries);
814 else
815 TX_STAT_INC(qnum, a_completed);
816 } else {
817 - if (bf_isxretried(bf))
818 + if (ts->ts_status & ATH9K_TXERR_XRETRY)
819 TX_STAT_INC(qnum, xretries);
820 else
821 TX_STAT_INC(qnum, completed);
822 --- a/drivers/net/wireless/ath/ath9k/debug.h
823 +++ b/drivers/net/wireless/ath/ath9k/debug.h
824 @@ -230,7 +230,8 @@ int ath9k_init_debug(struct ath_hw *ah);
825 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
826 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
827 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
828 - struct ath_tx_status *ts, struct ath_txq *txq);
829 + struct ath_tx_status *ts, struct ath_txq *txq,
830 + unsigned int flags);
831 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
832
833 #else
834 @@ -252,7 +253,8 @@ static inline void ath_debug_stat_interr
835 static inline void ath_debug_stat_tx(struct ath_softc *sc,
836 struct ath_buf *bf,
837 struct ath_tx_status *ts,
838 - struct ath_txq *txq)
839 + struct ath_txq *txq,
840 + unsigned int flags)
841 {
842 }
843
844 --- a/drivers/net/wireless/ath/ath9k/hw-ops.h
845 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
846 @@ -54,13 +54,10 @@ static inline bool ath9k_hw_getisr(struc
847 return ath9k_hw_ops(ah)->get_isr(ah, masked);
848 }
849
850 -static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
851 - bool is_firstseg, bool is_lastseg,
852 - const void *ds0, dma_addr_t buf_addr,
853 - unsigned int qcu)
854 +static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds,
855 + struct ath_tx_info *i)
856 {
857 - ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
858 - ds0, buf_addr, qcu);
859 + return ath9k_hw_ops(ah)->set_txdesc(ah, ds, i);
860 }
861
862 static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
863 @@ -69,55 +66,6 @@ static inline int ath9k_hw_txprocdesc(st
864 return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
865 }
866
867 -static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
868 - u32 pktLen, enum ath9k_pkt_type type,
869 - u32 txPower, u32 keyIx,
870 - enum ath9k_key_type keyType,
871 - u32 flags)
872 -{
873 - ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
874 - keyType, flags);
875 -}
876 -
877 -static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
878 - void *lastds,
879 - u32 durUpdateEn, u32 rtsctsRate,
880 - u32 rtsctsDuration,
881 - struct ath9k_11n_rate_series series[],
882 - u32 nseries, u32 flags)
883 -{
884 - ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
885 - rtsctsRate, rtsctsDuration, series,
886 - nseries, flags);
887 -}
888 -
889 -static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
890 - u32 aggrLen)
891 -{
892 - ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
893 -}
894 -
895 -static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
896 - u32 numDelims)
897 -{
898 - ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
899 -}
900 -
901 -static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
902 -{
903 - ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
904 -}
905 -
906 -static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
907 -{
908 - ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
909 -}
910 -
911 -static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
912 -{
913 - ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
914 -}
915 -
916 static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
917 struct ath_hw_antcomb_conf *antconf)
918 {
919 @@ -233,11 +181,6 @@ static inline void ath9k_hw_restore_chai
920 return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
921 }
922
923 -static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
924 -{
925 - return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
926 -}
927 -
928 static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
929 enum ath9k_ani_cmd cmd, int param)
930 {
931 --- a/drivers/net/wireless/ath/ath9k/hw.c
932 +++ b/drivers/net/wireless/ath/ath9k/hw.c
933 @@ -1496,14 +1496,16 @@ int ath9k_hw_reset(struct ath_hw *ah, st
934 }
935 ah->noise = ath9k_hw_getchan_noise(ah, chan);
936
937 + if ((AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) ||
938 + (AR_SREV_9300_20_OR_LATER(ah) && IS_CHAN_5GHZ(chan)))
939 + bChannelChange = false;
940 +
941 if (bChannelChange &&
942 (ah->chip_fullsleep != true) &&
943 (ah->curchan != NULL) &&
944 (chan->channel != ah->curchan->channel) &&
945 ((chan->channelFlags & CHANNEL_ALL) ==
946 - (ah->curchan->channelFlags & CHANNEL_ALL)) &&
947 - (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
948 -
949 + (ah->curchan->channelFlags & CHANNEL_ALL))) {
950 if (ath9k_hw_channel_change(ah, chan)) {
951 ath9k_hw_loadnf(ah, ah->curchan);
952 ath9k_hw_start_nfcal(ah, true);
953 --- a/drivers/net/wireless/ath/ath9k/hw.h
954 +++ b/drivers/net/wireless/ath/ath9k/hw.h
955 @@ -583,7 +583,6 @@ struct ath_hw_private_ops {
956 bool (*rfbus_req)(struct ath_hw *ah);
957 void (*rfbus_done)(struct ath_hw *ah);
958 void (*restore_chainmask)(struct ath_hw *ah);
959 - void (*set_diversity)(struct ath_hw *ah, bool value);
960 u32 (*compute_pll_control)(struct ath_hw *ah,
961 struct ath9k_channel *chan);
962 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
963 @@ -615,30 +614,10 @@ struct ath_hw_ops {
964 u8 rxchainmask,
965 bool longcal);
966 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
967 - void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
968 - bool is_firstseg, bool is_is_lastseg,
969 - const void *ds0, dma_addr_t buf_addr,
970 - unsigned int qcu);
971 + void (*set_txdesc)(struct ath_hw *ah, void *ds,
972 + struct ath_tx_info *i);
973 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
974 struct ath_tx_status *ts);
975 - void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
976 - u32 pktLen, enum ath9k_pkt_type type,
977 - u32 txPower, u8 keyIx,
978 - enum ath9k_key_type keyType,
979 - u32 flags);
980 - void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
981 - void *lastds,
982 - u32 durUpdateEn, u32 rtsctsRate,
983 - u32 rtsctsDuration,
984 - struct ath9k_11n_rate_series series[],
985 - u32 nseries, u32 flags);
986 - void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
987 - u32 aggrLen);
988 - void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
989 - u32 numDelims);
990 - void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
991 - void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
992 - void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
993 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
994 struct ath_hw_antcomb_conf *antconf);
995 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
996 --- a/drivers/net/wireless/ath/ath9k/mac.c
997 +++ b/drivers/net/wireless/ath/ath9k/mac.c
998 @@ -62,18 +62,6 @@ void ath9k_hw_txstart(struct ath_hw *ah,
999 }
1000 EXPORT_SYMBOL(ath9k_hw_txstart);
1001
1002 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
1003 -{
1004 - struct ar5416_desc *ads = AR5416DESC(ds);
1005 -
1006 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
1007 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
1008 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
1009 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
1010 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
1011 -}
1012 -EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
1013 -
1014 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
1015 {
1016 u32 npend;
1017 @@ -596,7 +584,7 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a
1018 else
1019 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
1020
1021 - rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
1022 + rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
1023 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
1024
1025 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
1026 --- a/drivers/net/wireless/ath/ath9k/mac.h
1027 +++ b/drivers/net/wireless/ath/ath9k/mac.h
1028 @@ -17,10 +17,6 @@
1029 #ifndef MAC_H
1030 #define MAC_H
1031
1032 -#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
1033 - MS(ads->ds_rxstatus0, AR_RxRate) : \
1034 - (ads->ds_rxstatus3 >> 2) & 0xFF)
1035 -
1036 #define set11nTries(_series, _index) \
1037 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
1038
1039 @@ -263,7 +259,11 @@ struct ath_desc {
1040 #define ATH9K_TXDESC_VMF 0x0100
1041 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
1042 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400
1043 -#define ATH9K_TXDESC_LDPC 0x00010000
1044 +#define ATH9K_TXDESC_LDPC 0x0800
1045 +#define ATH9K_TXDESC_CLRDMASK 0x1000
1046 +
1047 +#define ATH9K_TXDESC_PAPRD 0x70000
1048 +#define ATH9K_TXDESC_PAPRD_S 16
1049
1050 #define ATH9K_RXDESC_INTREQ 0x0020
1051
1052 @@ -659,6 +659,13 @@ struct ath9k_11n_rate_series {
1053 u32 RateFlags;
1054 };
1055
1056 +enum aggr_type {
1057 + AGGR_BUF_NONE,
1058 + AGGR_BUF_FIRST,
1059 + AGGR_BUF_MIDDLE,
1060 + AGGR_BUF_LAST,
1061 +};
1062 +
1063 enum ath9k_key_type {
1064 ATH9K_KEY_TYPE_CLEAR,
1065 ATH9K_KEY_TYPE_WEP,
1066 @@ -666,6 +673,33 @@ enum ath9k_key_type {
1067 ATH9K_KEY_TYPE_TKIP,
1068 };
1069
1070 +struct ath_tx_info {
1071 + u8 qcu;
1072 +
1073 + bool is_first;
1074 + bool is_last;
1075 +
1076 + enum aggr_type aggr;
1077 + u8 ndelim;
1078 + u16 aggr_len;
1079 +
1080 + dma_addr_t link;
1081 + int pkt_len;
1082 + u32 flags;
1083 +
1084 + dma_addr_t buf_addr[4];
1085 + int buf_len[4];
1086 +
1087 + struct ath9k_11n_rate_series rates[4];
1088 + u8 rtscts_rate;
1089 + bool dur_update;
1090 +
1091 + enum ath9k_pkt_type type;
1092 + enum ath9k_key_type keytype;
1093 + u8 keyix;
1094 + u8 txpower;
1095 +};
1096 +
1097 struct ath_hw;
1098 struct ath9k_channel;
1099 enum ath9k_int;
1100 @@ -673,7 +707,6 @@ enum ath9k_int;
1101 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
1102 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
1103 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
1104 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
1105 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
1106 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
1107 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
1108 --- a/drivers/net/wireless/ath/ath9k/main.c
1109 +++ b/drivers/net/wireless/ath/ath9k/main.c
1110 @@ -111,24 +111,29 @@ void ath9k_ps_wakeup(struct ath_softc *s
1111 void ath9k_ps_restore(struct ath_softc *sc)
1112 {
1113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1114 + enum ath9k_power_mode mode;
1115 unsigned long flags;
1116
1117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1118 if (--sc->ps_usecount != 0)
1119 goto unlock;
1120
1121 - spin_lock(&common->cc_lock);
1122 - ath_hw_cycle_counters_update(common);
1123 - spin_unlock(&common->cc_lock);
1124 -
1125 if (sc->ps_idle)
1126 - ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
1127 + mode = ATH9K_PM_FULL_SLEEP;
1128 else if (sc->ps_enabled &&
1129 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1130 PS_WAIT_FOR_CAB |
1131 PS_WAIT_FOR_PSPOLL_DATA |
1132 PS_WAIT_FOR_TX_ACK)))
1133 - ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
1134 + mode = ATH9K_PM_NETWORK_SLEEP;
1135 + else
1136 + goto unlock;
1137 +
1138 + spin_lock(&common->cc_lock);
1139 + ath_hw_cycle_counters_update(common);
1140 + spin_unlock(&common->cc_lock);
1141 +
1142 + ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
1143
1144 unlock:
1145 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1146 @@ -247,8 +252,8 @@ static bool ath_prepare_reset(struct ath
1147
1148 if (!flush) {
1149 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1150 - ath_rx_tasklet(sc, 0, true);
1151 - ath_rx_tasklet(sc, 0, false);
1152 + ath_rx_tasklet(sc, 1, true);
1153 + ath_rx_tasklet(sc, 1, false);
1154 } else {
1155 ath_flushrecv(sc);
1156 }
1157 @@ -669,15 +674,15 @@ void ath9k_tasklet(unsigned long data)
1158 u32 status = sc->intrstatus;
1159 u32 rxmask;
1160
1161 + ath9k_ps_wakeup(sc);
1162 + spin_lock(&sc->sc_pcu_lock);
1163 +
1164 if ((status & ATH9K_INT_FATAL) ||
1165 (status & ATH9K_INT_BB_WATCHDOG)) {
1166 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1167 - return;
1168 + goto out;
1169 }
1170
1171 - ath9k_ps_wakeup(sc);
1172 - spin_lock(&sc->sc_pcu_lock);
1173 -
1174 /*
1175 * Only run the baseband hang check if beacons stop working in AP or
1176 * IBSS mode, because it has a high false positive rate. For station
1177 @@ -725,6 +730,7 @@ void ath9k_tasklet(unsigned long data)
1178 if (status & ATH9K_INT_GENTIMER)
1179 ath_gen_timer_isr(sc->sc_ah);
1180
1181 +out:
1182 /* re-enable hardware interrupt */
1183 ath9k_hw_enable_interrupts(ah);
1184
1185 @@ -2015,6 +2021,7 @@ static void ath9k_config_bss(struct ath_
1186 /* Stop ANI */
1187 sc->sc_flags &= ~SC_OP_ANI_RUN;
1188 del_timer_sync(&common->ani.timer);
1189 + memset(&sc->caldata, 0, sizeof(sc->caldata));
1190 }
1191 }
1192
1193 --- a/drivers/net/wireless/ath/ath9k/pci.c
1194 +++ b/drivers/net/wireless/ath/ath9k/pci.c
1195 @@ -332,16 +332,16 @@ static int ath_pci_resume(struct device
1196 if ((val & 0x0000ff00) != 0)
1197 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1198
1199 + ath9k_ps_wakeup(sc);
1200 /* Enable LED */
1201 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1202 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1203 - ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1204 + ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1205
1206 /*
1207 * Reset key cache to sane defaults (all entries cleared) instead of
1208 * semi-random values after suspend/resume.
1209 */
1210 - ath9k_ps_wakeup(sc);
1211 ath9k_cmn_init_crypto(sc->sc_ah);
1212 ath9k_ps_restore(sc);
1213
1214 --- a/drivers/net/wireless/ath/ath9k/recv.c
1215 +++ b/drivers/net/wireless/ath/ath9k/recv.c
1216 @@ -1839,7 +1839,7 @@ int ath_rx_tasklet(struct ath_softc *sc,
1217 * If we're asked to flush receive queue, directly
1218 * chain it back at the queue without processing it.
1219 */
1220 - if (flush)
1221 + if (sc->sc_flags & SC_OP_RXFLUSH)
1222 goto requeue_drop_frag;
1223
1224 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1225 @@ -1967,7 +1967,8 @@ requeue:
1226 } else {
1227 list_move_tail(&bf->list, &sc->rx.rxbuf);
1228 ath_rx_buf_link(sc, bf);
1229 - ath9k_hw_rxena(ah);
1230 + if (!flush)
1231 + ath9k_hw_rxena(ah);
1232 }
1233 } while (1);
1234
1235 --- a/drivers/net/wireless/ath/ath9k/xmit.c
1236 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
1237 @@ -56,10 +56,9 @@ static void ath_tx_complete_buf(struct a
1238 struct ath_tx_status *ts, int txok, int sendbar);
1239 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1240 struct list_head *head, bool internal);
1241 -static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
1242 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1243 struct ath_tx_status *ts, int nframes, int nbad,
1244 - int txok, bool update_rc);
1245 + int txok);
1246 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
1247 int seqno);
1248 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1249 @@ -263,6 +262,7 @@ static void ath_tx_set_retry(struct ath_
1250 struct sk_buff *skb)
1251 {
1252 struct ath_frame_info *fi = get_frame_info(skb);
1253 + struct ath_buf *bf = fi->bf;
1254 struct ieee80211_hdr *hdr;
1255
1256 TX_STAT_INC(txq->axq_qnum, a_retries);
1257 @@ -271,6 +271,8 @@ static void ath_tx_set_retry(struct ath_
1258
1259 hdr = (struct ieee80211_hdr *)skb->data;
1260 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
1261 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1262 + sizeof(*hdr), DMA_TO_DEVICE);
1263 }
1264
1265 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1266 @@ -390,11 +392,9 @@ static void ath_tx_complete_aggr(struct
1267 while (bf) {
1268 bf_next = bf->bf_next;
1269
1270 - bf->bf_state.bf_type |= BUF_XRETRY;
1271 if (!bf->bf_stale || bf_next != NULL)
1272 list_move_tail(&bf->list, &bf_head);
1273
1274 - ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
1275 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
1276 0, 0);
1277
1278 @@ -470,7 +470,6 @@ static void ath_tx_complete_aggr(struct
1279 clear_filter = true;
1280 txpending = 1;
1281 } else {
1282 - bf->bf_state.bf_type |= BUF_XRETRY;
1283 txfail = 1;
1284 sendbar = 1;
1285 txfail_cnt++;
1286 @@ -497,17 +496,14 @@ static void ath_tx_complete_aggr(struct
1287
1288 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
1289 memcpy(tx_info->control.rates, rates, sizeof(rates));
1290 - ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
1291 + ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
1292 rc_update = false;
1293 - } else {
1294 - ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
1295 }
1296
1297 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
1298 !txfail, sendbar);
1299 } else {
1300 /* retry the un-acked ones */
1301 - ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
1302 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
1303 if (bf->bf_next == NULL && bf_last->bf_stale) {
1304 struct ath_buf *tbf;
1305 @@ -523,26 +519,13 @@ static void ath_tx_complete_aggr(struct
1306 ath_tx_update_baw(sc, tid, seqno);
1307 spin_unlock_bh(&txq->axq_lock);
1308
1309 - bf->bf_state.bf_type |=
1310 - BUF_XRETRY;
1311 - ath_tx_rc_status(sc, bf, ts, nframes,
1312 - nbad, 0, false);
1313 ath_tx_complete_buf(sc, bf, txq,
1314 &bf_head,
1315 - ts, 0, 0);
1316 + ts, 0, 1);
1317 break;
1318 }
1319
1320 - ath9k_hw_cleartxdesc(sc->sc_ah,
1321 - tbf->bf_desc);
1322 fi->bf = tbf;
1323 - } else {
1324 - /*
1325 - * Clear descriptor status words for
1326 - * software retry
1327 - */
1328 - ath9k_hw_cleartxdesc(sc->sc_ah,
1329 - bf->bf_desc);
1330 }
1331 }
1332
1333 @@ -778,7 +761,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
1334 if (!bf)
1335 continue;
1336
1337 - bf->bf_state.bf_type |= BUF_AMPDU;
1338 + bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
1339 seqno = bf->bf_state.seqno;
1340 if (!bf_first)
1341 bf_first = bf;
1342 @@ -805,8 +788,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
1343 }
1344
1345 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1346 - if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1347 - !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
1348 + if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
1349 break;
1350
1351 /* do not exceed subframe limit */
1352 @@ -828,20 +810,17 @@ static enum ATH_AGGR_STATUS ath_tx_form_
1353
1354 nframes++;
1355 bf->bf_next = NULL;
1356 - ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
1357
1358 /* link buffers of this frame to the aggregate */
1359 if (!fi->retries)
1360 ath_tx_addto_baw(sc, tid, seqno);
1361 - ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
1362 + bf->bf_state.ndelim = ndelim;
1363
1364 __skb_unlink(skb, &tid->buf_q);
1365 list_add_tail(&bf->list, bf_q);
1366 - if (bf_prev) {
1367 + if (bf_prev)
1368 bf_prev->bf_next = bf;
1369 - ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
1370 - bf->bf_daddr);
1371 - }
1372 +
1373 bf_prev = bf;
1374
1375 } while (!skb_queue_empty(&tid->buf_q));
1376 @@ -852,12 +831,245 @@ static enum ATH_AGGR_STATUS ath_tx_form_
1377 #undef PADBYTES
1378 }
1379
1380 +/*
1381 + * rix - rate index
1382 + * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1383 + * width - 0 for 20 MHz, 1 for 40 MHz
1384 + * half_gi - to use 4us v/s 3.6 us for symbol time
1385 + */
1386 +static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1387 + int width, int half_gi, bool shortPreamble)
1388 +{
1389 + u32 nbits, nsymbits, duration, nsymbols;
1390 + int streams;
1391 +
1392 + /* find number of symbols: PLCP + data */
1393 + streams = HT_RC_2_STREAMS(rix);
1394 + nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1395 + nsymbits = bits_per_symbol[rix % 8][width] * streams;
1396 + nsymbols = (nbits + nsymbits - 1) / nsymbits;
1397 +
1398 + if (!half_gi)
1399 + duration = SYMBOL_TIME(nsymbols);
1400 + else
1401 + duration = SYMBOL_TIME_HALFGI(nsymbols);
1402 +
1403 + /* addup duration for legacy/ht training and signal fields */
1404 + duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1405 +
1406 + return duration;
1407 +}
1408 +
1409 +static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1410 + struct ath_tx_info *info, int len)
1411 +{
1412 + struct ath_hw *ah = sc->sc_ah;
1413 + struct sk_buff *skb;
1414 + struct ieee80211_tx_info *tx_info;
1415 + struct ieee80211_tx_rate *rates;
1416 + const struct ieee80211_rate *rate;
1417 + struct ieee80211_hdr *hdr;
1418 + int i;
1419 + u8 rix = 0;
1420 +
1421 + skb = bf->bf_mpdu;
1422 + tx_info = IEEE80211_SKB_CB(skb);
1423 + rates = tx_info->control.rates;
1424 + hdr = (struct ieee80211_hdr *)skb->data;
1425 +
1426 + /* set dur_update_en for l-sig computation except for PS-Poll frames */
1427 + info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1428 +
1429 + /*
1430 + * We check if Short Preamble is needed for the CTS rate by
1431 + * checking the BSS's global flag.
1432 + * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1433 + */
1434 + rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1435 + info->rtscts_rate = rate->hw_value;
1436 + if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1437 + info->rtscts_rate |= rate->hw_value_short;
1438 +
1439 + for (i = 0; i < 4; i++) {
1440 + bool is_40, is_sgi, is_sp;
1441 + int phy;
1442 +
1443 + if (!rates[i].count || (rates[i].idx < 0))
1444 + continue;
1445 +
1446 + rix = rates[i].idx;
1447 + info->rates[i].Tries = rates[i].count;
1448 +
1449 + if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1450 + info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1451 + info->flags |= ATH9K_TXDESC_RTSENA;
1452 + } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1453 + info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1454 + info->flags |= ATH9K_TXDESC_CTSENA;
1455 + }
1456 +
1457 + if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1458 + info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1459 + if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1460 + info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1461 +
1462 + is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1463 + is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1464 + is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1465 +
1466 + if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1467 + /* MCS rates */
1468 + info->rates[i].Rate = rix | 0x80;
1469 + info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1470 + ah->txchainmask, info->rates[i].Rate);
1471 + info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1472 + is_40, is_sgi, is_sp);
1473 + if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1474 + info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1475 + continue;
1476 + }
1477 +
1478 + /* legacy rates */
1479 + if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1480 + !(rate->flags & IEEE80211_RATE_ERP_G))
1481 + phy = WLAN_RC_PHY_CCK;
1482 + else
1483 + phy = WLAN_RC_PHY_OFDM;
1484 +
1485 + rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1486 + info->rates[i].Rate = rate->hw_value;
1487 + if (rate->hw_value_short) {
1488 + if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1489 + info->rates[i].Rate |= rate->hw_value_short;
1490 + } else {
1491 + is_sp = false;
1492 + }
1493 +
1494 + if (bf->bf_state.bfs_paprd)
1495 + info->rates[i].ChSel = ah->txchainmask;
1496 + else
1497 + info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1498 + ah->txchainmask, info->rates[i].Rate);
1499 +
1500 + info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1501 + phy, rate->bitrate * 100, len, rix, is_sp);
1502 + }
1503 +
1504 + /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1505 + if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1506 + info->flags &= ~ATH9K_TXDESC_RTSENA;
1507 +
1508 + /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1509 + if (info->flags & ATH9K_TXDESC_RTSENA)
1510 + info->flags &= ~ATH9K_TXDESC_CTSENA;
1511 +}
1512 +
1513 +static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1514 +{
1515 + struct ieee80211_hdr *hdr;
1516 + enum ath9k_pkt_type htype;
1517 + __le16 fc;
1518 +
1519 + hdr = (struct ieee80211_hdr *)skb->data;
1520 + fc = hdr->frame_control;
1521 +
1522 + if (ieee80211_is_beacon(fc))
1523 + htype = ATH9K_PKT_TYPE_BEACON;
1524 + else if (ieee80211_is_probe_resp(fc))
1525 + htype = ATH9K_PKT_TYPE_PROBE_RESP;
1526 + else if (ieee80211_is_atim(fc))
1527 + htype = ATH9K_PKT_TYPE_ATIM;
1528 + else if (ieee80211_is_pspoll(fc))
1529 + htype = ATH9K_PKT_TYPE_PSPOLL;
1530 + else
1531 + htype = ATH9K_PKT_TYPE_NORMAL;
1532 +
1533 + return htype;
1534 +}
1535 +
1536 +static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1537 + struct ath_txq *txq, int len)
1538 +{
1539 + struct ath_hw *ah = sc->sc_ah;
1540 + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1541 + struct ath_buf *bf_first = bf;
1542 + struct ath_tx_info info;
1543 + bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1544 +
1545 + memset(&info, 0, sizeof(info));
1546 + info.is_first = true;
1547 + info.is_last = true;
1548 + info.txpower = MAX_RATE_POWER;
1549 + info.qcu = txq->axq_qnum;
1550 +
1551 + info.flags = ATH9K_TXDESC_INTREQ;
1552 + if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1553 + info.flags |= ATH9K_TXDESC_NOACK;
1554 + if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1555 + info.flags |= ATH9K_TXDESC_LDPC;
1556 +
1557 + ath_buf_set_rate(sc, bf, &info, len);
1558 +
1559 + if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1560 + info.flags |= ATH9K_TXDESC_CLRDMASK;
1561 +
1562 + if (bf->bf_state.bfs_paprd)
1563 + info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1564 +
1565 +
1566 + while (bf) {
1567 + struct sk_buff *skb = bf->bf_mpdu;
1568 + struct ath_frame_info *fi = get_frame_info(skb);
1569 + struct ieee80211_hdr *hdr;
1570 + int padpos, padsize;
1571 +
1572 + info.type = get_hw_packet_type(skb);
1573 + if (bf->bf_next)
1574 + info.link = bf->bf_next->bf_daddr;
1575 + else
1576 + info.link = 0;
1577 +
1578 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1579 + hdr = (struct ieee80211_hdr *)skb->data;
1580 + padpos = ath9k_cmn_padpos(hdr->frame_control);
1581 + padsize = padpos & 3;
1582 +
1583 + info.buf_addr[0] = bf->bf_buf_addr;
1584 + info.buf_len[0] = padpos + padsize;
1585 + info.buf_addr[1] = info.buf_addr[0] + padpos;
1586 + info.buf_len[1] = skb->len - padpos;
1587 + } else {
1588 + info.buf_addr[0] = bf->bf_buf_addr;
1589 + info.buf_len[0] = skb->len;
1590 + }
1591 +
1592 + info.pkt_len = fi->framelen;
1593 + info.keyix = fi->keyix;
1594 + info.keytype = fi->keytype;
1595 +
1596 + if (aggr) {
1597 + if (bf == bf_first)
1598 + info.aggr = AGGR_BUF_FIRST;
1599 + else if (!bf->bf_next)
1600 + info.aggr = AGGR_BUF_LAST;
1601 + else
1602 + info.aggr = AGGR_BUF_MIDDLE;
1603 +
1604 + info.ndelim = bf->bf_state.ndelim;
1605 + info.aggr_len = len;
1606 + }
1607 +
1608 + ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1609 + bf = bf->bf_next;
1610 + }
1611 +}
1612 +
1613 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1614 struct ath_atx_tid *tid)
1615 {
1616 struct ath_buf *bf;
1617 enum ATH_AGGR_STATUS status;
1618 - struct ath_frame_info *fi;
1619 + struct ieee80211_tx_info *tx_info;
1620 struct list_head bf_q;
1621 int aggr_len;
1622
1623 @@ -878,34 +1090,25 @@ static void ath_tx_sched_aggr(struct ath
1624
1625 bf = list_first_entry(&bf_q, struct ath_buf, list);
1626 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1627 + tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1628
1629 if (tid->ac->clear_ps_filter) {
1630 tid->ac->clear_ps_filter = false;
1631 - ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1632 + tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1633 + } else {
1634 + tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1635 }
1636
1637 /* if only one frame, send as non-aggregate */
1638 if (bf == bf->bf_lastbf) {
1639 - fi = get_frame_info(bf->bf_mpdu);
1640 -
1641 - bf->bf_state.bf_type &= ~BUF_AGGR;
1642 - ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
1643 - ath_buf_set_rate(sc, bf, fi->framelen);
1644 - ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1645 - continue;
1646 + aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1647 + bf->bf_state.bf_type = BUF_AMPDU;
1648 + } else {
1649 + TX_STAT_INC(txq->axq_qnum, a_aggr);
1650 }
1651
1652 - /* setup first desc of aggregate */
1653 - bf->bf_state.bf_type |= BUF_AGGR;
1654 - ath_buf_set_rate(sc, bf, aggr_len);
1655 - ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
1656 -
1657 - /* anchor last desc of aggregate */
1658 - ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
1659 -
1660 + ath_tx_fill_desc(sc, bf, txq, aggr_len);
1661 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1662 - TX_STAT_INC(txq->axq_qnum, a_aggr);
1663 -
1664 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1665 status != ATH_AGGR_BAW_CLOSED);
1666 }
1667 @@ -1483,7 +1686,7 @@ static void ath_tx_send_ampdu(struct ath
1668 if (!bf)
1669 return;
1670
1671 - bf->bf_state.bf_type |= BUF_AMPDU;
1672 + bf->bf_state.bf_type = BUF_AMPDU;
1673 INIT_LIST_HEAD(&bf_head);
1674 list_add(&bf->list, &bf_head);
1675
1676 @@ -1493,7 +1696,7 @@ static void ath_tx_send_ampdu(struct ath
1677 /* Queue to h/w without aggregation */
1678 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1679 bf->bf_lastbf = bf;
1680 - ath_buf_set_rate(sc, bf, fi->framelen);
1681 + ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1682 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1683 }
1684
1685 @@ -1513,41 +1716,18 @@ static void ath_tx_send_normal(struct at
1686
1687 INIT_LIST_HEAD(&bf_head);
1688 list_add_tail(&bf->list, &bf_head);
1689 - bf->bf_state.bf_type &= ~BUF_AMPDU;
1690 + bf->bf_state.bf_type = 0;
1691
1692 /* update starting sequence number for subsequent ADDBA request */
1693 if (tid)
1694 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1695
1696 bf->bf_lastbf = bf;
1697 - ath_buf_set_rate(sc, bf, fi->framelen);
1698 + ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1699 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1700 TX_STAT_INC(txq->axq_qnum, queued);
1701 }
1702
1703 -static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1704 -{
1705 - struct ieee80211_hdr *hdr;
1706 - enum ath9k_pkt_type htype;
1707 - __le16 fc;
1708 -
1709 - hdr = (struct ieee80211_hdr *)skb->data;
1710 - fc = hdr->frame_control;
1711 -
1712 - if (ieee80211_is_beacon(fc))
1713 - htype = ATH9K_PKT_TYPE_BEACON;
1714 - else if (ieee80211_is_probe_resp(fc))
1715 - htype = ATH9K_PKT_TYPE_PROBE_RESP;
1716 - else if (ieee80211_is_atim(fc))
1717 - htype = ATH9K_PKT_TYPE_ATIM;
1718 - else if (ieee80211_is_pspoll(fc))
1719 - htype = ATH9K_PKT_TYPE_PSPOLL;
1720 - else
1721 - htype = ATH9K_PKT_TYPE_NORMAL;
1722 -
1723 - return htype;
1724 -}
1725 -
1726 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1727 int framelen)
1728 {
1729 @@ -1575,51 +1755,6 @@ static void setup_frame_info(struct ieee
1730 fi->framelen = framelen;
1731 }
1732
1733 -static int setup_tx_flags(struct sk_buff *skb)
1734 -{
1735 - struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1736 - int flags = 0;
1737 -
1738 - flags |= ATH9K_TXDESC_INTREQ;
1739 -
1740 - if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1741 - flags |= ATH9K_TXDESC_NOACK;
1742 -
1743 - if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1744 - flags |= ATH9K_TXDESC_LDPC;
1745 -
1746 - return flags;
1747 -}
1748 -
1749 -/*
1750 - * rix - rate index
1751 - * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1752 - * width - 0 for 20 MHz, 1 for 40 MHz
1753 - * half_gi - to use 4us v/s 3.6 us for symbol time
1754 - */
1755 -static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1756 - int width, int half_gi, bool shortPreamble)
1757 -{
1758 - u32 nbits, nsymbits, duration, nsymbols;
1759 - int streams;
1760 -
1761 - /* find number of symbols: PLCP + data */
1762 - streams = HT_RC_2_STREAMS(rix);
1763 - nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1764 - nsymbits = bits_per_symbol[rix % 8][width] * streams;
1765 - nsymbols = (nbits + nsymbits - 1) / nsymbits;
1766 -
1767 - if (!half_gi)
1768 - duration = SYMBOL_TIME(nsymbols);
1769 - else
1770 - duration = SYMBOL_TIME_HALFGI(nsymbols);
1771 -
1772 - /* addup duration for legacy/ht training and signal fields */
1773 - duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1774 -
1775 - return duration;
1776 -}
1777 -
1778 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1779 {
1780 struct ath_hw *ah = sc->sc_ah;
1781 @@ -1632,118 +1767,6 @@ u8 ath_txchainmask_reduction(struct ath_
1782 return chainmask;
1783 }
1784
1785 -static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1786 -{
1787 - struct ath_hw *ah = sc->sc_ah;
1788 - struct ath9k_11n_rate_series series[4];
1789 - struct sk_buff *skb;
1790 - struct ieee80211_tx_info *tx_info;
1791 - struct ieee80211_tx_rate *rates;
1792 - const struct ieee80211_rate *rate;
1793 - struct ieee80211_hdr *hdr;
1794 - int i, flags = 0;
1795 - u8 rix = 0, ctsrate = 0;
1796 - bool is_pspoll;
1797 -
1798 - memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1799 -
1800 - skb = bf->bf_mpdu;
1801 - tx_info = IEEE80211_SKB_CB(skb);
1802 - rates = tx_info->control.rates;
1803 - hdr = (struct ieee80211_hdr *)skb->data;
1804 - is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1805 -
1806 - /*
1807 - * We check if Short Preamble is needed for the CTS rate by
1808 - * checking the BSS's global flag.
1809 - * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1810 - */
1811 - rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1812 - ctsrate = rate->hw_value;
1813 - if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1814 - ctsrate |= rate->hw_value_short;
1815 -
1816 - for (i = 0; i < 4; i++) {
1817 - bool is_40, is_sgi, is_sp;
1818 - int phy;
1819 -
1820 - if (!rates[i].count || (rates[i].idx < 0))
1821 - continue;
1822 -
1823 - rix = rates[i].idx;
1824 - series[i].Tries = rates[i].count;
1825 -
1826 - if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1827 - series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1828 - flags |= ATH9K_TXDESC_RTSENA;
1829 - } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1830 - series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1831 - flags |= ATH9K_TXDESC_CTSENA;
1832 - }
1833 -
1834 - if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1835 - series[i].RateFlags |= ATH9K_RATESERIES_2040;
1836 - if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1837 - series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1838 -
1839 - is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1840 - is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1841 - is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1842 -
1843 - if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1844 - /* MCS rates */
1845 - series[i].Rate = rix | 0x80;
1846 - series[i].ChSel = ath_txchainmask_reduction(sc,
1847 - ah->txchainmask, series[i].Rate);
1848 - series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1849 - is_40, is_sgi, is_sp);
1850 - if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1851 - series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1852 - continue;
1853 - }
1854 -
1855 - /* legacy rates */
1856 - if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1857 - !(rate->flags & IEEE80211_RATE_ERP_G))
1858 - phy = WLAN_RC_PHY_CCK;
1859 - else
1860 - phy = WLAN_RC_PHY_OFDM;
1861 -
1862 - rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1863 - series[i].Rate = rate->hw_value;
1864 - if (rate->hw_value_short) {
1865 - if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1866 - series[i].Rate |= rate->hw_value_short;
1867 - } else {
1868 - is_sp = false;
1869 - }
1870 -
1871 - if (bf->bf_state.bfs_paprd)
1872 - series[i].ChSel = ah->txchainmask;
1873 - else
1874 - series[i].ChSel = ath_txchainmask_reduction(sc,
1875 - ah->txchainmask, series[i].Rate);
1876 -
1877 - series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1878 - phy, rate->bitrate * 100, len, rix, is_sp);
1879 - }
1880 -
1881 - /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1882 - if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1883 - flags &= ~ATH9K_TXDESC_RTSENA;
1884 -
1885 - /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1886 - if (flags & ATH9K_TXDESC_RTSENA)
1887 - flags &= ~ATH9K_TXDESC_CTSENA;
1888 -
1889 - /* set dur_update_en for l-sig computation except for PS-Poll frames */
1890 - ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1891 - bf->bf_lastbf->bf_desc,
1892 - !is_pspoll, ctsrate,
1893 - 0, series, 4, flags);
1894 -
1895 -}
1896 -
1897 /*
1898 * Assign a descriptor (and sequence number if necessary,
1899 * and map buffer for DMA. Frees skb on error
1900 @@ -1753,13 +1776,10 @@ static struct ath_buf *ath_tx_setup_buff
1901 struct ath_atx_tid *tid,
1902 struct sk_buff *skb)
1903 {
1904 - struct ath_hw *ah = sc->sc_ah;
1905 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1906 struct ath_frame_info *fi = get_frame_info(skb);
1907 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1908 struct ath_buf *bf;
1909 - struct ath_desc *ds;
1910 - int frm_type;
1911 u16 seqno;
1912
1913 bf = ath_tx_get_buffer(sc);
1914 @@ -1777,7 +1797,6 @@ static struct ath_buf *ath_tx_setup_buff
1915 bf->bf_state.seqno = seqno;
1916 }
1917
1918 - bf->bf_flags = setup_tx_flags(skb);
1919 bf->bf_mpdu = skb;
1920
1921 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1922 @@ -1791,22 +1810,6 @@ static struct ath_buf *ath_tx_setup_buff
1923 goto error;
1924 }
1925
1926 - frm_type = get_hw_packet_type(skb);
1927 -
1928 - ds = bf->bf_desc;
1929 - ath9k_hw_set_desc_link(ah, ds, 0);
1930 -
1931 - ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1932 - fi->keyix, fi->keytype, bf->bf_flags);
1933 -
1934 - ath9k_hw_filltxdesc(ah, ds,
1935 - skb->len, /* segment length */
1936 - true, /* first segment */
1937 - true, /* last segment */
1938 - ds, /* first descriptor */
1939 - bf->bf_buf_addr,
1940 - txq->axq_qnum);
1941 -
1942 fi->bf = bf;
1943
1944 return bf;
1945 @@ -1849,16 +1852,9 @@ static void ath_tx_start_dma(struct ath_
1946
1947 bf->bf_state.bfs_paprd = txctl->paprd;
1948
1949 - if (bf->bf_state.bfs_paprd)
1950 - ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1951 - bf->bf_state.bfs_paprd);
1952 -
1953 if (txctl->paprd)
1954 bf->bf_state.bfs_paprd_timestamp = jiffies;
1955
1956 - if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1957 - ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1958 -
1959 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1960 }
1961
1962 @@ -1899,15 +1895,18 @@ int ath_tx_start(struct ieee80211_hw *hw
1963 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1964 }
1965
1966 - /* Add the padding after the header if this is not already done */
1967 - padpos = ath9k_cmn_padpos(hdr->frame_control);
1968 - padsize = padpos & 3;
1969 - if (padsize && skb->len > padpos) {
1970 - if (skb_headroom(skb) < padsize)
1971 - return -ENOMEM;
1972 -
1973 - skb_push(skb, padsize);
1974 - memmove(skb->data, skb->data + padsize, padpos);
1975 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
1976 + /* Add the padding after the header if this is not already done */
1977 + padpos = ath9k_cmn_padpos(hdr->frame_control);
1978 + padsize = padpos & 3;
1979 + if (padsize && skb->len > padpos) {
1980 + if (skb_headroom(skb) < padsize)
1981 + return -ENOMEM;
1982 +
1983 + skb_push(skb, padsize);
1984 + memmove(skb->data, skb->data + padsize, padpos);
1985 + hdr = (struct ieee80211_hdr *) skb->data;
1986 + }
1987 }
1988
1989 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1990 @@ -1953,20 +1952,21 @@ static void ath_tx_complete(struct ath_s
1991 if (tx_flags & ATH_TX_BAR)
1992 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1993
1994 - if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1995 + if (!(tx_flags & ATH_TX_ERROR))
1996 /* Frame was ACKed */
1997 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1998 - }
1999
2000 - padpos = ath9k_cmn_padpos(hdr->frame_control);
2001 - padsize = padpos & 3;
2002 - if (padsize && skb->len>padpos+padsize) {
2003 - /*
2004 - * Remove MAC header padding before giving the frame back to
2005 - * mac80211.
2006 - */
2007 - memmove(skb->data + padsize, skb->data, padpos);
2008 - skb_pull(skb, padsize);
2009 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
2010 + padpos = ath9k_cmn_padpos(hdr->frame_control);
2011 + padsize = padpos & 3;
2012 + if (padsize && skb->len>padpos+padsize) {
2013 + /*
2014 + * Remove MAC header padding before giving the frame back to
2015 + * mac80211.
2016 + */
2017 + memmove(skb->data + padsize, skb->data, padpos);
2018 + skb_pull(skb, padsize);
2019 + }
2020 }
2021
2022 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
2023 @@ -2000,18 +2000,18 @@ static void ath_tx_complete_buf(struct a
2024 struct ath_tx_status *ts, int txok, int sendbar)
2025 {
2026 struct sk_buff *skb = bf->bf_mpdu;
2027 + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2028 unsigned long flags;
2029 int tx_flags = 0;
2030
2031 if (sendbar)
2032 tx_flags = ATH_TX_BAR;
2033
2034 - if (!txok) {
2035 + if (!txok)
2036 tx_flags |= ATH_TX_ERROR;
2037
2038 - if (bf_isxretried(bf))
2039 - tx_flags |= ATH_TX_XRETRY;
2040 - }
2041 + if (ts->ts_status & ATH9K_TXERR_FILT)
2042 + tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2043
2044 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2045 bf->bf_buf_addr = 0;
2046 @@ -2024,7 +2024,7 @@ static void ath_tx_complete_buf(struct a
2047 else
2048 complete(&sc->paprd_complete);
2049 } else {
2050 - ath_debug_stat_tx(sc, bf, ts, txq);
2051 + ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2052 ath_tx_complete(sc, skb, tx_flags, txq);
2053 }
2054 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2055 @@ -2042,7 +2042,7 @@ static void ath_tx_complete_buf(struct a
2056
2057 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2058 struct ath_tx_status *ts, int nframes, int nbad,
2059 - int txok, bool update_rc)
2060 + int txok)
2061 {
2062 struct sk_buff *skb = bf->bf_mpdu;
2063 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2064 @@ -2057,9 +2057,7 @@ static void ath_tx_rc_status(struct ath_
2065 tx_rateindex = ts->ts_rateindex;
2066 WARN_ON(tx_rateindex >= hw->max_rates);
2067
2068 - if (ts->ts_status & ATH9K_TXERR_FILT)
2069 - tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2070 - if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
2071 + if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2072 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2073
2074 BUG_ON(nbad > nframes);
2075 @@ -2069,7 +2067,7 @@ static void ath_tx_rc_status(struct ath_
2076 }
2077
2078 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2079 - (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2080 + (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2081 /*
2082 * If an underrun error is seen assume it as an excessive
2083 * retry only if max frame trigger level has been reached
2084 @@ -2082,9 +2080,9 @@ static void ath_tx_rc_status(struct ath_
2085 * successfully by eventually preferring slower rates.
2086 * This itself should also alleviate congestion on the bus.
2087 */
2088 - if (ieee80211_is_data(hdr->frame_control) &&
2089 - (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2090 - ATH9K_TX_DELIM_UNDERRUN)) &&
2091 + if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2092 + ATH9K_TX_DELIM_UNDERRUN)) &&
2093 + ieee80211_is_data(hdr->frame_control) &&
2094 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2095 tx_info->status.rates[tx_rateindex].count =
2096 hw->max_rate_tries;
2097 @@ -2115,13 +2113,7 @@ static void ath_tx_process_buffer(struct
2098 spin_unlock_bh(&txq->axq_lock);
2099
2100 if (!bf_isampdu(bf)) {
2101 - /*
2102 - * This frame is sent out as a single frame.
2103 - * Use hardware retry status for this frame.
2104 - */
2105 - if (ts->ts_status & ATH9K_TXERR_XRETRY)
2106 - bf->bf_state.bf_type |= BUF_XRETRY;
2107 - ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2108 + ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2109 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2110 } else
2111 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2112 --- a/net/mac80211/agg-rx.c
2113 +++ b/net/mac80211/agg-rx.c
2114 @@ -180,6 +180,8 @@ static void ieee80211_send_addba_resp(st
2115 memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN);
2116 else if (sdata->vif.type == NL80211_IFTYPE_STATION)
2117 memcpy(mgmt->bssid, sdata->u.mgd.bssid, ETH_ALEN);
2118 + else if (sdata->vif.type == NL80211_IFTYPE_WDS)
2119 + memcpy(mgmt->bssid, da, ETH_ALEN);
2120
2121 mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
2122 IEEE80211_STYPE_ACTION);
2123 --- a/net/mac80211/agg-tx.c
2124 +++ b/net/mac80211/agg-tx.c
2125 @@ -77,7 +77,8 @@ static void ieee80211_send_addba_request
2126 memcpy(mgmt->da, da, ETH_ALEN);
2127 memcpy(mgmt->sa, sdata->vif.addr, ETH_ALEN);
2128 if (sdata->vif.type == NL80211_IFTYPE_AP ||
2129 - sdata->vif.type == NL80211_IFTYPE_AP_VLAN)
2130 + sdata->vif.type == NL80211_IFTYPE_AP_VLAN ||
2131 + sdata->vif.type == NL80211_IFTYPE_WDS)
2132 memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN);
2133 else if (sdata->vif.type == NL80211_IFTYPE_STATION)
2134 memcpy(mgmt->bssid, sdata->u.mgd.bssid, ETH_ALEN);
2135 @@ -397,7 +398,8 @@ int ieee80211_start_tx_ba_session(struct
2136 */
2137 if (sdata->vif.type != NL80211_IFTYPE_STATION &&
2138 sdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
2139 - sdata->vif.type != NL80211_IFTYPE_AP)
2140 + sdata->vif.type != NL80211_IFTYPE_AP &&
2141 + sdata->vif.type != NL80211_IFTYPE_WDS)
2142 return -EINVAL;
2143
2144 if (test_sta_flags(sta, WLAN_STA_BLOCK_BA)) {
2145 --- a/net/mac80211/debugfs_sta.c
2146 +++ b/net/mac80211/debugfs_sta.c
2147 @@ -59,7 +59,7 @@ static ssize_t sta_flags_read(struct fil
2148 char buf[100];
2149 struct sta_info *sta = file->private_data;
2150 u32 staflags = get_sta_flags(sta);
2151 - int res = scnprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s",
2152 + int res = scnprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s",
2153 staflags & WLAN_STA_AUTH ? "AUTH\n" : "",
2154 staflags & WLAN_STA_ASSOC ? "ASSOC\n" : "",
2155 staflags & WLAN_STA_PS_STA ? "PS (sta)\n" : "",
2156 @@ -67,7 +67,6 @@ static ssize_t sta_flags_read(struct fil
2157 staflags & WLAN_STA_AUTHORIZED ? "AUTHORIZED\n" : "",
2158 staflags & WLAN_STA_SHORT_PREAMBLE ? "SHORT PREAMBLE\n" : "",
2159 staflags & WLAN_STA_WME ? "WME\n" : "",
2160 - staflags & WLAN_STA_WDS ? "WDS\n" : "",
2161 staflags & WLAN_STA_MFP ? "MFP\n" : "");
2162 return simple_read_from_buffer(userbuf, count, ppos, buf, res);
2163 }
2164 --- a/net/mac80211/iface.c
2165 +++ b/net/mac80211/iface.c
2166 @@ -178,7 +178,6 @@ static int ieee80211_do_open(struct net_
2167 {
2168 struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev);
2169 struct ieee80211_local *local = sdata->local;
2170 - struct sta_info *sta;
2171 u32 changed = 0;
2172 int res;
2173 u32 hw_reconf_flags = 0;
2174 @@ -290,27 +289,6 @@ static int ieee80211_do_open(struct net_
2175
2176 set_bit(SDATA_STATE_RUNNING, &sdata->state);
2177
2178 - if (sdata->vif.type == NL80211_IFTYPE_WDS) {
2179 - /* Create STA entry for the WDS peer */
2180 - sta = sta_info_alloc(sdata, sdata->u.wds.remote_addr,
2181 - GFP_KERNEL);
2182 - if (!sta) {
2183 - res = -ENOMEM;
2184 - goto err_del_interface;
2185 - }
2186 -
2187 - /* no locking required since STA is not live yet */
2188 - sta->flags |= WLAN_STA_AUTHORIZED;
2189 -
2190 - res = sta_info_insert(sta);
2191 - if (res) {
2192 - /* STA has been freed */
2193 - goto err_del_interface;
2194 - }
2195 -
2196 - rate_control_rate_init(sta);
2197 - }
2198 -
2199 /*
2200 * set_multicast_list will be invoked by the networking core
2201 * which will check whether any increments here were done in
2202 @@ -344,8 +322,7 @@ static int ieee80211_do_open(struct net_
2203 netif_tx_start_all_queues(dev);
2204
2205 return 0;
2206 - err_del_interface:
2207 - drv_remove_interface(local, &sdata->vif);
2208 +
2209 err_stop:
2210 if (!local->open_count)
2211 drv_stop(local);
2212 @@ -718,6 +695,70 @@ static void ieee80211_if_setup(struct ne
2213 dev->destructor = free_netdev;
2214 }
2215
2216 +static void ieee80211_wds_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata,
2217 + struct sk_buff *skb)
2218 +{
2219 + struct ieee80211_local *local = sdata->local;
2220 + struct ieee80211_rx_status *rx_status;
2221 + struct ieee802_11_elems elems;
2222 + struct ieee80211_mgmt *mgmt;
2223 + struct sta_info *sta;
2224 + size_t baselen;
2225 + u32 rates = 0;
2226 + u16 stype;
2227 + bool new = false;
2228 + enum ieee80211_band band = local->hw.conf.channel->band;
2229 + struct ieee80211_supported_band *sband = local->hw.wiphy->bands[band];
2230 +
2231 + rx_status = IEEE80211_SKB_RXCB(skb);
2232 + mgmt = (struct ieee80211_mgmt *) skb->data;
2233 + stype = le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE;
2234 +
2235 + if (stype != IEEE80211_STYPE_BEACON)
2236 + return;
2237 +
2238 + baselen = (u8 *) mgmt->u.probe_resp.variable - (u8 *) mgmt;
2239 + if (baselen > skb->len)
2240 + return;
2241 +
2242 + ieee802_11_parse_elems(mgmt->u.probe_resp.variable,
2243 + skb->len - baselen, &elems);
2244 +
2245 + rates = ieee80211_sta_get_rates(local, &elems, band);
2246 +
2247 + rcu_read_lock();
2248 +
2249 + sta = sta_info_get(sdata, sdata->u.wds.remote_addr);
2250 +
2251 + if (!sta) {
2252 + rcu_read_unlock();
2253 + sta = sta_info_alloc(sdata, sdata->u.wds.remote_addr,
2254 + GFP_KERNEL);
2255 + if (!sta)
2256 + return;
2257 +
2258 + new = true;
2259 + }
2260 +
2261 + sta->last_rx = jiffies;
2262 + sta->sta.supp_rates[local->hw.conf.channel->band] = rates;
2263 +
2264 + if (elems.ht_cap_elem)
2265 + ieee80211_ht_cap_ie_to_sta_ht_cap(sband,
2266 + elems.ht_cap_elem, &sta->sta.ht_cap);
2267 +
2268 + if (elems.wmm_param)
2269 + set_sta_flags(sta, WLAN_STA_WME);
2270 +
2271 + if (new) {
2272 + sta->flags = WLAN_STA_AUTHORIZED;
2273 + rate_control_rate_init(sta);
2274 + sta_info_insert_rcu(sta);
2275 + }
2276 +
2277 + rcu_read_unlock();
2278 +}
2279 +
2280 static void ieee80211_iface_work(struct work_struct *work)
2281 {
2282 struct ieee80211_sub_if_data *sdata =
2283 @@ -822,6 +863,9 @@ static void ieee80211_iface_work(struct
2284 break;
2285 ieee80211_mesh_rx_queued_mgmt(sdata, skb);
2286 break;
2287 + case NL80211_IFTYPE_WDS:
2288 + ieee80211_wds_rx_queued_mgmt(sdata, skb);
2289 + break;
2290 default:
2291 WARN(1, "frame for unexpected interface type");
2292 break;
2293 --- a/net/mac80211/rx.c
2294 +++ b/net/mac80211/rx.c
2295 @@ -2163,7 +2163,8 @@ ieee80211_rx_h_action(struct ieee80211_r
2296 */
2297 if (sdata->vif.type != NL80211_IFTYPE_STATION &&
2298 sdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
2299 - sdata->vif.type != NL80211_IFTYPE_AP)
2300 + sdata->vif.type != NL80211_IFTYPE_AP &&
2301 + sdata->vif.type != NL80211_IFTYPE_WDS)
2302 break;
2303
2304 /* verify action_code is present */
2305 @@ -2378,13 +2379,14 @@ ieee80211_rx_h_mgmt(struct ieee80211_rx_
2306
2307 if (!ieee80211_vif_is_mesh(&sdata->vif) &&
2308 sdata->vif.type != NL80211_IFTYPE_ADHOC &&
2309 - sdata->vif.type != NL80211_IFTYPE_STATION)
2310 + sdata->vif.type != NL80211_IFTYPE_STATION &&
2311 + sdata->vif.type != NL80211_IFTYPE_WDS)
2312 return RX_DROP_MONITOR;
2313
2314 switch (stype) {
2315 case cpu_to_le16(IEEE80211_STYPE_BEACON):
2316 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
2317 - /* process for all: mesh, mlme, ibss */
2318 + /* process for all: mesh, mlme, ibss, wds */
2319 break;
2320 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
2321 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
2322 @@ -2727,10 +2729,16 @@ static int prepare_for_handlers(struct i
2323 }
2324 break;
2325 case NL80211_IFTYPE_WDS:
2326 - if (bssid || !ieee80211_is_data(hdr->frame_control))
2327 - return 0;
2328 if (compare_ether_addr(sdata->u.wds.remote_addr, hdr->addr2))
2329 return 0;
2330 +
2331 + if (ieee80211_is_data(hdr->frame_control) ||
2332 + ieee80211_is_action(hdr->frame_control)) {
2333 + if (compare_ether_addr(sdata->vif.addr, hdr->addr1))
2334 + return 0;
2335 + } else if (!ieee80211_is_beacon(hdr->frame_control))
2336 + return 0;
2337 +
2338 break;
2339 default:
2340 /* should never get here */
2341 --- a/net/mac80211/sta_info.h
2342 +++ b/net/mac80211/sta_info.h
2343 @@ -31,7 +31,6 @@
2344 * frames.
2345 * @WLAN_STA_ASSOC_AP: We're associated to that station, it is an AP.
2346 * @WLAN_STA_WME: Station is a QoS-STA.
2347 - * @WLAN_STA_WDS: Station is one of our WDS peers.
2348 * @WLAN_STA_CLEAR_PS_FILT: Clear PS filter in hardware (using the
2349 * IEEE80211_TX_CTL_CLEAR_PS_FILT control flag) when the next
2350 * frame to this station is transmitted.
2351 @@ -54,7 +53,6 @@ enum ieee80211_sta_info_flags {
2352 WLAN_STA_SHORT_PREAMBLE = 1<<4,
2353 WLAN_STA_ASSOC_AP = 1<<5,
2354 WLAN_STA_WME = 1<<6,
2355 - WLAN_STA_WDS = 1<<7,
2356 WLAN_STA_CLEAR_PS_FILT = 1<<9,
2357 WLAN_STA_MFP = 1<<10,
2358 WLAN_STA_BLOCK_BA = 1<<11,
2359 --- a/net/mac80211/status.c
2360 +++ b/net/mac80211/status.c
2361 @@ -278,17 +278,19 @@ void ieee80211_tx_status(struct ieee8021
2362 }
2363
2364 if (!acked && ieee80211_is_back_req(fc)) {
2365 + u16 control;
2366 +
2367 /*
2368 - * BAR failed, let's tear down the BA session as a
2369 - * last resort as some STAs (Intel 5100 on Windows)
2370 - * can get stuck when the BA window isn't flushed
2371 - * correctly.
2372 + * BAR failed, store the last SSN and retry sending
2373 + * the BAR when the next unicast transmission on the
2374 + * same TID succeeds.
2375 */
2376 bar = (struct ieee80211_bar *) skb->data;
2377 - if (!(bar->control & IEEE80211_BAR_CTRL_MULTI_TID)) {
2378 + control = le16_to_cpu(bar->control);
2379 + if (!(control & IEEE80211_BAR_CTRL_MULTI_TID)) {
2380 u16 ssn = le16_to_cpu(bar->start_seq_num);
2381
2382 - tid = (bar->control &
2383 + tid = (control &
2384 IEEE80211_BAR_CTRL_TID_INFO_MASK) >>
2385 IEEE80211_BAR_CTRL_TID_INFO_SHIFT;
2386
2387 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
2388 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
2389 @@ -704,8 +704,10 @@ static void ar5008_hw_override_ini(struc
2390 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
2391 }
2392
2393 - if (!AR_SREV_5416_20_OR_LATER(ah) ||
2394 - AR_SREV_9280_20_OR_LATER(ah))
2395 + REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
2396 + AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
2397 +
2398 + if (AR_SREV_9280_20_OR_LATER(ah))
2399 return;
2400 /*
2401 * Disable BB clock gating
2402 @@ -802,7 +804,8 @@ static int ar5008_hw_process_ini(struct
2403
2404 /* Write ADDAC shifts */
2405 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
2406 - ah->eep_ops->set_addac(ah, chan);
2407 + if (ah->eep_ops->set_addac)
2408 + ah->eep_ops->set_addac(ah, chan);
2409
2410 if (AR_SREV_5416_22_OR_LATER(ah)) {
2411 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
2412 @@ -1007,24 +1010,6 @@ static void ar5008_restore_chainmask(str
2413 }
2414 }
2415
2416 -static void ar5008_set_diversity(struct ath_hw *ah, bool value)
2417 -{
2418 - u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
2419 - if (value)
2420 - v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2421 - else
2422 - v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2423 - REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
2424 -}
2425 -
2426 -static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
2427 - struct ath9k_channel *chan)
2428 -{
2429 - if (chan && IS_CHAN_5GHZ(chan))
2430 - return 0x1450;
2431 - return 0x1458;
2432 -}
2433 -
2434 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
2435 struct ath9k_channel *chan)
2436 {
2437 @@ -1654,7 +1639,6 @@ void ar5008_hw_attach_phy_ops(struct ath
2438 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
2439 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
2440 priv_ops->restore_chainmask = ar5008_restore_chainmask;
2441 - priv_ops->set_diversity = ar5008_set_diversity;
2442 priv_ops->do_getnf = ar5008_hw_do_getnf;
2443 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
2444
2445 @@ -1664,9 +1648,7 @@ void ar5008_hw_attach_phy_ops(struct ath
2446 } else
2447 priv_ops->ani_control = ar5008_hw_ani_control_old;
2448
2449 - if (AR_SREV_9100(ah))
2450 - priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
2451 - else if (AR_SREV_9160_10_OR_LATER(ah))
2452 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
2453 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
2454 else
2455 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
2456 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
2457 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
2458 @@ -592,6 +592,9 @@ static void ar9003_hw_override_ini(struc
2459 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
2460 REG_WRITE(ah, AR_PCU_MISC_MODE2,
2461 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
2462 +
2463 + REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
2464 + AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
2465 }
2466
2467 static void ar9003_hw_prog_ini(struct ath_hw *ah,
2468 @@ -785,16 +788,6 @@ static void ar9003_hw_rfbus_done(struct
2469 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
2470 }
2471
2472 -static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
2473 -{
2474 - u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
2475 - if (value)
2476 - v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2477 - else
2478 - v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2479 - REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
2480 -}
2481 -
2482 static bool ar9003_hw_ani_control(struct ath_hw *ah,
2483 enum ath9k_ani_cmd cmd, int param)
2484 {
2485 @@ -1277,7 +1270,6 @@ void ar9003_hw_attach_phy_ops(struct ath
2486 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
2487 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
2488 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
2489 - priv_ops->set_diversity = ar9003_hw_set_diversity;
2490 priv_ops->ani_control = ar9003_hw_ani_control;
2491 priv_ops->do_getnf = ar9003_hw_do_getnf;
2492 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
2493 --- a/drivers/net/wireless/ath/ath9k/eeprom.c
2494 +++ b/drivers/net/wireless/ath/ath9k/eeprom.c
2495 @@ -456,12 +456,7 @@ void ath9k_hw_get_gain_boundaries_pdadcs
2496 pPdGainBoundaries[i] =
2497 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
2498
2499 - if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
2500 - minDelta = pPdGainBoundaries[0] - 23;
2501 - pPdGainBoundaries[0] = 23;
2502 - } else {
2503 - minDelta = 0;
2504 - }
2505 + minDelta = 0;
2506
2507 if (i == 0) {
2508 if (AR_SREV_9280_20_OR_LATER(ah))
2509 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
2510 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
2511 @@ -405,12 +405,7 @@ static void ath9k_hw_set_4k_power_cal_ta
2512 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
2513
2514 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
2515 - if (AR_SREV_5416_20_OR_LATER(ah) &&
2516 - (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2517 - (i != 0)) {
2518 - regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2519 - } else
2520 - regChainOffset = i * 0x1000;
2521 + regChainOffset = i * 0x1000;
2522
2523 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2524 pRawDataset = pEepData->calPierData2G[i];
2525 @@ -423,19 +418,17 @@ static void ath9k_hw_set_4k_power_cal_ta
2526
2527 ENABLE_REGWRITE_BUFFER(ah);
2528
2529 - if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2530 - REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
2531 - SM(pdGainOverlap_t2,
2532 - AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
2533 - | SM(gainBoundaries[0],
2534 - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
2535 - | SM(gainBoundaries[1],
2536 - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
2537 - | SM(gainBoundaries[2],
2538 - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
2539 - | SM(gainBoundaries[3],
2540 - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
2541 - }
2542 + REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
2543 + SM(pdGainOverlap_t2,
2544 + AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
2545 + | SM(gainBoundaries[0],
2546 + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
2547 + | SM(gainBoundaries[1],
2548 + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
2549 + | SM(gainBoundaries[2],
2550 + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
2551 + | SM(gainBoundaries[3],
2552 + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
2553
2554 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2555 for (j = 0; j < 32; j++) {
2556 @@ -715,10 +708,8 @@ static void ath9k_hw_4k_set_txpower(stru
2557 if (test)
2558 return;
2559
2560 - if (AR_SREV_9280_20_OR_LATER(ah)) {
2561 - for (i = 0; i < Ar5416RateSize; i++)
2562 - ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
2563 - }
2564 + for (i = 0; i < Ar5416RateSize; i++)
2565 + ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
2566
2567 ENABLE_REGWRITE_BUFFER(ah);
2568
2569 @@ -788,28 +779,6 @@ static void ath9k_hw_4k_set_txpower(stru
2570 REGWRITE_BUFFER_FLUSH(ah);
2571 }
2572
2573 -static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
2574 - struct ath9k_channel *chan)
2575 -{
2576 - struct modal_eep_4k_header *pModal;
2577 - struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
2578 - u8 biaslevel;
2579 -
2580 - if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
2581 - return;
2582 -
2583 - if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
2584 - return;
2585 -
2586 - pModal = &eep->modalHeader;
2587 -
2588 - if (pModal->xpaBiasLvl != 0xff) {
2589 - biaslevel = pModal->xpaBiasLvl;
2590 - INI_RA(&ah->iniAddac, 7, 1) =
2591 - (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
2592 - }
2593 -}
2594 -
2595 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
2596 struct modal_eep_4k_header *pModal,
2597 struct ar5416_eeprom_4k *eep,
2598 @@ -877,6 +846,7 @@ static void ath9k_hw_4k_set_board_values
2599 u8 txRxAttenLocal;
2600 u8 ob[5], db1[5], db2[5];
2601 u8 ant_div_control1, ant_div_control2;
2602 + u8 bb_desired_scale;
2603 u32 regVal;
2604
2605 pModal = &eep->modalHeader;
2606 @@ -1096,30 +1066,29 @@ static void ath9k_hw_4k_set_board_values
2607 AR_PHY_SETTLING_SWITCH,
2608 pModal->swSettleHt40);
2609 }
2610 - if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {
2611 - u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
2612 - EEP_4K_BB_DESIRED_SCALE_MASK);
2613 - if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
2614 - u32 pwrctrl, mask, clr;
2615 -
2616 - mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
2617 - pwrctrl = mask * bb_desired_scale;
2618 - clr = mask * 0x1f;
2619 - REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
2620 - REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
2621 - REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
2622 -
2623 - mask = BIT(0)|BIT(5)|BIT(15);
2624 - pwrctrl = mask * bb_desired_scale;
2625 - clr = mask * 0x1f;
2626 - REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
2627 -
2628 - mask = BIT(0)|BIT(5);
2629 - pwrctrl = mask * bb_desired_scale;
2630 - clr = mask * 0x1f;
2631 - REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
2632 - REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
2633 - }
2634 +
2635 + bb_desired_scale = (pModal->bb_scale_smrt_antenna &
2636 + EEP_4K_BB_DESIRED_SCALE_MASK);
2637 + if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
2638 + u32 pwrctrl, mask, clr;
2639 +
2640 + mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
2641 + pwrctrl = mask * bb_desired_scale;
2642 + clr = mask * 0x1f;
2643 + REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
2644 + REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
2645 + REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
2646 +
2647 + mask = BIT(0)|BIT(5)|BIT(15);
2648 + pwrctrl = mask * bb_desired_scale;
2649 + clr = mask * 0x1f;
2650 + REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
2651 +
2652 + mask = BIT(0)|BIT(5);
2653 + pwrctrl = mask * bb_desired_scale;
2654 + clr = mask * 0x1f;
2655 + REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
2656 + REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
2657 }
2658 }
2659
2660 @@ -1161,7 +1130,6 @@ const struct eeprom_ops eep_4k_ops = {
2661 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
2662 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
2663 .set_board_values = ath9k_hw_4k_set_board_values,
2664 - .set_addac = ath9k_hw_4k_set_addac,
2665 .set_txpower = ath9k_hw_4k_set_txpower,
2666 .get_spur_channel = ath9k_hw_4k_get_spur_channel
2667 };
2668 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
2669 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
2670 @@ -851,10 +851,8 @@ static void ath9k_hw_ar9287_set_txpower(
2671 if (test)
2672 return;
2673
2674 - if (AR_SREV_9280_20_OR_LATER(ah)) {
2675 - for (i = 0; i < Ar5416RateSize; i++)
2676 - ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
2677 - }
2678 + for (i = 0; i < Ar5416RateSize; i++)
2679 + ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
2680
2681 ENABLE_REGWRITE_BUFFER(ah);
2682
2683 @@ -944,11 +942,6 @@ static void ath9k_hw_ar9287_set_txpower(
2684 REGWRITE_BUFFER_FLUSH(ah);
2685 }
2686
2687 -static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
2688 - struct ath9k_channel *chan)
2689 -{
2690 -}
2691 -
2692 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
2693 struct ath9k_channel *chan)
2694 {
2695 @@ -1100,7 +1093,6 @@ const struct eeprom_ops eep_ar9287_ops =
2696 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
2697 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
2698 .set_board_values = ath9k_hw_ar9287_set_board_values,
2699 - .set_addac = ath9k_hw_ar9287_set_addac,
2700 .set_txpower = ath9k_hw_ar9287_set_txpower,
2701 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
2702 };
2703 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
2704 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
2705 @@ -547,8 +547,7 @@ static void ath9k_hw_def_set_board_value
2706 break;
2707 }
2708
2709 - if (AR_SREV_5416_20_OR_LATER(ah) &&
2710 - (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
2711 + if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
2712 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2713 else
2714 regChainOffset = i * 0x1000;
2715 @@ -565,9 +564,8 @@ static void ath9k_hw_def_set_board_value
2716 SM(pModal->iqCalQCh[i],
2717 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
2718
2719 - if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
2720 - ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
2721 - regChainOffset, i);
2722 + ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
2723 + regChainOffset, i);
2724 }
2725
2726 if (AR_SREV_9280_20_OR_LATER(ah)) {
2727 @@ -893,8 +891,7 @@ static void ath9k_hw_set_def_power_cal_t
2728 xpdGainValues[2]);
2729
2730 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2731 - if (AR_SREV_5416_20_OR_LATER(ah) &&
2732 - (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2733 + if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2734 (i != 0)) {
2735 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2736 } else
2737 @@ -935,27 +932,24 @@ static void ath9k_hw_set_def_power_cal_t
2738
2739 ENABLE_REGWRITE_BUFFER(ah);
2740
2741 - if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2742 - if (OLC_FOR_AR9280_20_LATER) {
2743 - REG_WRITE(ah,
2744 - AR_PHY_TPCRG5 + regChainOffset,
2745 - SM(0x6,
2746 - AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2747 - SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2748 - SM_PD_GAIN(3) | SM_PD_GAIN(4));
2749 - } else {
2750 - REG_WRITE(ah,
2751 - AR_PHY_TPCRG5 + regChainOffset,
2752 - SM(pdGainOverlap_t2,
2753 - AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2754 - SM_PDGAIN_B(0, 1) |
2755 - SM_PDGAIN_B(1, 2) |
2756 - SM_PDGAIN_B(2, 3) |
2757 - SM_PDGAIN_B(3, 4));
2758 - }
2759 + if (OLC_FOR_AR9280_20_LATER) {
2760 + REG_WRITE(ah,
2761 + AR_PHY_TPCRG5 + regChainOffset,
2762 + SM(0x6,
2763 + AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2764 + SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2765 + SM_PD_GAIN(3) | SM_PD_GAIN(4));
2766 + } else {
2767 + REG_WRITE(ah,
2768 + AR_PHY_TPCRG5 + regChainOffset,
2769 + SM(pdGainOverlap_t2,
2770 + AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2771 + SM_PDGAIN_B(0, 1) |
2772 + SM_PDGAIN_B(1, 2) |
2773 + SM_PDGAIN_B(2, 3) |
2774 + SM_PDGAIN_B(3, 4));
2775 }
2776
2777 -
2778 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
2779 diff, pdadcValues);
2780
2781 --- a/drivers/net/wireless/ath/ath9k/init.c
2782 +++ b/drivers/net/wireless/ath/ath9k/init.c
2783 @@ -506,7 +506,6 @@ static void ath9k_init_misc(struct ath_s
2784 sc->sc_flags |= SC_OP_RXAGGR;
2785 }
2786
2787 - ath9k_hw_set_diversity(sc->sc_ah, true);
2788 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
2789
2790 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
2791 --- a/drivers/net/wireless/ath/ath9k/reg.h
2792 +++ b/drivers/net/wireless/ath/ath9k/reg.h
2793 @@ -800,10 +800,6 @@
2794 #define AR_SREV_5416(_ah) \
2795 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
2796 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))
2797 -#define AR_SREV_5416_20_OR_LATER(_ah) \
2798 - (((AR_SREV_5416(_ah)) && \
2799 - ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \
2800 - ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
2801 #define AR_SREV_5416_22_OR_LATER(_ah) \
2802 (((AR_SREV_5416(_ah)) && \
2803 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
2804 --- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
2805 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
2806 @@ -869,6 +869,7 @@ static bool ar9002_hw_init_cal(struct at
2807 ar9002_hw_pa_cal(ah, true);
2808
2809 /* Do NF Calibration after DC offset and other calibrations */
2810 + ath9k_hw_loadnf(ah, chan);
2811 ath9k_hw_start_nfcal(ah, true);
2812
2813 if (ah->caldata)
2814 --- a/net/mac80211/ieee80211_i.h
2815 +++ b/net/mac80211/ieee80211_i.h
2816 @@ -671,7 +671,6 @@ enum queue_stop_reason {
2817 IEEE80211_QUEUE_STOP_REASON_AGGREGATION,
2818 IEEE80211_QUEUE_STOP_REASON_SUSPEND,
2819 IEEE80211_QUEUE_STOP_REASON_SKB_ADD,
2820 - IEEE80211_QUEUE_STOP_REASON_CHTYPE_CHANGE,
2821 };
2822
2823 #ifdef CONFIG_MAC80211_LEDS
2824 --- a/net/mac80211/mlme.c
2825 +++ b/net/mac80211/mlme.c
2826 @@ -1921,24 +1921,8 @@ static void ieee80211_rx_mgmt_beacon(str
2827
2828 rcu_read_unlock();
2829
2830 - /*
2831 - * Whenever the AP announces the HT mode change that can be
2832 - * 40MHz intolerant or etc., it would be safer to stop tx
2833 - * queues before doing hw config to avoid buffer overflow.
2834 - */
2835 - ieee80211_stop_queues_by_reason(&sdata->local->hw,
2836 - IEEE80211_QUEUE_STOP_REASON_CHTYPE_CHANGE);
2837 -
2838 - /* flush out all packets */
2839 - synchronize_net();
2840 -
2841 - drv_flush(local, false);
2842 -
2843 changed |= ieee80211_enable_ht(sdata, elems.ht_info_elem,
2844 bssid, ap_ht_cap_flags);
2845 -
2846 - ieee80211_wake_queues_by_reason(&sdata->local->hw,
2847 - IEEE80211_QUEUE_STOP_REASON_CHTYPE_CHANGE);
2848 }
2849
2850 /* Note: country IE parsing is done for us by cfg80211 */
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