2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
25 static void ar71xx_pci_irq_dispatch(void)
29 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS
) &
30 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
32 if (pending
& PCI_INT_DEV0
)
33 do_IRQ(AR71XX_PCI_IRQ_DEV0
);
35 else if (pending
& PCI_INT_DEV1
)
36 do_IRQ(AR71XX_PCI_IRQ_DEV1
);
38 else if (pending
& PCI_INT_DEV2
)
39 do_IRQ(AR71XX_PCI_IRQ_DEV2
);
41 else if (pending
& PCI_INT_CORE
)
42 do_IRQ(AR71XX_PCI_IRQ_CORE
);
48 static void ar71xx_pci_irq_unmask(unsigned int irq
)
50 irq
-= AR71XX_PCI_IRQ_BASE
;
51 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
52 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) | (1 << irq
));
55 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
58 static void ar71xx_pci_irq_mask(unsigned int irq
)
60 irq
-= AR71XX_PCI_IRQ_BASE
;
61 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
62 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) & ~(1 << irq
));
65 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
68 static struct irq_chip ar71xx_pci_irq_chip
= {
69 .name
= "AR71XX PCI ",
70 .mask
= ar71xx_pci_irq_mask
,
71 .unmask
= ar71xx_pci_irq_unmask
,
72 .mask_ack
= ar71xx_pci_irq_mask
,
75 static struct irqaction ar71xx_pci_irqaction
= {
77 .name
= "cascade [AR71XX PCI]",
80 static void __init
ar71xx_pci_irq_init(void)
84 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
, 0);
85 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS
, 0);
87 for (i
= AR71XX_PCI_IRQ_BASE
;
88 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
89 irq_desc
[i
].status
= IRQ_DISABLED
;
90 set_irq_chip_and_handler(i
, &ar71xx_pci_irq_chip
,
94 setup_irq(AR71XX_CPU_IRQ_PCI
, &ar71xx_pci_irqaction
);
97 static void ar724x_pci_irq_dispatch(void)
101 pending
= ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
) &
102 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
104 if (pending
& AR724X_PCI_INT_DEV0
)
105 do_IRQ(AR71XX_PCI_IRQ_DEV0
);
108 spurious_interrupt();
111 static void ar724x_pci_irq_unmask(unsigned int irq
)
114 case AR71XX_PCI_IRQ_DEV0
:
115 irq
-= AR71XX_PCI_IRQ_BASE
;
116 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
,
117 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
) |
118 AR724X_PCI_INT_DEV0
);
120 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
124 static void ar724x_pci_irq_mask(unsigned int irq
)
127 case AR71XX_PCI_IRQ_DEV0
:
128 irq
-= AR71XX_PCI_IRQ_BASE
;
129 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
,
130 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
) &
131 ~AR724X_PCI_INT_DEV0
);
133 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
135 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS
,
136 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
) |
137 AR724X_PCI_INT_DEV0
);
139 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
);
143 static struct irq_chip ar724x_pci_irq_chip
= {
144 .name
= "AR724X PCI ",
145 .mask
= ar724x_pci_irq_mask
,
146 .unmask
= ar724x_pci_irq_unmask
,
147 .mask_ack
= ar724x_pci_irq_mask
,
150 static struct irqaction ar724x_pci_irqaction
= {
151 .handler
= no_action
,
152 .name
= "cascade [AR724X PCI]",
155 static void __init
ar724x_pci_irq_init(void)
159 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
, 0);
160 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS
, 0);
162 for (i
= AR71XX_PCI_IRQ_BASE
;
163 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
164 irq_desc
[i
].status
= IRQ_DISABLED
;
165 set_irq_chip_and_handler(i
, &ar724x_pci_irq_chip
,
169 setup_irq(AR71XX_CPU_IRQ_PCI
, &ar724x_pci_irqaction
);
171 #endif /* CONFIG_PCI */
173 static void ar71xx_gpio_irq_dispatch(void)
177 pending
= ar71xx_gpio_rr(GPIO_REG_INT_PENDING
)
178 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
181 do_IRQ(AR71XX_GPIO_IRQ_BASE
+ fls(pending
) - 1);
183 spurious_interrupt();
186 static void ar71xx_gpio_irq_unmask(unsigned int irq
)
188 irq
-= AR71XX_GPIO_IRQ_BASE
;
189 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
190 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) | (1 << irq
));
193 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
196 static void ar71xx_gpio_irq_mask(unsigned int irq
)
198 irq
-= AR71XX_GPIO_IRQ_BASE
;
199 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
200 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) & ~(1 << irq
));
203 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
207 static int ar71xx_gpio_irq_set_type(unsigned int irq
, unsigned int flow_type
)
209 /* TODO: implement */
213 #define ar71xx_gpio_irq_set_type NULL
216 static struct irq_chip ar71xx_gpio_irq_chip
= {
217 .name
= "AR71XX GPIO",
218 .unmask
= ar71xx_gpio_irq_unmask
,
219 .mask
= ar71xx_gpio_irq_mask
,
220 .mask_ack
= ar71xx_gpio_irq_mask
,
221 .set_type
= ar71xx_gpio_irq_set_type
,
224 static struct irqaction ar71xx_gpio_irqaction
= {
225 .handler
= no_action
,
226 .name
= "cascade [AR71XX GPIO]",
229 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
230 #define GPIO_INT_ALL 0xffff
232 static void __init
ar71xx_gpio_irq_init(void)
236 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
, 0);
237 ar71xx_gpio_wr(GPIO_REG_INT_PENDING
, 0);
239 /* setup type of all GPIO interrupts to level sensitive */
240 ar71xx_gpio_wr(GPIO_REG_INT_TYPE
, GPIO_INT_ALL
);
242 /* setup polarity of all GPIO interrupts to active high */
243 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY
, GPIO_INT_ALL
);
245 for (i
= AR71XX_GPIO_IRQ_BASE
;
246 i
< AR71XX_GPIO_IRQ_BASE
+ AR71XX_GPIO_IRQ_COUNT
; i
++) {
247 irq_desc
[i
].status
= GPIO_IRQ_INIT_STATUS
;
248 set_irq_chip_and_handler(i
, &ar71xx_gpio_irq_chip
,
252 setup_irq(AR71XX_MISC_IRQ_GPIO
, &ar71xx_gpio_irqaction
);
255 static void ar71xx_misc_irq_dispatch(void)
259 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
)
260 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
262 if (pending
& MISC_INT_UART
)
263 do_IRQ(AR71XX_MISC_IRQ_UART
);
265 else if (pending
& MISC_INT_DMA
)
266 do_IRQ(AR71XX_MISC_IRQ_DMA
);
268 else if (pending
& MISC_INT_PERFC
)
269 do_IRQ(AR71XX_MISC_IRQ_PERFC
);
271 else if (pending
& MISC_INT_TIMER
)
272 do_IRQ(AR71XX_MISC_IRQ_TIMER
);
274 else if (pending
& MISC_INT_OHCI
)
275 do_IRQ(AR71XX_MISC_IRQ_OHCI
);
277 else if (pending
& MISC_INT_ERROR
)
278 do_IRQ(AR71XX_MISC_IRQ_ERROR
);
280 else if (pending
& MISC_INT_GPIO
)
281 ar71xx_gpio_irq_dispatch();
283 else if (pending
& MISC_INT_WDOG
)
284 do_IRQ(AR71XX_MISC_IRQ_WDOG
);
287 spurious_interrupt();
290 static void ar71xx_misc_irq_unmask(unsigned int irq
)
292 irq
-= AR71XX_MISC_IRQ_BASE
;
293 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
294 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) | (1 << irq
));
297 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
300 static void ar71xx_misc_irq_mask(unsigned int irq
)
302 irq
-= AR71XX_MISC_IRQ_BASE
;
303 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
304 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) & ~(1 << irq
));
307 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
310 static void ar724x_misc_irq_ack(unsigned int irq
)
312 irq
-= AR71XX_MISC_IRQ_BASE
;
313 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
,
314 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
) & ~(1 << irq
));
317 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
);
320 static struct irq_chip ar71xx_misc_irq_chip
= {
321 .name
= "AR71XX MISC",
322 .unmask
= ar71xx_misc_irq_unmask
,
323 .mask
= ar71xx_misc_irq_mask
,
326 static struct irqaction ar71xx_misc_irqaction
= {
327 .handler
= no_action
,
328 .name
= "cascade [AR71XX MISC]",
331 static void __init
ar71xx_misc_irq_init(void)
335 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
, 0);
336 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
, 0);
338 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
339 ar71xx_misc_irq_chip
.ack
= ar724x_misc_irq_ack
;
341 ar71xx_misc_irq_chip
.mask_ack
= ar71xx_misc_irq_mask
;
343 for (i
= AR71XX_MISC_IRQ_BASE
;
344 i
< AR71XX_MISC_IRQ_BASE
+ AR71XX_MISC_IRQ_COUNT
; i
++) {
345 irq_desc
[i
].status
= IRQ_DISABLED
;
346 set_irq_chip_and_handler(i
, &ar71xx_misc_irq_chip
,
350 setup_irq(AR71XX_CPU_IRQ_MISC
, &ar71xx_misc_irqaction
);
353 static void ar913x_wmac_irq_dispatch(void)
355 do_IRQ(AR71XX_CPU_IRQ_WMAC
);
358 static void (* ar71xx_ip2_irq_handler
)(void) = spurious_interrupt
;
360 asmlinkage
void plat_irq_dispatch(void)
362 unsigned long pending
;
364 pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
366 if (pending
& STATUSF_IP7
)
367 do_IRQ(AR71XX_CPU_IRQ_TIMER
);
369 else if (pending
& STATUSF_IP2
)
370 ar71xx_ip2_irq_handler();
372 else if (pending
& STATUSF_IP4
)
373 do_IRQ(AR71XX_CPU_IRQ_GE0
);
375 else if (pending
& STATUSF_IP5
)
376 do_IRQ(AR71XX_CPU_IRQ_GE1
);
378 else if (pending
& STATUSF_IP3
)
379 do_IRQ(AR71XX_CPU_IRQ_USB
);
381 else if (pending
& STATUSF_IP6
)
382 ar71xx_misc_irq_dispatch();
385 spurious_interrupt();
388 void __init
arch_init_irq(void)
392 ar71xx_misc_irq_init();
394 switch (ar71xx_soc
) {
395 case AR71XX_SOC_AR7130
:
396 case AR71XX_SOC_AR7141
:
397 case AR71XX_SOC_AR7161
:
399 ar71xx_pci_irq_init();
400 ar71xx_ip2_irq_handler
= ar71xx_pci_irq_dispatch
;
403 case AR71XX_SOC_AR7240
:
405 ar724x_pci_irq_init();
406 ar71xx_ip2_irq_handler
= ar724x_pci_irq_dispatch
;
409 case AR71XX_SOC_AR9130
:
410 case AR71XX_SOC_AR9132
:
411 ar71xx_ip2_irq_handler
= ar913x_wmac_irq_dispatch
;
417 ar71xx_gpio_irq_init();