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[brcm63xx] remove mail headers from patches
[openwrt.git] / target / linux / atheros / patches-2.6.32 / 100-board.patch
1 Index: linux-2.6.32.7/arch/mips/Kconfig
2 ===================================================================
3 --- linux-2.6.32.7.orig/arch/mips/Kconfig 2010-02-03 16:57:31.290430165 +0100
4 +++ linux-2.6.32.7/arch/mips/Kconfig 2010-02-03 17:00:08.814429898 +0100
5 @@ -96,6 +96,19 @@
6 help
7 Support for BCM63XX based boards
8
9 +config ATHEROS_AR231X
10 + bool "Atheros 231x/531x SoC support"
11 + select CEVT_R4K
12 + select CSRC_R4K
13 + select DMA_NONCOHERENT
14 + select IRQ_CPU
15 + select SYS_HAS_CPU_MIPS32_R1
16 + select SYS_SUPPORTS_BIG_ENDIAN
17 + select SYS_SUPPORTS_32BIT_KERNEL
18 + select GENERIC_GPIO
19 + help
20 + Support for AR231x and AR531x based boards
21 +
22 config MIPS_COBALT
23 bool "Cobalt Server"
24 select CEVT_R4K
25 @@ -673,6 +686,7 @@
26
27 endchoice
28
29 +source "arch/mips/ar231x/Kconfig"
30 source "arch/mips/alchemy/Kconfig"
31 source "arch/mips/basler/excite/Kconfig"
32 source "arch/mips/bcm63xx/Kconfig"
33 Index: linux-2.6.32.7/arch/mips/Makefile
34 ===================================================================
35 --- linux-2.6.32.7.orig/arch/mips/Makefile 2010-02-03 16:57:31.851429682 +0100
36 +++ linux-2.6.32.7/arch/mips/Makefile 2010-02-03 17:00:08.814429898 +0100
37 @@ -296,6 +296,13 @@
38
39
40 #
41 +# Atheros AR5312/AR2312 WiSoC
42 +#
43 +core-$(CONFIG_ATHEROS_AR231X) += arch/mips/ar231x/
44 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
45 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
46 +
47 +#
48 # Cobalt Server
49 #
50 core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
51 Index: linux-2.6.32.7/arch/mips/ar231x/Kconfig
52 ===================================================================
53 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
54 +++ linux-2.6.32.7/arch/mips/ar231x/Kconfig 2010-02-03 17:00:08.814429898 +0100
55 @@ -0,0 +1,17 @@
56 +config ATHEROS_AR5312
57 + bool "Atheros 5312/2312+ support"
58 + depends on ATHEROS_AR231X
59 + default y
60 +
61 +config ATHEROS_AR2315
62 + bool "Atheros 2315+ support"
63 + depends on ATHEROS_AR231X
64 + select DMA_NONCOHERENT
65 + select CEVT_R4K
66 + select CSRC_R4K
67 + select IRQ_CPU
68 + select SYS_HAS_CPU_MIPS32_R1
69 + select SYS_SUPPORTS_32BIT_KERNEL
70 + select SYS_SUPPORTS_BIG_ENDIAN
71 + select GENERIC_GPIO
72 + default y
73 Index: linux-2.6.32.7/arch/mips/ar231x/Makefile
74 ===================================================================
75 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
76 +++ linux-2.6.32.7/arch/mips/ar231x/Makefile 2010-02-03 17:00:08.814429898 +0100
77 @@ -0,0 +1,13 @@
78 +#
79 +# This file is subject to the terms and conditions of the GNU General Public
80 +# License. See the file "COPYING" in the main directory of this archive
81 +# for more details.
82 +#
83 +# Copyright (C) 2006 FON Technology, SL.
84 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
85 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
86 +#
87 +
88 +obj-y += board.o prom.o devices.o
89 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
90 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
91 Index: linux-2.6.32.7/arch/mips/ar231x/board.c
92 ===================================================================
93 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
94 +++ linux-2.6.32.7/arch/mips/ar231x/board.c 2010-02-03 17:00:08.814429898 +0100
95 @@ -0,0 +1,251 @@
96 +/*
97 + * This file is subject to the terms and conditions of the GNU General Public
98 + * License. See the file "COPYING" in the main directory of this archive
99 + * for more details.
100 + *
101 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
102 + * Copyright (C) 2006 FON Technology, SL.
103 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
104 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
105 + */
106 +
107 +#include <linux/autoconf.h>
108 +#include <linux/init.h>
109 +#include <linux/module.h>
110 +#include <linux/types.h>
111 +#include <linux/string.h>
112 +#include <linux/platform_device.h>
113 +#include <linux/kernel.h>
114 +#include <linux/random.h>
115 +#include <linux/etherdevice.h>
116 +#include <asm/irq_cpu.h>
117 +#include <asm/reboot.h>
118 +#include <asm/io.h>
119 +
120 +#include <ar231x_platform.h>
121 +#include "devices.h"
122 +#include "ar5312.h"
123 +#include "ar2315.h"
124 +
125 +void (*ar231x_irq_dispatch)(void);
126 +
127 +static inline bool
128 +check_radio_magic(u8 *addr)
129 +{
130 + addr += 0x7a; /* offset for flash magic */
131 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
132 + return 1;
133 + }
134 + return 0;
135 +}
136 +
137 +static inline bool
138 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
139 +{
140 + /* config magic found */
141 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
142 + return 1;
143 +
144 + if (!broken)
145 + return 0;
146 +
147 + if (check_radio_magic(addr + 0xf8))
148 + ar231x_board.radio = addr + 0xf8;
149 + if ((addr < flash_limit + 0x10000) &&
150 + check_radio_magic(addr + 0x10000))
151 + ar231x_board.radio = addr + 0x10000;
152 +
153 + if (ar231x_board.radio) {
154 + /* broken board data detected, use radio data to find the offset,
155 + * user will fix this */
156 + return 1;
157 + }
158 + return 0;
159 +}
160 +
161 +static u8 *
162 +find_board_config(u8 *flash_limit, bool broken)
163 +{
164 + u8 *addr;
165 + int found = 0;
166 +
167 + for (addr = flash_limit - 0x1000;
168 + addr >= flash_limit - 0x30000;
169 + addr -= 0x1000) {
170 +
171 + if (check_board_data(flash_limit, addr, broken)) {
172 + found = 1;
173 + break;
174 + }
175 + }
176 +
177 + if (!found)
178 + addr = NULL;
179 +
180 + return addr;
181 +}
182 +
183 +static u8 *
184 +find_radio_config(u8 *flash_limit, u8 *board_config)
185 +{
186 + int found;
187 + u8 *radio_config;
188 +
189 + /*
190 + * Now find the start of Radio Configuration data, using heuristics:
191 + * Search forward from Board Configuration data by 0x1000 bytes
192 + * at a time until we find non-0xffffffff.
193 + */
194 + found = 0;
195 + for (radio_config = board_config + 0x1000;
196 + (radio_config < flash_limit);
197 + radio_config += 0x1000) {
198 + if ((*(u32 *)radio_config != 0xffffffff) &&
199 + check_radio_magic(radio_config)) {
200 + found = 1;
201 + break;
202 + }
203 + }
204 +
205 + /* AR2316 relocates radio config to new location */
206 + if (!found) {
207 + for (radio_config = board_config + 0xf8;
208 + (radio_config < flash_limit - 0x1000 + 0xf8);
209 + radio_config += 0x1000) {
210 + if ((*(u32 *)radio_config != 0xffffffff) &&
211 + check_radio_magic(radio_config)) {
212 + found = 1;
213 + break;
214 + }
215 + }
216 + }
217 +
218 + if (!found) {
219 + printk("Could not find Radio Configuration data\n");
220 + radio_config = 0;
221 + }
222 +
223 + return (u8 *) radio_config;
224 +}
225 +
226 +int __init
227 +ar231x_find_config(u8 *flash_limit)
228 +{
229 + struct ar231x_boarddata *config;
230 + unsigned int rcfg_size;
231 + int broken_boarddata = 0;
232 + u8 *bcfg, *rcfg;
233 + u8 *board_data;
234 + u8 *radio_data;
235 + u32 offset;
236 +
237 + ar231x_board.config = NULL;
238 + ar231x_board.radio = NULL;
239 + /* Copy the board and radio data to RAM, because accessing the mapped
240 + * memory of the flash directly after booting is not safe */
241 +
242 + /* Try to find valid board and radio data */
243 + bcfg = find_board_config(flash_limit, false);
244 +
245 + /* If that fails, try to at least find valid radio data */
246 + if (!bcfg) {
247 + bcfg = find_board_config(flash_limit, true);
248 + broken_boarddata = 1;
249 + }
250 +
251 + if (!bcfg) {
252 + printk(KERN_WARNING "WARNING: No board configuration data found!\n");
253 + return -ENODEV;
254 + }
255 +
256 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
257 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
258 + memcpy(board_data, bcfg, 0x100);
259 + if (broken_boarddata) {
260 + printk(KERN_WARNING "WARNING: broken board data detected\n");
261 + config = ar231x_board.config;
262 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
263 + printk(KERN_INFO "Fixing up empty mac addresses\n");
264 + config->resetConfigGpio = 0xffff;
265 + config->sysLedGpio = 0xffff;
266 + random_ether_addr(config->wlan0_mac);
267 + config->wlan0_mac[0] &= ~0x06;
268 + random_ether_addr(config->enet0_mac);
269 + random_ether_addr(config->enet1_mac);
270 + }
271 + }
272 +
273 +
274 + /* Radio config starts 0x100 bytes after board config, regardless
275 + * of what the physical layout on the flash chip looks like */
276 +
277 + if (ar231x_board.radio)
278 + rcfg = (u8 *) ar231x_board.radio;
279 + else
280 + rcfg = find_radio_config(flash_limit, bcfg);
281 +
282 + if (!rcfg)
283 + return -ENODEV;
284 +
285 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
286 + ar231x_board.radio = radio_data;
287 + offset = radio_data - board_data;
288 + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
289 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
290 + memcpy(radio_data, rcfg, rcfg_size);
291 +
292 + return 0;
293 +}
294 +
295 +static void
296 +ar231x_halt(void)
297 +{
298 + local_irq_disable();
299 + while (1);
300 +}
301 +
302 +void __init
303 +plat_mem_setup(void)
304 +{
305 + _machine_halt = ar231x_halt;
306 + pm_power_off = ar231x_halt;
307 +
308 + ar5312_plat_setup();
309 + ar2315_plat_setup();
310 +
311 + /* Disable data watchpoints */
312 + write_c0_watchlo0(0);
313 +}
314 +
315 +
316 +asmlinkage void
317 +plat_irq_dispatch(void)
318 +{
319 + ar231x_irq_dispatch();
320 +}
321 +
322 +void __init
323 +plat_time_init(void)
324 +{
325 + ar5312_time_init();
326 + ar2315_time_init();
327 +}
328 +
329 +unsigned int __cpuinit
330 +get_c0_compare_int(void)
331 +{
332 + return CP0_LEGACY_COMPARE_IRQ;
333 +}
334 +
335 +void __init
336 +arch_init_irq(void)
337 +{
338 + clear_c0_status(ST0_IM);
339 + mips_cpu_irq_init();
340 +
341 + /* Initialize interrupt controllers */
342 + ar5312_irq_init();
343 + ar2315_irq_init();
344 +}
345 +
346 +
347 Index: linux-2.6.32.7/arch/mips/ar231x/prom.c
348 ===================================================================
349 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
350 +++ linux-2.6.32.7/arch/mips/ar231x/prom.c 2010-02-03 17:00:08.814429898 +0100
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar531x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <linux/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
390 ===================================================================
391 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
392 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2010-02-03 17:00:08.814429898 +0100
393 @@ -0,0 +1,83 @@
394 +#ifndef __AR531X_PLATFORM_H
395 +#define __AR531X_PLATFORM_H
396 +
397 +/*
398 + * This is board-specific data that is stored in a "fixed" location in flash.
399 + * It is shared across operating systems, so it should not be changed lightly.
400 + * The main reason we need it is in order to extract the ethernet MAC
401 + * address(es).
402 + */
403 +struct ar231x_boarddata {
404 + u32 magic; /* board data is valid */
405 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
406 + u16 cksum; /* checksum (starting with BD_REV 2) */
407 + u16 rev; /* revision of this struct */
408 +#define BD_REV 4
409 + char boardName[64]; /* Name of board */
410 + u16 major; /* Board major number */
411 + u16 minor; /* Board minor number */
412 + u32 flags; /* Board configuration */
413 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
414 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
415 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
416 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
417 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
418 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
419 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
420 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
421 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
422 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
423 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
424 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
425 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
426 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
427 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
428 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
429 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
430 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
431 + u16 resetConfigGpio; /* Reset factory GPIO pin */
432 + u16 sysLedGpio; /* System LED GPIO pin */
433 +
434 + u32 cpuFreq; /* CPU core frequency in Hz */
435 + u32 sysFreq; /* System frequency in Hz */
436 + u32 cntFreq; /* Calculated C0_COUNT frequency */
437 +
438 + u8 wlan0_mac[6];
439 + u8 enet0_mac[6];
440 + u8 enet1_mac[6];
441 +
442 + u16 pciId; /* Pseudo PCIID for common code */
443 + u16 memCap; /* cap bank1 in MB */
444 +
445 + /* version 3 */
446 + u8 wlan1_mac[6]; /* (ar5212) */
447 +};
448 +
449 +#define BOARD_CONFIG_BUFSZ 0x1000
450 +
451 +/*
452 + * Platform device information for the Wireless MAC
453 + */
454 +struct ar231x_board_config {
455 + u16 devid;
456 +
457 + /* board config data */
458 + struct ar231x_boarddata *config;
459 +
460 + /* radio calibration data */
461 + const char *radio;
462 +};
463 +
464 +/*
465 + * Platform device information for the Ethernet MAC
466 + */
467 +struct ar231x_eth {
468 + u32 reset_base;
469 + u32 reset_mac;
470 + u32 reset_phy;
471 + u32 phy_base;
472 + struct ar231x_board_config *config;
473 + char *macaddr;
474 +};
475 +
476 +#endif /* __AR531X_PLATFORM_H */
477 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
478 ===================================================================
479 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
480 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2010-02-03 17:00:08.814429898 +0100
481 @@ -0,0 +1,84 @@
482 +/*
483 + * Atheros SoC specific CPU feature overrides
484 + *
485 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
486 + *
487 + * This file was derived from: include/asm-mips/cpu-features.h
488 + * Copyright (C) 2003, 2004 Ralf Baechle
489 + * Copyright (C) 2004 Maciej W. Rozycki
490 + *
491 + * This program is free software; you can redistribute it and/or modify it
492 + * under the terms of the GNU General Public License version 2 as published
493 + * by the Free Software Foundation.
494 + *
495 + */
496 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
497 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
498 +
499 +/*
500 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
501 + */
502 +#define cpu_has_tlb 1
503 +#define cpu_has_4kex 1
504 +#define cpu_has_3k_cache 0
505 +#define cpu_has_4k_cache 1
506 +#define cpu_has_tx39_cache 0
507 +#define cpu_has_sb1_cache 0
508 +#define cpu_has_fpu 0
509 +#define cpu_has_32fpr 0
510 +#define cpu_has_counter 1
511 +/* #define cpu_has_watch ? */
512 +/* #define cpu_has_divec ? */
513 +/* #define cpu_has_vce ? */
514 +/* #define cpu_has_cache_cdex_p ? */
515 +/* #define cpu_has_cache_cdex_s ? */
516 +/* #define cpu_has_prefetch ? */
517 +/* #define cpu_has_mcheck ? */
518 +#define cpu_has_ejtag 1
519 +
520 +#if !defined(CONFIG_ATHEROS_AR5312)
521 +# define cpu_has_llsc 1
522 +#else
523 +/*
524 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
525 + * ll/sc instructions.
526 + */
527 +# define cpu_has_llsc 0
528 +#endif
529 +
530 +#define cpu_has_mips16 0
531 +#define cpu_has_mdmx 0
532 +#define cpu_has_mips3d 0
533 +#define cpu_has_smartmips 0
534 +
535 +/* #define cpu_has_vtag_icache ? */
536 +/* #define cpu_has_dc_aliases ? */
537 +/* #define cpu_has_ic_fills_f_dc ? */
538 +/* #define cpu_has_pindexed_dcache ? */
539 +
540 +/* #define cpu_icache_snoops_remote_store ? */
541 +
542 +#define cpu_has_mips32r1 1
543 +
544 +#if !defined(CONFIG_ATHEROS_AR5312)
545 +# define cpu_has_mips32r2 1
546 +#endif
547 +
548 +#define cpu_has_mips64r1 0
549 +#define cpu_has_mips64r2 0
550 +
551 +#define cpu_has_dsp 0
552 +#define cpu_has_mipsmt 0
553 +
554 +/* #define cpu_has_nofpuex ? */
555 +#define cpu_has_64bits 0
556 +#define cpu_has_64bit_zero_reg 0
557 +#define cpu_has_64bit_gp_regs 0
558 +#define cpu_has_64bit_addresses 0
559 +
560 +/* #define cpu_has_inclusive_pcaches ? */
561 +
562 +/* #define cpu_dcache_line_size() ? */
563 +/* #define cpu_icache_line_size() ? */
564 +
565 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
566 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/dma-coherence.h
567 ===================================================================
568 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
569 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2010-02-03 17:00:08.814429898 +0100
570 @@ -0,0 +1,64 @@
571 +/*
572 + * This file is subject to the terms and conditions of the GNU General Public
573 + * License. See the file "COPYING" in the main directory of this archive
574 + * for more details.
575 + *
576 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
577 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
578 + *
579 + */
580 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
581 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
582 +
583 +#define PCI_DMA_OFFSET 0x20000000
584 +
585 +struct device;
586 +
587 +static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
588 +{
589 + return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0);
590 +}
591 +
592 +static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
593 +{
594 + return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0);
595 +}
596 +
597 +static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
598 + dma_addr_t dma_addr)
599 +{
600 + return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr);
601 +}
602 +
603 +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
604 + size_t size, enum dma_data_direction direction)
605 +{
606 +}
607 +
608 +static inline int plat_dma_supported(struct device *dev, u64 mask)
609 +{
610 + return 1;
611 +}
612 +
613 +static inline void plat_extra_sync_for_device(struct device *dev)
614 +{
615 + return;
616 +}
617 +
618 +static inline int plat_dma_mapping_error(struct device *dev,
619 + dma_addr_t dma_addr)
620 +{
621 + return 0;
622 +}
623 +
624 +static inline int plat_device_is_coherent(struct device *dev)
625 +{
626 +#ifdef CONFIG_DMA_COHERENT
627 + return 1;
628 +#endif
629 +#ifdef CONFIG_DMA_NONCOHERENT
630 + return 0;
631 +#endif
632 +}
633 +
634 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
635 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/gpio.h
636 ===================================================================
637 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
638 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/gpio.h 2010-02-03 17:00:08.814429898 +0100
639 @@ -0,0 +1,79 @@
640 +#ifndef _ATHEROS_GPIO_H_
641 +#define _ATHEROS_GPIO_H_
642 +
643 +#include <ar231x.h>
644 +
645 +struct ar231x_gpiodev {
646 + u32 valid_mask;
647 + u32 (*get_output)(void);
648 + u32 (*set_output)(u32 mask, u32 val);
649 + u32 (*get)(void);
650 + u32 (*set)(u32 mask, u32 val);
651 +};
652 +
653 +extern const struct ar231x_gpiodev *ar231x_gpiodev;
654 +
655 +/*
656 + * Wrappers for the generic GPIO layer
657 + */
658 +
659 +static inline int gpio_direction_input(unsigned gpio) {
660 + u32 mask = 1 << gpio;
661 +
662 + if (!(ar231x_gpiodev->valid_mask & mask))
663 + return -ENXIO;
664 +
665 + ar231x_gpiodev->set_output(mask, 0);
666 + return 0;
667 +}
668 +
669 +static inline void gpio_set_value(unsigned gpio, int value) {
670 + u32 mask = 1 << gpio;
671 +
672 + if (!(ar231x_gpiodev->valid_mask & mask))
673 + return;
674 +
675 + ar231x_gpiodev->set(mask, (!!value) * mask);
676 +}
677 +
678 +static inline int gpio_direction_output(unsigned gpio, int value) {
679 + u32 mask = 1 << gpio;
680 +
681 + if (!(ar231x_gpiodev->valid_mask & mask))
682 + return -ENXIO;
683 +
684 + ar231x_gpiodev->set_output(mask, mask);
685 + ar231x_gpiodev->set(mask, (!!value) * mask);
686 + return 0;
687 +}
688 +
689 +/* Reads the gpio pin. Unchecked function */
690 +static inline int gpio_get_value(unsigned gpio) {
691 + u32 mask = 1 << gpio;
692 +
693 + if (!(ar231x_gpiodev->valid_mask & mask))
694 + return 0;
695 +
696 + return !!(ar231x_gpiodev->get() & mask);
697 +}
698 +
699 +static inline int gpio_request(unsigned gpio, const char *label) {
700 + return 0;
701 +}
702 +
703 +static inline void gpio_free(unsigned gpio) {
704 +}
705 +
706 +/* Returns IRQ to attach for gpio. Unchecked function */
707 +static inline int gpio_to_irq(unsigned gpio) {
708 + return AR531X_GPIO_IRQ(gpio);
709 +}
710 +
711 +/* Returns gpio for IRQ attached. Unchecked function */
712 +static inline int irq_to_gpio(unsigned irq) {
713 + return (irq - (AR531X_GPIO_IRQ(0)));
714 +}
715 +
716 +#include <asm-generic/gpio.h> /* cansleep wrappers */
717 +
718 +#endif
719 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/reset.h
720 ===================================================================
721 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
722 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/reset.h 2010-02-03 17:00:08.814429898 +0100
723 @@ -0,0 +1,6 @@
724 +#ifndef __AR531X_RESET_H
725 +#define __AR531X_RESET_H
726 +
727 +void ar531x_disable_reset_button(void);
728 +
729 +#endif /* __AR531X_RESET_H */
730 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/war.h
731 ===================================================================
732 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
733 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/war.h 2010-02-03 17:00:08.814429898 +0100
734 @@ -0,0 +1,25 @@
735 +/*
736 + * This file is subject to the terms and conditions of the GNU General Public
737 + * License. See the file "COPYING" in the main directory of this archive
738 + * for more details.
739 + *
740 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
741 + */
742 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
743 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
744 +
745 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
746 +#define R4600_V1_HIT_CACHEOP_WAR 0
747 +#define R4600_V2_HIT_CACHEOP_WAR 0
748 +#define R5432_CP0_INTERRUPT_WAR 0
749 +#define BCM1250_M3_WAR 0
750 +#define SIBYTE_1956_WAR 0
751 +#define MIPS4K_ICACHE_REFILL_WAR 0
752 +#define MIPS_CACHE_SYNC_WAR 0
753 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
754 +#define RM9000_CDEX_SMP_WAR 0
755 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
756 +#define R10000_LLSC_WAR 0
757 +#define MIPS34K_MISSED_ITLB_WAR 0
758 +
759 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
760 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
761 ===================================================================
762 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
763 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2010-02-03 17:00:08.814429898 +0100
764 @@ -0,0 +1,580 @@
765 +/*
766 + * Register definitions for AR2315+
767 + *
768 + * This file is subject to the terms and conditions of the GNU General Public
769 + * License. See the file "COPYING" in the main directory of this archive
770 + * for more details.
771 + *
772 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
773 + * Copyright (C) 2006 FON Technology, SL.
774 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
775 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
776 + */
777 +
778 +#ifndef __AR2315_REG_H
779 +#define __AR2315_REG_H
780 +
781 +/*
782 + * IRQs
783 + */
784 +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
785 +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
786 +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
787 +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
788 +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
789 +
790 +/*
791 + * Address map
792 + */
793 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
794 +#define AR2315_WLAN0 0xB0000000 /* Wireless MMR */
795 +#define AR2315_PCI 0xB0100000 /* PCI MMR */
796 +#define AR2315_SDRAMCTL 0xB0300000 /* SDRAM MMR */
797 +#define AR2315_LOCAL 0xB0400000 /* LOCAL BUS MMR */
798 +#define AR2315_ENET0 0xB0500000 /* ETHERNET MMR */
799 +#define AR2315_DSLBASE 0xB1000000 /* RESET CONTROL MMR */
800 +#define AR2315_UART0 0xB1100003 /* UART MMR */
801 +#define AR2315_SPI 0xB1300000 /* SPI FLASH MMR */
802 +#define AR2315_PCIEXT 0x80000000 /* pci external */
803 +
804 +/*
805 + * Reset Register
806 + */
807 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
808 +
809 +#define AR2315_RESET_COLD_AHB 0x00000001
810 +#define AR2315_RESET_COLD_APB 0x00000002
811 +#define AR2315_RESET_COLD_CPU 0x00000004
812 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
813 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
814 +#define AR2317_RESET_SYSTEM 0x00000010
815 +
816 +
817 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
818 +
819 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
820 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
821 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
822 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
823 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
824 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
825 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
826 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
827 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
828 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
829 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
830 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
831 +
832 +/*
833 + * AHB master arbitration control
834 + */
835 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
836 +
837 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
838 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
839 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
840 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
841 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
842 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
843 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
844 +
845 +/*
846 + * Config Register
847 + */
848 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
849 +
850 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
851 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
852 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
853 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
854 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
855 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
856 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
857 +
858 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
859 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
860 +#define AR2315_CONFIG_PCIAHB 0x00000800
861 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
862 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
863 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
864 +#define AR2315_CONFIG_CPU_PCI 0x00020000
865 +#define AR2315_CONFIG_CPU_MMR 0x00040000
866 +#define AR2315_CONFIG_BIG 0x00000400
867 +
868 +
869 +/*
870 + * NMI control
871 + */
872 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
873 +
874 +#define AR2315_NMI_EN 1
875 +
876 +/*
877 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
878 + */
879 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
880 +
881 +#define AR2315_REV_MAJ 0x00f0
882 +#define AR2315_REV_MAJ_S 4
883 +#define AR2315_REV_MIN 0x000f
884 +#define AR2315_REV_MIN_S 0
885 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
886 +
887 +/*
888 + * Interface Enable
889 + */
890 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
891 +
892 +#define AR2315_IF_MASK 0x00000007
893 +#define AR2315_IF_DISABLED 0
894 +#define AR2315_IF_PCI 1
895 +#define AR2315_IF_TS_LOCAL 2
896 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
897 +#define AR2315_IF_LOCAL_HOST 0x00000008
898 +#define AR2315_IF_PCI_HOST 0x00000010
899 +#define AR2315_IF_PCI_INTR 0x00000020
900 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
901 +#define AR2315_IF_PCI_CLK_INPUT 0
902 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
903 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
904 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
905 +#define AR2315_IF_PCI_CLK_SHIFT 16
906 +
907 +/*
908 + * APB Interrupt control
909 + */
910 +
911 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
912 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
913 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
914 +
915 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
916 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
917 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
918 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
919 +#define AR2315_ISR_APB 0x0010 /* APB error */
920 +#define AR2315_ISR_TIMER 0x0020 /* timer */
921 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
922 +#define AR2315_ISR_WD 0x0080 /* watchdog */
923 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
924 +
925 +#define AR2315_GISR_MISC 0x0001
926 +#define AR2315_GISR_WLAN0 0x0002
927 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
928 +#define AR2315_GISR_LOCALPCI 0x0008
929 +#define AR2315_GISR_WMACPOLL 0x0010
930 +#define AR2315_GISR_TIMER 0x0020
931 +#define AR2315_GISR_ETHERNET 0x0040
932 +
933 +/*
934 + * Interrupt routing from IO to the processor IP bits
935 + * Define our inter mask and level
936 + */
937 +#define AR2315_INTR_MISCIO SR_IBIT3
938 +#define AR2315_INTR_WLAN0 SR_IBIT4
939 +#define AR2315_INTR_ENET0 SR_IBIT5
940 +#define AR2315_INTR_LOCALPCI SR_IBIT6
941 +#define AR2315_INTR_WMACPOLL SR_IBIT7
942 +#define AR2315_INTR_COMPARE SR_IBIT8
943 +
944 +/*
945 + * Timers
946 + */
947 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
948 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
949 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
950 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
951 +
952 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
953 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
954 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
955 +
956 +/*
957 + * CPU Performance Counters
958 + */
959 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
960 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
961 +
962 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
963 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
964 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
965 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
966 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
967 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
968 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
969 +
970 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
971 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
972 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
973 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
974 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
975 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
976 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
977 +
978 +/*
979 + * AHB Error Reporting.
980 + */
981 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
982 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
983 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
984 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
985 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
986 +
987 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
988 + /* write 1 to clear all bits in ERR0 */
989 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
990 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
991 +
992 +#define AR2315_PROCERR_HMAST 0x0000000f
993 +#define AR2315_PROCERR_HMAST_DFLT 0
994 +#define AR2315_PROCERR_HMAST_WMAC 1
995 +#define AR2315_PROCERR_HMAST_ENET 2
996 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
997 +#define AR2315_PROCERR_HMAST_LOCAL 4
998 +#define AR2315_PROCERR_HMAST_CPU 5
999 +#define AR2315_PROCERR_HMAST_PCITGT 6
1000 +
1001 +#define AR2315_PROCERR_HMAST_S 0
1002 +#define AR2315_PROCERR_HWRITE 0x00000010
1003 +#define AR2315_PROCERR_HSIZE 0x00000060
1004 +#define AR2315_PROCERR_HSIZE_S 5
1005 +#define AR2315_PROCERR_HTRANS 0x00000180
1006 +#define AR2315_PROCERR_HTRANS_S 7
1007 +#define AR2315_PROCERR_HBURST 0x00000e00
1008 +#define AR2315_PROCERR_HBURST_S 9
1009 +
1010 +/*
1011 + * Clock Control
1012 + */
1013 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1014 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1015 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1016 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1017 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1018 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1019 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1020 +
1021 +/* PLLc Control fields */
1022 +#define PLLC_REF_DIV_M 0x00000003
1023 +#define PLLC_REF_DIV_S 0
1024 +#define PLLC_FDBACK_DIV_M 0x0000007C
1025 +#define PLLC_FDBACK_DIV_S 2
1026 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1027 +#define PLLC_ADD_FDBACK_DIV_S 7
1028 +#define PLLC_CLKC_DIV_M 0x0001c000
1029 +#define PLLC_CLKC_DIV_S 14
1030 +#define PLLC_CLKM_DIV_M 0x00700000
1031 +#define PLLC_CLKM_DIV_S 20
1032 +
1033 +/* CPU CLK Control fields */
1034 +#define CPUCLK_CLK_SEL_M 0x00000003
1035 +#define CPUCLK_CLK_SEL_S 0
1036 +#define CPUCLK_CLK_DIV_M 0x0000000c
1037 +#define CPUCLK_CLK_DIV_S 2
1038 +
1039 +/* AMBA CLK Control fields */
1040 +#define AMBACLK_CLK_SEL_M 0x00000003
1041 +#define AMBACLK_CLK_SEL_S 0
1042 +#define AMBACLK_CLK_DIV_M 0x0000000c
1043 +#define AMBACLK_CLK_DIV_S 2
1044 +
1045 +/*
1046 + * GPIO
1047 + */
1048 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1049 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1050 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1051 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1052 +
1053 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1054 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1055 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1056 +
1057 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1058 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1059 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1060 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1061 +
1062 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1063 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1064 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1065 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1066 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1067 +
1068 +#define AR2315_RESET_GPIO 5
1069 +#define AR2315_NUM_GPIO 22
1070 +
1071 +/*
1072 + * PCI Clock Control
1073 + */
1074 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1075 +
1076 +#define AR2315_PCICLK_INPUT_M 0x3
1077 +#define AR2315_PCICLK_INPUT_S 0
1078 +
1079 +#define AR2315_PCICLK_PLLC_CLKM 0
1080 +#define AR2315_PCICLK_PLLC_CLKM1 1
1081 +#define AR2315_PCICLK_PLLC_CLKC 2
1082 +#define AR2315_PCICLK_REF_CLK 3
1083 +
1084 +#define AR2315_PCICLK_DIV_M 0xc
1085 +#define AR2315_PCICLK_DIV_S 2
1086 +
1087 +#define AR2315_PCICLK_IN_FREQ 0
1088 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1089 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1090 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1091 +
1092 +/*
1093 + * Observation Control Register
1094 + */
1095 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1096 +#define OCR_GPIO0_IRIN 0x0040
1097 +#define OCR_GPIO1_IROUT 0x0080
1098 +#define OCR_GPIO3_RXCLR 0x0200
1099 +
1100 +/*
1101 + * General Clock Control
1102 + */
1103 +
1104 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1105 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1106 +#define MISCCLK_PROCREFCLK 0x00000002
1107 +
1108 +/*
1109 + * SDRAM Controller
1110 + * - No read or write buffers are included.
1111 + */
1112 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1113 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1114 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1115 +
1116 +#define SDRAM_DATA_WIDTH_M 0x00006000
1117 +#define SDRAM_DATA_WIDTH_S 13
1118 +
1119 +#define SDRAM_COL_WIDTH_M 0x00001E00
1120 +#define SDRAM_COL_WIDTH_S 9
1121 +
1122 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1123 +#define SDRAM_ROW_WIDTH_S 5
1124 +
1125 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1126 +#define SDRAM_BANKADDR_BITS_S 3
1127 +
1128 +/*
1129 + * SPI Flash Interface Registers
1130 + */
1131 +
1132 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1133 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1134 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1135 +
1136 +#define SPI_CTL_START 0x00000100
1137 +#define SPI_CTL_BUSY 0x00010000
1138 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1139 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1140 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1141 +#define SPI_CTL_SIZE_MASK 0x00060000
1142 +
1143 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1144 +#define SPI_OPCODE_MASK 0x000000ff
1145 +
1146 +/*
1147 + * PCI Bus Interface Registers
1148 + */
1149 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1150 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1151 +
1152 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1153 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1154 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1155 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1156 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1157 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1158 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1159 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1160 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1161 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1162 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1163 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1164 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1165 +
1166 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1167 +
1168 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1169 +
1170 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1171 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1172 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1173 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1174 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1175 +
1176 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1177 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1178 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1179 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1180 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1181 +
1182 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1183 +
1184 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1185 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1186 +
1187 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1188 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1189 +
1190 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1191 +
1192 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1193 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1194 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1195 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1196 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1197 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1198 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1199 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1200 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1201 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1202 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1203 +#define AR2315_PCI_EXT_INT 0x02000000
1204 +#define AR2315_PCI_ABORT_INT 0x04000000
1205 +
1206 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1207 +
1208 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1209 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1210 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1211 +
1212 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1213 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1214 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1215 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1216 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1217 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1218 +
1219 +
1220 +/*
1221 + * Local Bus Interface Registers
1222 + */
1223 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1224 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1225 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1226 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1227 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1228 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1229 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1230 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1231 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1232 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1233 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1234 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1235 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1236 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1237 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1238 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1239 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1240 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1241 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1242 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1243 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1244 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1245 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1246 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1247 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1248 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1249 +
1250 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1251 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1252 +
1253 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1254 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1255 +
1256 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1257 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1258 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1259 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1260 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1261 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1262 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1263 +#define AR2315_LBM_TIMEOUT_SHFT 7
1264 +#define AR2315_LBM_PORTMUX 0x07000000
1265 +
1266 +
1267 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1268 +
1269 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1270 +#define AR2315_LB_TXEN_0 0x01
1271 +#define AR2315_LB_TXEN_1 0x02
1272 +#define AR2315_LB_TXEN_2 0x04
1273 +#define AR2315_LB_TXEN_3 0x08
1274 +
1275 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1276 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1277 +
1278 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1279 +#define AR2315_LB_RXEN 0x01
1280 +
1281 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1282 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1283 +
1284 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1285 +#define AR2315_INT_TX_DESC 0x0001
1286 +#define AR2315_INT_TX_OK 0x0002
1287 +#define AR2315_INT_TX_ERR 0x0004
1288 +#define AR2315_INT_TX_EOF 0x0008
1289 +#define AR2315_INT_RX_DESC 0x0010
1290 +#define AR2315_INT_RX_OK 0x0020
1291 +#define AR2315_INT_RX_ERR 0x0040
1292 +#define AR2315_INT_RX_EOF 0x0080
1293 +#define AR2315_INT_TX_TRUNC 0x0100
1294 +#define AR2315_INT_TX_STARVE 0x0200
1295 +#define AR2315_INT_LB_TIMEOUT 0x0400
1296 +#define AR2315_INT_LB_ERR 0x0800
1297 +#define AR2315_INT_MBOX_WR 0x1000
1298 +#define AR2315_INT_MBOX_RD 0x2000
1299 +
1300 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1301 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1302 +
1303 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1304 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1305 +
1306 +/*
1307 + * IR Interface Registers
1308 + */
1309 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1310 +
1311 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1312 +
1313 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1314 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1315 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1316 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1317 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1318 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1319 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1320 +
1321 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1322 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1323 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1324 +
1325 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1326 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1327 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1328 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1329 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1330 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1331 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1332 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1333 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1334 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1335 +
1336 +#define HOST_PCI_DEV_ID 3
1337 +#define HOST_PCI_MBAR0 0x10000000
1338 +#define HOST_PCI_MBAR1 0x20000000
1339 +#define HOST_PCI_MBAR2 0x30000000
1340 +
1341 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1342 +#define PCI_DEVICE_MEM_SPACE 0x800000
1343 +
1344 +#endif /* __AR2315_REG_H */
1345 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1346 ===================================================================
1347 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1348 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2010-02-03 17:00:08.818431986 +0100
1349 @@ -0,0 +1,236 @@
1350 +/*
1351 + * This file is subject to the terms and conditions of the GNU General Public
1352 + * License. See the file "COPYING" in the main directory of this archive
1353 + * for more details.
1354 + *
1355 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1356 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1357 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1358 + */
1359 +
1360 +#ifndef AR5312_H
1361 +#define AR5312_H
1362 +
1363 +#include <asm/addrspace.h>
1364 +
1365 +/*
1366 + * IRQs
1367 + */
1368 +
1369 +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1370 +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1371 +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1372 +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1373 +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1374 +
1375 +
1376 +/* Address Map */
1377 +#define AR531X_WLAN0 0x18000000
1378 +#define AR531X_WLAN1 0x18500000
1379 +#define AR531X_ENET0 0x18100000
1380 +#define AR531X_ENET1 0x18200000
1381 +#define AR531X_SDRAMCTL 0x18300000
1382 +#define AR531X_FLASHCTL 0x18400000
1383 +#define AR531X_APBBASE 0x1c000000
1384 +#define AR531X_FLASH 0x1e000000
1385 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1386 +
1387 +/*
1388 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1389 + * should be considered available. The AR5312 supports 2 enet MACS,
1390 + * even though many reference boards only actually use 1 of them
1391 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1392 + * The AR2312 supports 1 enet MAC.
1393 + */
1394 +#define AR531X_NUM_ENET_MAC 2
1395 +
1396 +/*
1397 + * Need these defines to determine true number of ethernet MACs
1398 + */
1399 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1400 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1401 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1402 +#define AR531X_RADIO_MASK_OFF 0xc8
1403 +#define AR531X_RADIO0_MASK 0x0003
1404 +#define AR531X_RADIO1_MASK 0x000c
1405 +#define AR531X_RADIO1_S 2
1406 +
1407 +/*
1408 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1409 + * should be considered available.
1410 + */
1411 +#define AR531X_NUM_WMAC 2
1412 +
1413 +/* Reset/Timer Block Address Map */
1414 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1415 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1416 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1417 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1418 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1419 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1420 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1421 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1422 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1423 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1424 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1425 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1426 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1427 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1428 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1429 +
1430 +/* AR531X_WD_CTRL register bit field definitions */
1431 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1432 +#define AR531X_WD_CTRL_NMI 0x0001
1433 +#define AR531X_WD_CTRL_RESET 0x0002
1434 +
1435 +/* AR531X_ISR register bit field definitions */
1436 +#define AR531X_ISR_NONE 0x0000
1437 +#define AR531X_ISR_TIMER 0x0001
1438 +#define AR531X_ISR_AHBPROC 0x0002
1439 +#define AR531X_ISR_AHBDMA 0x0004
1440 +#define AR531X_ISR_GPIO 0x0008
1441 +#define AR531X_ISR_UART0 0x0010
1442 +#define AR531X_ISR_UART0DMA 0x0020
1443 +#define AR531X_ISR_WD 0x0040
1444 +#define AR531X_ISR_LOCAL 0x0080
1445 +
1446 +/* AR531X_RESET register bit field definitions */
1447 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1448 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1449 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1450 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1451 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1452 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1453 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1454 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1455 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1456 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1457 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1458 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1459 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1460 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1461 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1462 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1463 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1464 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1465 +
1466 +#define AR531X_RESET_WMAC0_BITS \
1467 + AR531X_RESET_WLAN0 |\
1468 + AR531X_RESET_WARM_WLAN0_MAC |\
1469 + AR531X_RESET_WARM_WLAN0_BB
1470 +
1471 +#define AR531X_RESERT_WMAC1_BITS \
1472 + AR531X_RESET_WLAN1 |\
1473 + AR531X_RESET_WARM_WLAN1_MAC |\
1474 + AR531X_RESET_WARM_WLAN1_BB
1475 +
1476 +/* AR5312_CLOCKCTL1 register bit field definitions */
1477 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1478 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1479 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1480 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1481 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1482 +
1483 +/* Valid for AR5312 and AR2312 */
1484 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1485 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1486 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1487 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1488 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1489 +
1490 +/* Valid for AR2313 */
1491 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1492 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1493 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1494 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1495 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1496 +
1497 +
1498 +/* AR531X_ENABLE register bit field definitions */
1499 +#define AR531X_ENABLE_WLAN0 0x0001
1500 +#define AR531X_ENABLE_ENET0 0x0002
1501 +#define AR531X_ENABLE_ENET1 0x0004
1502 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1503 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1504 +#define AR531X_ENABLE_WLAN1 \
1505 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1506 +
1507 +/* AR531X_REV register bit field definitions */
1508 +#define AR531X_REV_WMAC_MAJ 0xf000
1509 +#define AR531X_REV_WMAC_MAJ_S 12
1510 +#define AR531X_REV_WMAC_MIN 0x0f00
1511 +#define AR531X_REV_WMAC_MIN_S 8
1512 +#define AR531X_REV_MAJ 0x00f0
1513 +#define AR531X_REV_MAJ_S 4
1514 +#define AR531X_REV_MIN 0x000f
1515 +#define AR531X_REV_MIN_S 0
1516 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1517 +
1518 +/* Major revision numbers, bits 7..4 of Revision ID register */
1519 +#define AR531X_REV_MAJ_AR5312 0x4
1520 +#define AR531X_REV_MAJ_AR2313 0x5
1521 +
1522 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1523 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1524 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1525 +
1526 +/* AR531X_FLASHCTL register bit field definitions */
1527 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1528 +#define FLASHCTL_IDCY_S 0
1529 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1530 +#define FLASHCTL_WST1_S 5
1531 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1532 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1533 +#define FLASHCTL_WST2_S 11
1534 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1535 +#define FLASHCTL_AC_S 16
1536 +#define FLASHCTL_AC_128K 0x00000000
1537 +#define FLASHCTL_AC_256K 0x00010000
1538 +#define FLASHCTL_AC_512K 0x00020000
1539 +#define FLASHCTL_AC_1M 0x00030000
1540 +#define FLASHCTL_AC_2M 0x00040000
1541 +#define FLASHCTL_AC_4M 0x00050000
1542 +#define FLASHCTL_AC_8M 0x00060000
1543 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1544 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1545 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1546 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1547 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1548 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1549 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1550 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1551 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1552 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1553 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1554 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1555 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1556 +
1557 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1558 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1559 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1560 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1561 +
1562 +/* ARM SDRAM Controller -- just enough to determine memory size */
1563 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1564 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1565 +#define MEM_CFG1_AC0_S 8
1566 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1567 +#define MEM_CFG1_AC1_S 12
1568 +
1569 +/* GPIO Address Map */
1570 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1571 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1572 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1573 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1574 +
1575 +/* GPIO Control Register bit field definitions */
1576 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1577 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1578 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1579 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1580 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1581 +#define AR531X_NUM_GPIO 8
1582 +
1583 +
1584 +#endif
1585 +
1586 Index: linux-2.6.32.7/arch/mips/ar231x/ar5312.c
1587 ===================================================================
1588 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1589 +++ linux-2.6.32.7/arch/mips/ar231x/ar5312.c 2010-02-03 17:00:08.818431986 +0100
1590 @@ -0,0 +1,547 @@
1591 +/*
1592 + * This file is subject to the terms and conditions of the GNU General Public
1593 + * License. See the file "COPYING" in the main directory of this archive
1594 + * for more details.
1595 + *
1596 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1597 + * Copyright (C) 2006 FON Technology, SL.
1598 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1599 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1600 + */
1601 +
1602 +/*
1603 + * Platform devices for Atheros SoCs
1604 + */
1605 +
1606 +#include <linux/autoconf.h>
1607 +#include <linux/init.h>
1608 +#include <linux/module.h>
1609 +#include <linux/types.h>
1610 +#include <linux/string.h>
1611 +#include <linux/mtd/physmap.h>
1612 +#include <linux/platform_device.h>
1613 +#include <linux/kernel.h>
1614 +#include <linux/reboot.h>
1615 +#include <linux/leds.h>
1616 +#include <asm/bootinfo.h>
1617 +#include <asm/reboot.h>
1618 +#include <asm/time.h>
1619 +#include <asm/irq.h>
1620 +#include <asm/io.h>
1621 +#include <gpio.h>
1622 +
1623 +#include <ar231x_platform.h>
1624 +#include <ar5312_regs.h>
1625 +#include <ar231x.h>
1626 +#include "devices.h"
1627 +#include "ar5312.h"
1628 +
1629 +static void
1630 +ar5312_misc_irq_dispatch(void)
1631 +{
1632 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1633 +
1634 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1635 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1636 + (void)ar231x_read_reg(AR531X_TIMER);
1637 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1638 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1639 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1640 + do_IRQ(AR531X_MISC_IRQ_UART0);
1641 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1642 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1643 + else
1644 + do_IRQ(AR531X_MISC_IRQ_NONE);
1645 +}
1646 +
1647 +static asmlinkage void
1648 +ar5312_irq_dispatch(void)
1649 +{
1650 + int pending = read_c0_status() & read_c0_cause();
1651 +
1652 + if (pending & CAUSEF_IP2)
1653 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1654 + else if (pending & CAUSEF_IP3)
1655 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1656 + else if (pending & CAUSEF_IP4)
1657 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1658 + else if (pending & CAUSEF_IP5)
1659 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1660 + else if (pending & CAUSEF_IP6)
1661 + ar5312_misc_irq_dispatch();
1662 + else if (pending & CAUSEF_IP7)
1663 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1664 +}
1665 +
1666 +
1667 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1668 +static void
1669 +ar5312_misc_intr_enable(unsigned int irq)
1670 +{
1671 + unsigned int imr;
1672 +
1673 + imr = ar231x_read_reg(AR531X_IMR);
1674 + imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1675 + ar231x_write_reg(AR531X_IMR, imr);
1676 +}
1677 +
1678 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1679 +static void
1680 +ar5312_misc_intr_disable(unsigned int irq)
1681 +{
1682 + unsigned int imr;
1683 +
1684 + imr = ar231x_read_reg(AR531X_IMR);
1685 + imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1686 + ar231x_write_reg(AR531X_IMR, imr);
1687 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1688 +}
1689 +
1690 +static void
1691 +ar5312_misc_intr_end(unsigned int irq)
1692 +{
1693 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1694 + ar5312_misc_intr_enable(irq);
1695 +}
1696 +
1697 +static struct irq_chip ar5312_misc_intr_controller = {
1698 + .name = "AR5312-MISC",
1699 + .disable = ar5312_misc_intr_disable,
1700 + .ack = ar5312_misc_intr_disable,
1701 + .mask_ack = ar5312_misc_intr_disable,
1702 + .mask = ar5312_misc_intr_disable,
1703 + .unmask = ar5312_misc_intr_enable,
1704 + .end = ar5312_misc_intr_end,
1705 +};
1706 +
1707 +
1708 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1709 +{
1710 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1711 + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1712 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1713 + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1714 +
1715 + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1716 + procAddr, proc1, dmaAddr, dma1);
1717 +
1718 + machine_restart("AHB error"); /* Catastrophic failure */
1719 + return IRQ_HANDLED;
1720 +}
1721 +
1722 +
1723 +static struct irqaction ar5312_ahb_proc_interrupt = {
1724 + .handler = ar5312_ahb_proc_handler,
1725 + .flags = IRQF_DISABLED,
1726 + .name = "ar5312_ahb_proc_interrupt",
1727 +};
1728 +
1729 +
1730 +static struct irqaction cascade = {
1731 + .handler = no_action,
1732 + .flags = IRQF_DISABLED,
1733 + .name = "cascade",
1734 +};
1735 +
1736 +void __init ar5312_irq_init(void)
1737 +{
1738 + int i;
1739 +
1740 + if (!is_5312())
1741 + return;
1742 +
1743 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1744 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1745 + int irq = AR531X_MISC_IRQ_BASE + i;
1746 + set_irq_chip_and_handler(irq, &ar5312_misc_intr_controller,
1747 + handle_level_irq);
1748 + }
1749 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1750 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1751 +}
1752 +
1753 +const struct ar231x_gpiodev ar5312_gpiodev;
1754 +
1755 +static u32
1756 +ar5312_gpio_get_output(void)
1757 +{
1758 + u32 reg;
1759 + reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1760 + reg &= ar5312_gpiodev.valid_mask;
1761 + return reg;
1762 +}
1763 +
1764 +static u32
1765 +ar5312_gpio_set_output(u32 mask, u32 val)
1766 +{
1767 + u32 reg;
1768 +
1769 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1770 + reg |= mask;
1771 + reg &= ~val;
1772 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1773 + return reg;
1774 +}
1775 +
1776 +static u32
1777 +ar5312_gpio_get(void)
1778 +{
1779 + u32 reg;
1780 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1781 + reg &= ar5312_gpiodev.valid_mask;
1782 + return reg;
1783 +}
1784 +
1785 +static u32
1786 +ar5312_gpio_set(u32 mask, u32 value)
1787 +{
1788 + u32 reg;
1789 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1790 + reg &= ~mask;
1791 + reg |= value;
1792 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1793 + return reg;
1794 +}
1795 +
1796 +const struct ar231x_gpiodev ar5312_gpiodev = {
1797 + .valid_mask = (1 << 8) - 1,
1798 + .get_output = ar5312_gpio_get_output,
1799 + .set_output = ar5312_gpio_set_output,
1800 + .get = ar5312_gpio_get,
1801 + .set = ar5312_gpio_set,
1802 +};
1803 +
1804 +static struct physmap_flash_data ar5312_flash_data = {
1805 + .width = 2,
1806 +};
1807 +
1808 +static struct resource ar5312_flash_resource = {
1809 + .start = AR531X_FLASH,
1810 + .end = AR531X_FLASH + 0x800000 - 1,
1811 + .flags = IORESOURCE_MEM,
1812 +};
1813 +
1814 +static struct ar231x_eth ar5312_eth0_data = {
1815 + .reset_base = AR531X_RESET,
1816 + .reset_mac = AR531X_RESET_ENET0,
1817 + .reset_phy = AR531X_RESET_EPHY0,
1818 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1819 + .config = &ar231x_board,
1820 +};
1821 +
1822 +static struct ar231x_eth ar5312_eth1_data = {
1823 + .reset_base = AR531X_RESET,
1824 + .reset_mac = AR531X_RESET_ENET1,
1825 + .reset_phy = AR531X_RESET_EPHY1,
1826 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1827 + .config = &ar231x_board,
1828 +};
1829 +
1830 +static struct platform_device ar5312_physmap_flash = {
1831 + .name = "physmap-flash",
1832 + .id = 0,
1833 + .dev.platform_data = &ar5312_flash_data,
1834 + .resource = &ar5312_flash_resource,
1835 + .num_resources = 1,
1836 +};
1837 +
1838 +#ifdef CONFIG_LEDS_GPIO
1839 +static struct gpio_led ar5312_leds[] = {
1840 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1841 +};
1842 +
1843 +static const struct gpio_led_platform_data ar5312_led_data = {
1844 + .num_leds = ARRAY_SIZE(ar5312_leds),
1845 + .leds = (void *) ar5312_leds,
1846 +};
1847 +
1848 +static struct platform_device ar5312_gpio_leds = {
1849 + .name = "leds-gpio",
1850 + .id = -1,
1851 + .dev.platform_data = (void *) &ar5312_led_data,
1852 +};
1853 +#endif
1854 +
1855 +/*
1856 + * NB: This mapping size is larger than the actual flash size,
1857 + * but this shouldn't be a problem here, because the flash
1858 + * will simply be mapped multiple times.
1859 + */
1860 +static char __init *ar5312_flash_limit(void)
1861 +{
1862 + u32 ctl;
1863 + /*
1864 + * Configure flash bank 0.
1865 + * Assume 8M window size. Flash will be aliased if it's smaller
1866 + */
1867 + ctl = FLASHCTL_E |
1868 + FLASHCTL_AC_8M |
1869 + FLASHCTL_RBLE |
1870 + (0x01 << FLASHCTL_IDCY_S) |
1871 + (0x07 << FLASHCTL_WST1_S) |
1872 + (0x07 << FLASHCTL_WST2_S) |
1873 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1874 +
1875 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1876 +
1877 + /* Disable other flash banks */
1878 + ar231x_write_reg(AR531X_FLASHCTL1,
1879 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1880 +
1881 + ar231x_write_reg(AR531X_FLASHCTL2,
1882 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1883 +
1884 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1885 +}
1886 +
1887 +int __init ar5312_init_devices(void)
1888 +{
1889 + struct ar231x_boarddata *config;
1890 + u32 fctl = 0;
1891 + const u8 *radio;
1892 + u8 *c;
1893 +
1894 + if (!is_5312())
1895 + return 0;
1896 +
1897 + /* Locate board/radio config data */
1898 + ar231x_find_config(ar5312_flash_limit());
1899 + config = ar231x_board.config;
1900 +
1901 +
1902 + /*
1903 + * Chip IDs and hardware detection for some Atheros
1904 + * models are really broken!
1905 + *
1906 + * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
1907 + * as indication for AR2312, which is otherwise
1908 + * indistinguishable from the real AR5312.
1909 + */
1910 + if (ar231x_board.radio) {
1911 + radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
1912 + if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
1913 + config->flags |= BD_ISCASPER;
1914 + } else
1915 + radio = NULL;
1916 +
1917 + /* AR2313 has CPU minor rev. 10 */
1918 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1919 + ar231x_devtype = DEV_TYPE_AR2313;
1920 +
1921 + /* AR2312 shares the same Silicon ID as AR5312 */
1922 + else if (config->flags & BD_ISCASPER)
1923 + ar231x_devtype = DEV_TYPE_AR2312;
1924 +
1925 + /* Everything else is probably AR5312 or compatible */
1926 + else
1927 + ar231x_devtype = DEV_TYPE_AR5312;
1928 +
1929 + /* fixup flash width */
1930 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1931 + switch (fctl) {
1932 + case FLASHCTL_MWx16:
1933 + ar5312_flash_data.width = 2;
1934 + break;
1935 + case FLASHCTL_MWx8:
1936 + default:
1937 + ar5312_flash_data.width = 1;
1938 + break;
1939 + }
1940 +
1941 + platform_device_register(&ar5312_physmap_flash);
1942 +
1943 +#ifdef CONFIG_LEDS_GPIO
1944 + ar5312_leds[0].gpio = config->sysLedGpio;
1945 + platform_device_register(&ar5312_gpio_leds);
1946 +#endif
1947 +
1948 + /* Fix up MAC addresses if necessary */
1949 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1950 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1951 +
1952 + /* If ENET0 and ENET1 have the same mac address,
1953 + * increment the one from ENET1 */
1954 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1955 + c = config->enet1_mac + 5;
1956 + while ((c >= config->enet1_mac) && !(++(*c)))
1957 + c--;
1958 + }
1959 +
1960 + switch(ar231x_devtype) {
1961 + case DEV_TYPE_AR5312:
1962 + ar5312_eth0_data.macaddr = config->enet0_mac;
1963 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1964 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1965 +
1966 + ar5312_eth1_data.macaddr = config->enet1_mac;
1967 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1968 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1969 +
1970 + if (!ar231x_board.radio)
1971 + return 0;
1972 +
1973 + if (*((u32 *) radio) & AR531X_RADIO0_MASK)
1974 + ar231x_add_wmac(0, AR531X_WLAN0,
1975 + AR5312_IRQ_WLAN0_INTRS);
1976 +
1977 + break;
1978 + /*
1979 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1980 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1981 + */
1982 + case DEV_TYPE_AR2312:
1983 + case DEV_TYPE_AR2313:
1984 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1985 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1986 + ar5312_eth1_data.macaddr = config->enet0_mac;
1987 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1988 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1989 +
1990 + if (!ar231x_board.radio)
1991 + return 0;
1992 + break;
1993 + default:
1994 + break;
1995 + }
1996 +
1997 + if (*((u32 *) radio) & AR531X_RADIO1_MASK)
1998 + ar231x_add_wmac(1, AR531X_WLAN1,
1999 + AR5312_IRQ_WLAN1_INTRS);
2000 +
2001 + return 0;
2002 +}
2003 +
2004 +
2005 +static void ar5312_restart(char *command)
2006 +{
2007 + /* reset the system */
2008 + local_irq_disable();
2009 + while(1) {
2010 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2011 + }
2012 +}
2013 +
2014 +
2015 +/*
2016 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2017 + * to determine the predevisor value.
2018 + */
2019 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2020 +
2021 +
2022 +static int __init
2023 +ar5312_cpu_frequency(void)
2024 +{
2025 + unsigned int result;
2026 + unsigned int predivide_mask, predivide_shift;
2027 + unsigned int multiplier_mask, multiplier_shift;
2028 + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
2029 + unsigned int doubler_mask;
2030 + u16 devid;
2031 +
2032 + /* Trust the bootrom's idea of cpu frequency. */
2033 + if ((result = ar231x_read_reg(AR5312_SCRATCH)))
2034 + return result;
2035 +
2036 + devid = ar231x_read_reg(AR531X_REV);
2037 + devid &= AR531X_REV_MAJ;
2038 + devid >>= AR531X_REV_MAJ_S;
2039 + if (devid == AR531X_REV_MAJ_AR2313) {
2040 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2041 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2042 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2043 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2044 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2045 + } else { /* AR5312 and AR2312 */
2046 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2047 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2048 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2049 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2050 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2051 + }
2052 +
2053 + /*
2054 + * Clocking is derived from a fixed 40MHz input clock.
2055 + *
2056 + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2057 + * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2058 + * flash, Timer, Watchdog Timer)
2059 + *
2060 + * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2061 + *
2062 + * So, for example, with a PLL multiplier of 5, we have
2063 + *
2064 + * cpuFreq = 200MHz
2065 + * sysFreq = 50MHz
2066 + * cntFreq = 100MHz
2067 + *
2068 + * We compute the CPU frequency, based on PLL settings.
2069 + */
2070 +
2071 + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2072 + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2073 + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2074 + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2075 +
2076 + if (clockCtl1 & doubler_mask) {
2077 + multiplier = multiplier << 1;
2078 + }
2079 + return (40000000 / preDivisor) * multiplier;
2080 +}
2081 +
2082 +static inline int
2083 +ar5312_sys_frequency(void)
2084 +{
2085 + return ar5312_cpu_frequency() / 4;
2086 +}
2087 +
2088 +void __init
2089 +ar5312_time_init(void)
2090 +{
2091 + if (!is_5312())
2092 + return;
2093 +
2094 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2095 +}
2096 +
2097 +
2098 +void __init
2099 +ar5312_prom_init(void)
2100 +{
2101 + u32 memsize, memcfg, bank0AC, bank1AC;
2102 + u32 devid;
2103 +
2104 + if (!is_5312())
2105 + return;
2106 +
2107 + /* Detect memory size */
2108 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2109 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2110 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2111 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2112 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2113 + memsize <<= 20;
2114 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2115 +
2116 + devid = ar231x_read_reg(AR531X_REV);
2117 + devid >>= AR531X_REV_WMAC_MIN_S;
2118 + devid &= AR531X_REV_CHIP;
2119 + ar231x_board.devid = (u16) devid;
2120 + ar231x_gpiodev = &ar5312_gpiodev;
2121 +}
2122 +
2123 +void __init
2124 +ar5312_plat_setup(void)
2125 +{
2126 + if (!is_5312())
2127 + return;
2128 +
2129 + /* Clear any lingering AHB errors */
2130 + ar231x_read_reg(AR531X_PROCADDR);
2131 + ar231x_read_reg(AR531X_DMAADDR);
2132 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2133 +
2134 + _machine_restart = ar5312_restart;
2135 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2136 +}
2137 +
2138 Index: linux-2.6.32.7/arch/mips/ar231x/ar2315.c
2139 ===================================================================
2140 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2141 +++ linux-2.6.32.7/arch/mips/ar231x/ar2315.c 2010-02-03 17:00:08.818431986 +0100
2142 @@ -0,0 +1,658 @@
2143 +/*
2144 + * This file is subject to the terms and conditions of the GNU General Public
2145 + * License. See the file "COPYING" in the main directory of this archive
2146 + * for more details.
2147 + *
2148 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2149 + * Copyright (C) 2006 FON Technology, SL.
2150 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2151 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2152 + */
2153 +
2154 +/*
2155 + * Platform devices for Atheros SoCs
2156 + */
2157 +
2158 +#include <linux/autoconf.h>
2159 +#include <linux/init.h>
2160 +#include <linux/module.h>
2161 +#include <linux/types.h>
2162 +#include <linux/string.h>
2163 +#include <linux/platform_device.h>
2164 +#include <linux/kernel.h>
2165 +#include <linux/reboot.h>
2166 +#include <linux/delay.h>
2167 +#include <linux/leds.h>
2168 +#include <asm/bootinfo.h>
2169 +#include <asm/reboot.h>
2170 +#include <asm/time.h>
2171 +#include <asm/irq.h>
2172 +#include <asm/io.h>
2173 +#include <asm/gpio.h>
2174 +
2175 +#include <ar231x_platform.h>
2176 +#include <ar2315_regs.h>
2177 +#include <ar231x.h>
2178 +#include "devices.h"
2179 +#include "ar2315.h"
2180 +
2181 +static u32 gpiointmask = 0, gpiointval = 0;
2182 +
2183 +static inline void ar2315_gpio_irq(void)
2184 +{
2185 + u32 pend;
2186 + int bit = -1;
2187 +
2188 + /* only do one gpio interrupt at a time */
2189 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2190 +
2191 + if (pend) {
2192 + bit = fls(pend) - 1;
2193 + pend &= ~(1 << bit);
2194 + gpiointval ^= (1 << bit);
2195 + }
2196 +
2197 + if (!pend)
2198 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2199 +
2200 + /* Enable interrupt with edge detection */
2201 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2202 + return;
2203 +
2204 + if (bit >= 0)
2205 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2206 +}
2207 +
2208 +
2209 +/*
2210 + * Called when an interrupt is received, this function
2211 + * determines exactly which interrupt it was, and it
2212 + * invokes the appropriate handler.
2213 + *
2214 + * Implicitly, we also define interrupt priority by
2215 + * choosing which to dispatch first.
2216 + */
2217 +static asmlinkage void
2218 +ar2315_irq_dispatch(void)
2219 +{
2220 + int pending = read_c0_status() & read_c0_cause();
2221 +
2222 + if (pending & CAUSEF_IP3)
2223 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2224 + else if (pending & CAUSEF_IP4)
2225 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2226 + else if (pending & CAUSEF_IP2) {
2227 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2228 +
2229 + if (misc_intr & AR2315_ISR_SPI)
2230 + do_IRQ(AR531X_MISC_IRQ_SPI);
2231 + else if (misc_intr & AR2315_ISR_TIMER)
2232 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2233 + else if (misc_intr & AR2315_ISR_AHB)
2234 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2235 + else if (misc_intr & AR2315_ISR_GPIO)
2236 + ar2315_gpio_irq();
2237 + else if (misc_intr & AR2315_ISR_UART0)
2238 + do_IRQ(AR531X_MISC_IRQ_UART0);
2239 + else if (misc_intr & AR2315_ISR_WD)
2240 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2241 + else
2242 + do_IRQ(AR531X_MISC_IRQ_NONE);
2243 + } else if (pending & CAUSEF_IP7)
2244 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2245 +}
2246 +
2247 +static void ar2315_set_gpiointmask(int gpio, int level)
2248 +{
2249 + u32 reg;
2250 +
2251 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2252 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2253 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2254 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2255 +}
2256 +
2257 +static void ar2315_gpio_intr_enable(unsigned int irq)
2258 +{
2259 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2260 +
2261 + /* Enable interrupt with edge detection */
2262 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2263 + return;
2264 +
2265 + gpiointmask |= (1 << gpio);
2266 + ar2315_set_gpiointmask(gpio, 3);
2267 +}
2268 +
2269 +static unsigned int ar2315_gpio_intr_startup(unsigned int irq)
2270 +{
2271 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2272 +
2273 + /* reconfigure GPIO line as input */
2274 + ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
2275 + ar2315_gpio_intr_enable(irq);
2276 + return 0;
2277 +}
2278 +
2279 +static void ar2315_gpio_intr_disable(unsigned int irq)
2280 +{
2281 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2282 +
2283 + /* Disable interrupt */
2284 + gpiointmask &= ~(1 << gpio);
2285 + ar2315_set_gpiointmask(gpio, 0);
2286 +}
2287 +
2288 +static void
2289 +ar2315_gpio_intr_end(unsigned int irq)
2290 +{
2291 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2292 + ar2315_gpio_intr_enable(irq);
2293 +}
2294 +
2295 +static struct irq_chip ar2315_gpio_intr_controller = {
2296 + .typename = "AR2315-GPIO",
2297 + .startup = ar2315_gpio_intr_startup,
2298 + .ack = ar2315_gpio_intr_disable,
2299 + .mask_ack = ar2315_gpio_intr_disable,
2300 + .mask = ar2315_gpio_intr_disable,
2301 + .unmask = ar2315_gpio_intr_enable,
2302 + .end = ar2315_gpio_intr_end,
2303 +};
2304 +
2305 +static void
2306 +ar2315_misc_intr_enable(unsigned int irq)
2307 +{
2308 + unsigned int imr;
2309 +
2310 + imr = ar231x_read_reg(AR2315_IMR);
2311 + switch(irq) {
2312 + case AR531X_MISC_IRQ_SPI:
2313 + imr |= AR2315_ISR_SPI;
2314 + break;
2315 + case AR531X_MISC_IRQ_TIMER:
2316 + imr |= AR2315_ISR_TIMER;
2317 + break;
2318 + case AR531X_MISC_IRQ_AHB_PROC:
2319 + imr |= AR2315_ISR_AHB;
2320 + break;
2321 + case AR531X_MISC_IRQ_GPIO:
2322 + imr |= AR2315_ISR_GPIO;
2323 + break;
2324 + case AR531X_MISC_IRQ_UART0:
2325 + imr |= AR2315_ISR_UART0;
2326 + break;
2327 + case AR531X_MISC_IRQ_WATCHDOG:
2328 + imr |= AR2315_ISR_WD;
2329 + break;
2330 + default:
2331 + break;
2332 + }
2333 + ar231x_write_reg(AR2315_IMR, imr);
2334 +}
2335 +
2336 +static void
2337 +ar2315_misc_intr_disable(unsigned int irq)
2338 +{
2339 + unsigned int imr;
2340 +
2341 + imr = ar231x_read_reg(AR2315_IMR);
2342 + switch(irq) {
2343 + case AR531X_MISC_IRQ_SPI:
2344 + imr &= ~AR2315_ISR_SPI;
2345 + break;
2346 + case AR531X_MISC_IRQ_TIMER:
2347 + imr &= ~AR2315_ISR_TIMER;
2348 + break;
2349 + case AR531X_MISC_IRQ_AHB_PROC:
2350 + imr &= ~AR2315_ISR_AHB;
2351 + break;
2352 + case AR531X_MISC_IRQ_GPIO:
2353 + imr &= ~AR2315_ISR_GPIO;
2354 + break;
2355 + case AR531X_MISC_IRQ_UART0:
2356 + imr &= ~AR2315_ISR_UART0;
2357 + break;
2358 + case AR531X_MISC_IRQ_WATCHDOG:
2359 + imr &= ~AR2315_ISR_WD;
2360 + break;
2361 + default:
2362 + break;
2363 + }
2364 + ar231x_write_reg(AR2315_IMR, imr);
2365 +}
2366 +
2367 +static void
2368 +ar2315_misc_intr_end(unsigned int irq)
2369 +{
2370 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2371 + ar2315_misc_intr_enable(irq);
2372 +}
2373 +
2374 +
2375 +static struct irq_chip ar2315_misc_intr_controller = {
2376 + .typename = "AR2315-MISC",
2377 + .ack = ar2315_misc_intr_disable,
2378 + .mask_ack = ar2315_misc_intr_disable,
2379 + .mask = ar2315_misc_intr_disable,
2380 + .unmask = ar2315_misc_intr_enable,
2381 + .end = ar2315_misc_intr_end,
2382 +};
2383 +
2384 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2385 +{
2386 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2387 + ar231x_read_reg(AR2315_AHB_ERR1);
2388 +
2389 + printk(KERN_ERR "AHB fatal error\n");
2390 + machine_restart("AHB error"); /* Catastrophic failure */
2391 +
2392 + return IRQ_HANDLED;
2393 +}
2394 +
2395 +static struct irqaction ar2315_ahb_proc_interrupt = {
2396 + .handler = ar2315_ahb_proc_handler,
2397 + .flags = IRQF_DISABLED,
2398 + .name = "ar2315_ahb_proc_interrupt",
2399 +};
2400 +
2401 +static struct irqaction cascade = {
2402 + .handler = no_action,
2403 + .flags = IRQF_DISABLED,
2404 + .name = "cascade",
2405 +};
2406 +
2407 +void
2408 +ar2315_irq_init(void)
2409 +{
2410 + int i;
2411 +
2412 + if (!is_2315())
2413 + return;
2414 +
2415 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2416 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2417 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2418 + int irq = AR531X_MISC_IRQ_BASE + i;
2419 + set_irq_chip_and_handler(irq, &ar2315_misc_intr_controller,
2420 + handle_level_irq);
2421 + }
2422 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2423 + int irq = AR531X_GPIO_IRQ_BASE + i;
2424 + set_irq_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2425 + handle_level_irq);
2426 + }
2427 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2428 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2429 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2430 +}
2431 +
2432 +const struct ar231x_gpiodev ar2315_gpiodev;
2433 +
2434 +static u32
2435 +ar2315_gpio_get_output(void)
2436 +{
2437 + u32 reg;
2438 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2439 + reg &= ar2315_gpiodev.valid_mask;
2440 + return reg;
2441 +}
2442 +
2443 +static u32
2444 +ar2315_gpio_set_output(u32 mask, u32 val)
2445 +{
2446 + u32 reg;
2447 +
2448 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2449 + reg &= ~mask;
2450 + reg |= val;
2451 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2452 + return reg;
2453 +}
2454 +
2455 +static u32
2456 +ar2315_gpio_get(void)
2457 +{
2458 + u32 reg;
2459 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2460 + reg &= ar2315_gpiodev.valid_mask;
2461 + return reg;
2462 +}
2463 +
2464 +static u32
2465 +ar2315_gpio_set(u32 mask, u32 value)
2466 +{
2467 + u32 reg;
2468 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2469 + reg &= ~mask;
2470 + reg |= value;
2471 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2472 + return reg;
2473 +}
2474 +
2475 +const struct ar231x_gpiodev ar2315_gpiodev = {
2476 + .valid_mask = (1 << 22) - 1,
2477 + .get_output = ar2315_gpio_get_output,
2478 + .set_output = ar2315_gpio_set_output,
2479 + .get = ar2315_gpio_get,
2480 + .set = ar2315_gpio_set,
2481 +};
2482 +
2483 +static struct ar231x_eth ar2315_eth_data = {
2484 + .reset_base = AR2315_RESET,
2485 + .reset_mac = AR2315_RESET_ENET0,
2486 + .reset_phy = AR2315_RESET_EPHY0,
2487 + .phy_base = AR2315_ENET0,
2488 + .config = &ar231x_board,
2489 +};
2490 +
2491 +static struct resource ar2315_spiflash_res[] = {
2492 + {
2493 + .name = "flash_base",
2494 + .flags = IORESOURCE_MEM,
2495 + .start = KSEG1ADDR(AR2315_SPI_READ),
2496 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2497 + },
2498 + {
2499 + .name = "flash_regs",
2500 + .flags = IORESOURCE_MEM,
2501 + .start = 0x11300000,
2502 + .end = 0x11300012,
2503 + },
2504 +};
2505 +
2506 +static struct platform_device ar2315_spiflash = {
2507 + .id = 0,
2508 + .name = "spiflash",
2509 + .resource = ar2315_spiflash_res,
2510 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2511 +};
2512 +
2513 +static struct platform_device ar2315_wdt = {
2514 + .id = 0,
2515 + .name = "ar2315_wdt",
2516 +};
2517 +
2518 +#define SPI_FLASH_CTL 0x00
2519 +#define SPI_FLASH_OPCODE 0x04
2520 +#define SPI_FLASH_DATA 0x08
2521 +
2522 +static inline u32
2523 +spiflash_read_reg(int reg)
2524 +{
2525 + return ar231x_read_reg(KSEG1ADDR(AR2315_SPI) + reg);
2526 +}
2527 +
2528 +static inline void
2529 +spiflash_write_reg(int reg, u32 data)
2530 +{
2531 + ar231x_write_reg(KSEG1ADDR(AR2315_SPI) + reg, data);
2532 +}
2533 +
2534 +static u32
2535 +spiflash_wait_status(void)
2536 +{
2537 + u32 reg;
2538 +
2539 + do {
2540 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2541 + } while (reg & SPI_CTL_BUSY);
2542 +
2543 + return reg;
2544 +}
2545 +
2546 +static u8
2547 +spiflash_probe(void)
2548 +{
2549 + u32 reg;
2550 +
2551 + reg = spiflash_wait_status();
2552 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2553 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2554 +
2555 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2556 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2557 +
2558 + reg = spiflash_wait_status();
2559 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2560 + reg &= 0xff;
2561 +
2562 + return (u8) reg;
2563 +}
2564 +
2565 +
2566 +#define STM_8MBIT_SIGNATURE 0x13
2567 +#define STM_16MBIT_SIGNATURE 0x14
2568 +#define STM_32MBIT_SIGNATURE 0x15
2569 +#define STM_64MBIT_SIGNATURE 0x16
2570 +#define STM_128MBIT_SIGNATURE 0x17
2571 +
2572 +static u8 __init *
2573 +ar2315_flash_limit(void)
2574 +{
2575 + u32 flash_size = 0;
2576 +
2577 + /* probe the flash chip size */
2578 + switch(spiflash_probe()) {
2579 + case STM_8MBIT_SIGNATURE:
2580 + flash_size = 0x00100000;
2581 + break;
2582 + case STM_16MBIT_SIGNATURE:
2583 + flash_size = 0x00200000;
2584 + break;
2585 + case STM_32MBIT_SIGNATURE:
2586 + flash_size = 0x00400000;
2587 + break;
2588 + case STM_64MBIT_SIGNATURE:
2589 + flash_size = 0x00800000;
2590 + break;
2591 + case STM_128MBIT_SIGNATURE:
2592 + flash_size = 0x01000000;
2593 + break;
2594 + }
2595 +
2596 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2597 + flash_size - 1;
2598 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2599 +}
2600 +
2601 +#ifdef CONFIG_LEDS_GPIO
2602 +static struct gpio_led ar2315_leds[6];
2603 +static struct gpio_led_platform_data ar2315_led_data = {
2604 + .leds = (void *) ar2315_leds,
2605 +};
2606 +
2607 +static struct platform_device ar2315_gpio_leds = {
2608 + .name = "leds-gpio",
2609 + .id = -1,
2610 + .dev = {
2611 + .platform_data = (void *) &ar2315_led_data,
2612 + }
2613 +};
2614 +
2615 +static void __init
2616 +ar2315_init_gpio(void)
2617 +{
2618 + static char led_names[6][6];
2619 + int i, led = 0;
2620 +
2621 + ar2315_led_data.num_leds = 0;
2622 + for(i = 1; i < 8; i++)
2623 + {
2624 + if((i == AR2315_RESET_GPIO) ||
2625 + (i == ar231x_board.config->resetConfigGpio))
2626 + continue;
2627 +
2628 + if(i == ar231x_board.config->sysLedGpio)
2629 + strcpy(led_names[led], "wlan");
2630 + else
2631 + sprintf(led_names[led], "gpio%d", i);
2632 +
2633 + ar2315_leds[led].name = led_names[led];
2634 + ar2315_leds[led].gpio = i;
2635 + ar2315_leds[led].active_low = 0;
2636 + led++;
2637 + }
2638 + ar2315_led_data.num_leds = led;
2639 + platform_device_register(&ar2315_gpio_leds);
2640 +}
2641 +#else
2642 +static inline void ar2315_init_gpio(void)
2643 +{
2644 +}
2645 +#endif
2646 +
2647 +int __init
2648 +ar2315_init_devices(void)
2649 +{
2650 + if (!is_2315())
2651 + return 0;
2652 +
2653 + /* Find board configuration */
2654 + ar231x_find_config(ar2315_flash_limit());
2655 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2656 +
2657 + ar2315_init_gpio();
2658 + platform_device_register(&ar2315_wdt);
2659 + platform_device_register(&ar2315_spiflash);
2660 + ar231x_add_ethernet(0, AR2315_ENET0, AR2315_IRQ_ENET0_INTRS,
2661 + &ar2315_eth_data);
2662 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2663 +
2664 + return 0;
2665 +}
2666 +
2667 +static void
2668 +ar2315_restart(char *command)
2669 +{
2670 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2671 +
2672 + local_irq_disable();
2673 +
2674 + /* try reset the system via reset control */
2675 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2676 +
2677 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2678 + * give it some time to attempt a gpio based hardware reset
2679 + * (atheros reference design workaround) */
2680 + gpio_direction_output(AR2315_RESET_GPIO, 0);
2681 + mdelay(100);
2682 +
2683 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2684 + * workaround. Attempt to jump to the mips reset location -
2685 + * the boot loader itself might be able to recover the system */
2686 + mips_reset_vec();
2687 +}
2688 +
2689 +
2690 +/*
2691 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2692 + * to determine the predevisor value.
2693 + */
2694 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2695 +static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
2696 +
2697 +static unsigned int __init
2698 +ar2315_sys_clk(unsigned int clockCtl)
2699 +{
2700 + unsigned int pllcCtrl,cpuDiv;
2701 + unsigned int pllcOut,refdiv,fdiv,divby2;
2702 + unsigned int clkDiv;
2703 +
2704 + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2705 + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2706 + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2707 + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2708 + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2709 + divby2 += 1;
2710 + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2711 +
2712 +
2713 + /* clkm input selected */
2714 + switch(clockCtl & CPUCLK_CLK_SEL_M) {
2715 + case 0:
2716 + case 1:
2717 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2718 + break;
2719 + case 2:
2720 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2721 + break;
2722 + default:
2723 + pllcOut = 40000000;
2724 + clkDiv = 1;
2725 + break;
2726 + }
2727 + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2728 + cpuDiv = cpuDiv * 2 ?: 1;
2729 + return (pllcOut/(clkDiv * cpuDiv));
2730 +}
2731 +
2732 +static inline unsigned int
2733 +ar2315_cpu_frequency(void)
2734 +{
2735 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2736 +}
2737 +
2738 +static inline unsigned int
2739 +ar2315_apb_frequency(void)
2740 +{
2741 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2742 +}
2743 +
2744 +void __init
2745 +ar2315_time_init(void)
2746 +{
2747 + if (!is_2315())
2748 + return;
2749 +
2750 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2751 +}
2752 +
2753 +void __init
2754 +ar2315_prom_init(void)
2755 +{
2756 + u32 memsize, memcfg, devid;
2757 +
2758 + if (!is_2315())
2759 + return;
2760 +
2761 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2762 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2763 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2764 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2765 + memsize <<= 3;
2766 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2767 +
2768 + /* Detect the hardware based on the device ID */
2769 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2770 + switch(devid) {
2771 + case 0x90:
2772 + case 0x91:
2773 + ar231x_devtype = DEV_TYPE_AR2317;
2774 + break;
2775 + default:
2776 + ar231x_devtype = DEV_TYPE_AR2315;
2777 + break;
2778 + }
2779 + ar231x_gpiodev = &ar2315_gpiodev;
2780 + ar231x_board.devid = devid;
2781 +}
2782 +
2783 +void __init
2784 +ar2315_plat_setup(void)
2785 +{
2786 + u32 config;
2787 +
2788 + if (!is_2315())
2789 + return;
2790 +
2791 + /* Clear any lingering AHB errors */
2792 + config = read_c0_config();
2793 + write_c0_config(config & ~0x3);
2794 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2795 + ar231x_read_reg(AR2315_AHB_ERR1);
2796 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2797 +
2798 + _machine_restart = ar2315_restart;
2799 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2800 +}
2801 Index: linux-2.6.32.7/arch/mips/ar231x/ar2315.h
2802 ===================================================================
2803 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2804 +++ linux-2.6.32.7/arch/mips/ar231x/ar2315.h 2010-02-03 17:00:08.818431986 +0100
2805 @@ -0,0 +1,37 @@
2806 +#ifndef __AR2315_H
2807 +#define __AR2315_H
2808 +
2809 +#ifdef CONFIG_ATHEROS_AR2315
2810 +
2811 +extern void ar2315_irq_init(void);
2812 +extern int ar2315_init_devices(void);
2813 +extern void ar2315_prom_init(void);
2814 +extern void ar2315_plat_setup(void);
2815 +extern void ar2315_time_init(void);
2816 +
2817 +#else
2818 +
2819 +static inline void ar2315_irq_init(void)
2820 +{
2821 +}
2822 +
2823 +static inline int ar2315_init_devices(void)
2824 +{
2825 + return 0;
2826 +}
2827 +
2828 +static inline void ar2315_prom_init(void)
2829 +{
2830 +}
2831 +
2832 +static inline void ar2315_plat_setup(void)
2833 +{
2834 +}
2835 +
2836 +static inline void ar2315_time_init(void)
2837 +{
2838 +}
2839 +
2840 +#endif
2841 +
2842 +#endif
2843 Index: linux-2.6.32.7/arch/mips/ar231x/ar5312.h
2844 ===================================================================
2845 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2846 +++ linux-2.6.32.7/arch/mips/ar231x/ar5312.h 2010-02-03 17:00:08.818431986 +0100
2847 @@ -0,0 +1,38 @@
2848 +#ifndef __AR5312_H
2849 +#define __AR5312_H
2850 +
2851 +#ifdef CONFIG_ATHEROS_AR5312
2852 +
2853 +extern void ar5312_irq_init(void);
2854 +extern int ar5312_init_devices(void);
2855 +extern void ar5312_prom_init(void);
2856 +extern void ar5312_plat_setup(void);
2857 +extern void ar5312_time_init(void);
2858 +extern void ar5312_time_init(void);
2859 +
2860 +#else
2861 +
2862 +static inline void ar5312_irq_init(void)
2863 +{
2864 +}
2865 +
2866 +static inline int ar5312_init_devices(void)
2867 +{
2868 + return 0;
2869 +}
2870 +
2871 +static inline void ar5312_prom_init(void)
2872 +{
2873 +}
2874 +
2875 +static inline void ar5312_plat_setup(void)
2876 +{
2877 +}
2878 +
2879 +static inline void ar5312_time_init(void)
2880 +{
2881 +}
2882 +
2883 +#endif
2884 +
2885 +#endif
2886 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar231x.h
2887 ===================================================================
2888 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2889 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar231x.h 2010-02-03 17:00:08.818431986 +0100
2890 @@ -0,0 +1,54 @@
2891 +#ifndef __AR531X_H
2892 +#define __AR531X_H
2893 +
2894 +#define AR531X_MISC_IRQ_BASE 0x20
2895 +#define AR531X_GPIO_IRQ_BASE 0x30
2896 +
2897 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2898 +#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2899 +#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2900 +
2901 +/* Miscellaneous interrupts, which share IP6 */
2902 +#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2903 +#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2904 +#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2905 +#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2906 +#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2907 +#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2908 +#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2909 +#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2910 +#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2911 +#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2912 +#define AR531X_MISC_IRQ_COUNT 10
2913 +
2914 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2915 +#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2916 +#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2917 +#define AR531X_GPIO_IRQ_COUNT 22
2918 +
2919 +static inline u32
2920 +ar231x_read_reg(u32 reg)
2921 +{
2922 + return __raw_readl((u32 *) KSEG1ADDR(reg));
2923 +}
2924 +
2925 +static inline void
2926 +ar231x_write_reg(u32 reg, u32 val)
2927 +{
2928 + __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2929 +}
2930 +
2931 +static inline u32
2932 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2933 +{
2934 + u32 ret;
2935 +
2936 + ret = ar231x_read_reg(reg);
2937 + ret &= ~mask;
2938 + ret |= val;
2939 + ar231x_write_reg(reg, ret);
2940 +
2941 + return ret;
2942 +}
2943 +
2944 +#endif
2945 Index: linux-2.6.32.7/arch/mips/ar231x/devices.h
2946 ===================================================================
2947 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2948 +++ linux-2.6.32.7/arch/mips/ar231x/devices.h 2010-02-03 17:00:08.818431986 +0100
2949 @@ -0,0 +1,37 @@
2950 +#ifndef __AR231X_DEVICES_H
2951 +#define __AR231X_DEVICES_H
2952 +
2953 +enum {
2954 + /* handled by ar5312.c */
2955 + DEV_TYPE_AR2312,
2956 + DEV_TYPE_AR2313,
2957 + DEV_TYPE_AR5312,
2958 +
2959 + /* handled by ar2315.c */
2960 + DEV_TYPE_AR2315,
2961 + DEV_TYPE_AR2316,
2962 + DEV_TYPE_AR2317,
2963 +
2964 + DEV_TYPE_UNKNOWN
2965 +};
2966 +
2967 +extern int ar231x_devtype;
2968 +extern struct ar231x_board_config ar231x_board;
2969 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2970 +
2971 +extern int ar231x_find_config(u8 *flash_limit);
2972 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2973 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2974 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2975 +
2976 +static inline bool is_2315(void)
2977 +{
2978 + return (current_cpu_data.cputype == CPU_4KEC);
2979 +}
2980 +
2981 +static inline bool is_5312(void)
2982 +{
2983 + return !is_2315();
2984 +}
2985 +
2986 +#endif
2987 Index: linux-2.6.32.7/arch/mips/ar231x/devices.c
2988 ===================================================================
2989 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2990 +++ linux-2.6.32.7/arch/mips/ar231x/devices.c 2010-02-03 17:00:08.818431986 +0100
2991 @@ -0,0 +1,175 @@
2992 +#include <linux/kernel.h>
2993 +#include <linux/init.h>
2994 +#include <linux/serial.h>
2995 +#include <linux/serial_core.h>
2996 +#include <linux/serial_8250.h>
2997 +#include <linux/platform_device.h>
2998 +#include <ar231x_platform.h>
2999 +#include <ar231x.h>
3000 +#include "devices.h"
3001 +#include "ar5312.h"
3002 +#include "ar2315.h"
3003 +
3004 +struct ar231x_board_config ar231x_board;
3005 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
3006 +const struct ar231x_gpiodev *ar231x_gpiodev;
3007 +EXPORT_SYMBOL(ar231x_gpiodev);
3008 +
3009 +static struct resource ar231x_eth0_res[] = {
3010 + {
3011 + .name = "eth0_membase",
3012 + .flags = IORESOURCE_MEM,
3013 + },
3014 + {
3015 + .name = "eth0_irq",
3016 + .flags = IORESOURCE_IRQ,
3017 + }
3018 +};
3019 +
3020 +static struct resource ar231x_eth1_res[] = {
3021 + {
3022 + .name = "eth1_membase",
3023 + .flags = IORESOURCE_MEM,
3024 + },
3025 + {
3026 + .name = "eth1_irq",
3027 + .flags = IORESOURCE_IRQ,
3028 + }
3029 +};
3030 +
3031 +static struct platform_device ar231x_eth[] = {
3032 + {
3033 + .id = 0,
3034 + .name = "ar231x-eth",
3035 + .resource = ar231x_eth0_res,
3036 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3037 + },
3038 + {
3039 + .id = 1,
3040 + .name = "ar231x-eth",
3041 + .resource = ar231x_eth1_res,
3042 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3043 + }
3044 +};
3045 +
3046 +static struct resource ar231x_wmac0_res[] = {
3047 + {
3048 + .name = "wmac0_membase",
3049 + .flags = IORESOURCE_MEM,
3050 + },
3051 + {
3052 + .name = "wmac0_irq",
3053 + .flags = IORESOURCE_IRQ,
3054 + }
3055 +};
3056 +
3057 +static struct resource ar231x_wmac1_res[] = {
3058 + {
3059 + .name = "wmac1_membase",
3060 + .flags = IORESOURCE_MEM,
3061 + },
3062 + {
3063 + .name = "wmac1_irq",
3064 + .flags = IORESOURCE_IRQ,
3065 + }
3066 +};
3067 +
3068 +
3069 +static struct platform_device ar231x_wmac[] = {
3070 + {
3071 + .id = 0,
3072 + .name = "ar231x-wmac",
3073 + .resource = ar231x_wmac0_res,
3074 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3075 + .dev.platform_data = &ar231x_board,
3076 + },
3077 + {
3078 + .id = 1,
3079 + .name = "ar231x-wmac",
3080 + .resource = ar231x_wmac1_res,
3081 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3082 + .dev.platform_data = &ar231x_board,
3083 + },
3084 +};
3085 +
3086 +static const char *devtype_strings[] = {
3087 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3088 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3089 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3090 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3091 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3092 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3093 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3094 +};
3095 +
3096 +const char *get_system_type(void)
3097 +{
3098 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3099 + !devtype_strings[ar231x_devtype])
3100 + return devtype_strings[DEV_TYPE_UNKNOWN];
3101 + return devtype_strings[ar231x_devtype];
3102 +}
3103 +
3104 +
3105 +int __init
3106 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3107 +{
3108 + struct resource *res;
3109 +
3110 + ar231x_eth[nr].dev.platform_data = pdata;
3111 + res = &ar231x_eth[nr].resource[0];
3112 + res->start = base;
3113 + res->end = base + 0x2000 - 1;
3114 + res++;
3115 + res->start = irq;
3116 + res->end = irq;
3117 + return platform_device_register(&ar231x_eth[nr]);
3118 +}
3119 +
3120 +void __init
3121 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3122 +{
3123 + struct uart_port s;
3124 +
3125 + memset(&s, 0, sizeof(s));
3126 +
3127 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3128 + s.iotype = UPIO_MEM;
3129 + s.irq = AR531X_MISC_IRQ_UART0;
3130 + s.regshift = 2;
3131 + s.mapbase = mapbase;
3132 + s.uartclk = uartclk;
3133 + s.membase = (void __iomem *)s.mapbase;
3134 +
3135 + early_serial_setup(&s);
3136 +}
3137 +
3138 +int __init
3139 +ar231x_add_wmac(int nr, u32 base, int irq)
3140 +{
3141 + struct resource *res;
3142 +
3143 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3144 + res = &ar231x_wmac[nr].resource[0];
3145 + res->start = base;
3146 + res->end = base + 0x10000 - 1;
3147 + res++;
3148 + res->start = irq;
3149 + res->end = irq;
3150 + return platform_device_register(&ar231x_wmac[nr]);
3151 +}
3152 +
3153 +static int __init ar231x_register_devices(void)
3154 +{
3155 + static struct resource res = {
3156 + .start = 0xFFFFFFFF,
3157 + };
3158 +
3159 + platform_device_register_simple("GPIODEV", 0, &res, 1);
3160 + ar5312_init_devices();
3161 + ar2315_init_devices();
3162 +
3163 + return 0;
3164 +}
3165 +
3166 +device_initcall(ar231x_register_devices);
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