target/linux/atheros/patches-2.6.32/120-spiflash.patch

   1 Index: linux-2.6.32.7/drivers/mtd/devices/Kconfig
   2 ===================================================================
   3 --- linux-2.6.32.7.orig/drivers/mtd/devices/Kconfig     2010-01-29 00:06:20.000000000 +0100
   4 +++ linux-2.6.32.7/drivers/mtd/devices/Kconfig  2010-02-03 17:01:08.858429535 +0100
   5 @@ -114,6 +114,10 @@
   6           Set up your spi devices with the right board-specific platform data,
   7           if you want to specify device partitioning.
   8
   9 +config MTD_AR2315
  10 +       tristate "Atheros AR2315+ SPI Flash support"
  11 +       depends on ATHEROS_AR2315
  12 +
  13  config MTD_SLRAM
  14         tristate "Uncached system RAM"
  15         help
  16 Index: linux-2.6.32.7/drivers/mtd/devices/Makefile
  17 ===================================================================
  18 --- linux-2.6.32.7.orig/drivers/mtd/devices/Makefile    2010-01-29 00:06:20.000000000 +0100
  19 +++ linux-2.6.32.7/drivers/mtd/devices/Makefile 2010-02-03 17:01:30.282430590 +0100
  20 @@ -17,3 +17,4 @@
  21  obj-$(CONFIG_MTD_DATAFLASH)    += mtd_dataflash.o
  22  obj-$(CONFIG_MTD_M25P80)       += m25p80.o
  23  obj-$(CONFIG_MTD_SST25L)       += sst25l.o
  24 +obj-$(CONFIG_MTD_AR2315)       += ar2315.o
  25 Index: linux-2.6.32.7/drivers/mtd/devices/ar2315.c
  26 ===================================================================
  27 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  28 +++ linux-2.6.32.7/drivers/mtd/devices/ar2315.c 2010-02-03 17:01:08.858429535 +0100
  29 @@ -0,0 +1,517 @@
  30 +
  31 +/*
  32 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
  33 + *
  34 + * Copyright (c) 2005-2006 Atheros Communications Inc.
  35 + * Copyright (C) 2006-2007 FON Technology, SL.
  36 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
  37 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
  38 + *
  39 + * This code is free software; you can redistribute it and/or modify
  40 + * it under the terms of the GNU General Public License version 2 as
  41 + * published by the Free Software Foundation.
  42 + *
  43 + */
  44 +
  45 +#include <linux/kernel.h>
  46 +#include <linux/module.h>
  47 +#include <linux/types.h>
  48 +#include <linux/version.h>
  49 +#include <linux/errno.h>
  50 +#include <linux/slab.h>
  51 +#include <linux/mtd/mtd.h>
  52 +#include <linux/mtd/partitions.h>
  53 +#include <linux/platform_device.h>
  54 +#include <linux/sched.h>
  55 +#include <linux/root_dev.h>
  56 +#include <linux/delay.h>
  57 +#include <asm/delay.h>
  58 +#include <asm/io.h>
  59 +
  60 +#include <ar2315_spiflash.h>
  61 +#include <ar231x_platform.h>
  62 +#include <ar231x.h>
  63 +
  64 +
  65 +#define SPIFLASH "spiflash: "
  66 +#define busy_wait(_priv, _condition, _wait) do { \
  67 +       while (_condition) { \
  68 +               spin_unlock_bh(&_priv->lock); \
  69 +               if (_wait > 1) \
  70 +                       msleep(_wait); \
  71 +               else if ((_wait == 1) && need_resched()) \
  72 +                       schedule(); \
  73 +               else \
  74 +                       udelay(1); \
  75 +               spin_lock_bh(&_priv->lock); \
  76 +       } \
  77 +} while (0)
  78 +
  79 +enum {
  80 +       FLASH_NONE,
  81 +       FLASH_1MB,
  82 +       FLASH_2MB,
  83 +       FLASH_4MB,
  84 +       FLASH_8MB,
  85 +       FLASH_16MB,
  86 +};
  87 +
  88 +/* Flash configuration table */
  89 +struct flashconfig {
  90 +       u32 byte_cnt;
  91 +       u32 sector_cnt;
  92 +       u32 sector_size;
  93 +};
  94 +
  95 +const struct flashconfig flashconfig_tbl[] = {
  96 +       [FLASH_NONE] = { 0, 0, 0},
  97 +       [FLASH_1MB]  = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
  98 +       [FLASH_2MB]  = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
  99 +       [FLASH_4MB]  = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
 100 +       [FLASH_8MB]  = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
 101 +       [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
 102 +};
 103 +
 104 +/* Mapping of generic opcodes to STM serial flash opcodes */
 105 +enum {
 106 +       SPI_WRITE_ENABLE,
 107 +       SPI_WRITE_DISABLE,
 108 +       SPI_RD_STATUS,
 109 +       SPI_WR_STATUS,
 110 +       SPI_RD_DATA,
 111 +       SPI_FAST_RD_DATA,
 112 +       SPI_PAGE_PROGRAM,
 113 +       SPI_SECTOR_ERASE,
 114 +       SPI_BULK_ERASE,
 115 +       SPI_DEEP_PWRDOWN,
 116 +       SPI_RD_SIG,
 117 +};
 118 +
 119 +struct opcodes {
 120 +    __u16 code;
 121 +    __s8 tx_cnt;
 122 +    __s8 rx_cnt;
 123 +};
 124 +const struct opcodes stm_opcodes[] = {
 125 +       [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
 126 +       [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
 127 +       [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
 128 +       [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
 129 +       [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
 130 +       [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
 131 +       [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
 132 +       [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
 133 +       [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
 134 +       [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
 135 +       [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
 136 +};
 137 +
 138 +/* Driver private data structure */
 139 +struct spiflash_priv {
 140 +       struct mtd_info mtd;
 141 +       void *readaddr; /* memory mapped data for read  */
 142 +       void *mmraddr;  /* memory mapped register space */
 143 +       wait_queue_head_t wq;
 144 +       spinlock_t lock;
 145 +       int state;
 146 +};
 147 +
 148 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
 149 +
 150 +enum {
 151 +       FL_READY,
 152 +       FL_READING,
 153 +       FL_ERASING,
 154 +       FL_WRITING
 155 +};
 156 +
 157 +/***************************************************************************************************/
 158 +
 159 +static u32
 160 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
 161 +{
 162 +       return ar231x_read_reg((u32) priv->mmraddr + reg);
 163 +}
 164 +
 165 +static void
 166 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
 167 +{
 168 +       ar231x_write_reg((u32) priv->mmraddr + reg, data);
 169 +}
 170 +
 171 +static u32
 172 +spiflash_wait_busy(struct spiflash_priv *priv)
 173 +{
 174 +       u32 reg;
 175 +
 176 +       busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
 177 +               SPI_CTL_BUSY, 0);
 178 +       return reg;
 179 +}
 180 +
 181 +static u32
 182 +spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr)
 183 +{
 184 +       const struct opcodes *op;
 185 +       u32 reg, mask;
 186 +
 187 +       op = &stm_opcodes[opcode];
 188 +       reg = spiflash_wait_busy(priv);
 189 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE,
 190 +               ((u32) op->code) | (addr << 8));
 191 +
 192 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 193 +       reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
 194 +
 195 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 196 +       spiflash_wait_busy(priv);
 197 +
 198 +       if (!op->rx_cnt)
 199 +               return 0;
 200 +
 201 +       reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
 202 +
 203 +       switch (op->rx_cnt) {
 204 +       case 1:
 205 +               mask = 0x000000ff;
 206 +               break;
 207 +       case 2:
 208 +               mask = 0x0000ffff;
 209 +               break;
 210 +       case 3:
 211 +               mask = 0x00ffffff;
 212 +               break;
 213 +       default:
 214 +               mask = 0xffffffff;
 215 +               break;
 216 +       }
 217 +       reg &= mask;
 218 +
 219 +       return reg;
 220 +}
 221 +
 222 +
 223 +/*
 224 + * Probe SPI flash device
 225 + * Function returns 0 for failure.
 226 + * and flashconfig_tbl array index for success.
 227 + */
 228 +static int
 229 +spiflash_probe_chip (struct spiflash_priv *priv)
 230 +{
 231 +       u32 sig;
 232 +       int flash_size;
 233 +
 234 +       /* Read the signature on the flash device */
 235 +       spin_lock_bh(&priv->lock);
 236 +       sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
 237 +       spin_unlock_bh(&priv->lock);
 238 +
 239 +       switch (sig) {
 240 +       case STM_8MBIT_SIGNATURE:
 241 +               flash_size = FLASH_1MB;
 242 +               break;
 243 +       case STM_16MBIT_SIGNATURE:
 244 +               flash_size = FLASH_2MB;
 245 +               break;
 246 +       case STM_32MBIT_SIGNATURE:
 247 +               flash_size = FLASH_4MB;
 248 +               break;
 249 +       case STM_64MBIT_SIGNATURE:
 250 +               flash_size = FLASH_8MB;
 251 +               break;
 252 +       case STM_128MBIT_SIGNATURE:
 253 +               flash_size = FLASH_16MB;
 254 +               break;
 255 +       default:
 256 +               printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
 257 +               return 0;
 258 +       }
 259 +
 260 +       return flash_size;
 261 +}
 262 +
 263 +
 264 +/* wait until the flash chip is ready and grab a lock */
 265 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
 266 +{
 267 +       DECLARE_WAITQUEUE(wait, current);
 268 +
 269 +retry:
 270 +       spin_lock_bh(&priv->lock);
 271 +       if (priv->state != FL_READY) {
 272 +               set_current_state(TASK_UNINTERRUPTIBLE);
 273 +               add_wait_queue(&priv->wq, &wait);
 274 +               spin_unlock_bh(&priv->lock);
 275 +               schedule();
 276 +               remove_wait_queue(&priv->wq, &wait);
 277 +
 278 +               if(signal_pending(current))
 279 +                       return 0;
 280 +
 281 +               goto retry;
 282 +       }
 283 +       priv->state = state;
 284 +
 285 +       return 1;
 286 +}
 287 +
 288 +static inline void spiflash_done(struct spiflash_priv *priv)
 289 +{
 290 +       priv->state = FL_READY;
 291 +       spin_unlock_bh(&priv->lock);
 292 +       wake_up(&priv->wq);
 293 +}
 294 +
 295 +static void
 296 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
 297 +{
 298 +       busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
 299 +               SPI_STATUS_WIP, timeout);
 300 +       spiflash_done(priv);
 301 +}
 302 +
 303 +
 304 +
 305 +static int
 306 +spiflash_erase (struct mtd_info *mtd, struct erase_info *instr)
 307 +{
 308 +       struct spiflash_priv *priv = to_spiflash(mtd);
 309 +       const struct opcodes *op;
 310 +       u32 temp, reg;
 311 +
 312 +       if (instr->addr + instr->len > mtd->size)
 313 +               return -EINVAL;
 314 +
 315 +       if (!spiflash_wait_ready(priv, FL_ERASING))
 316 +               return -EINTR;
 317 +
 318 +       spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 319 +       reg = spiflash_wait_busy(priv);
 320 +
 321 +       op = &stm_opcodes[SPI_SECTOR_ERASE];
 322 +       temp = ((u32)instr->addr << 8) | (u32)(op->code);
 323 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
 324 +
 325 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 326 +       reg |= op->tx_cnt | SPI_CTL_START;
 327 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 328 +
 329 +       spiflash_wait_complete(priv, 20);
 330 +
 331 +       instr->state = MTD_ERASE_DONE;
 332 +       mtd_erase_callback(instr);
 333 +
 334 +       return 0;
 335 +}
 336 +
 337 +static int
 338 +spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
 339 +{
 340 +       struct spiflash_priv *priv = to_spiflash(mtd);
 341 +       u8 *read_addr;
 342 +
 343 +       if (!len)
 344 +               return 0;
 345 +
 346 +       if (from + len > mtd->size)
 347 +               return -EINVAL;
 348 +
 349 +       *retlen = len;
 350 +
 351 +       if (!spiflash_wait_ready(priv, FL_READING))
 352 +               return -EINTR;
 353 +
 354 +       read_addr = (u8 *)(priv->readaddr + from);
 355 +       memcpy_fromio(buf, read_addr, len);
 356 +       spiflash_done(priv);
 357 +
 358 +       return 0;
 359 +}
 360 +
 361 +static int
 362 +spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf)
 363 +{
 364 +       struct spiflash_priv *priv = to_spiflash(mtd);
 365 +       u32 opcode, bytes_left;
 366 +
 367 +       *retlen = 0;
 368 +
 369 +       if (!len)
 370 +               return 0;
 371 +
 372 +       if (to + len > mtd->size)
 373 +               return -EINVAL;
 374 +
 375 +       bytes_left = len;
 376 +
 377 +       do {
 378 +               u32 read_len, reg, page_offset, spi_data = 0;
 379 +
 380 +               read_len = min(bytes_left, sizeof(u32));
 381 +
 382 +               /* 32-bit writes cannot span across a page boundary
 383 +                * (256 bytes). This types of writes require two page
 384 +                * program operations to handle it correctly. The STM part
 385 +                * will write the overflow data to the beginning of the
 386 +                * current page as opposed to the subsequent page.
 387 +                */
 388 +               page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
 389 +
 390 +               if (page_offset > STM_PAGE_SIZE)
 391 +                       read_len -= (page_offset - STM_PAGE_SIZE);
 392 +
 393 +               if (!spiflash_wait_ready(priv, FL_WRITING))
 394 +                       return -EINTR;
 395 +
 396 +               spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 397 +               spi_data = 0;
 398 +               switch (read_len) {
 399 +               case 4:
 400 +                       spi_data |= buf[3] << 24;
 401 +                       /* fall through */
 402 +               case 3:
 403 +                       spi_data |= buf[2] << 16;
 404 +                       /* fall through */
 405 +               case 2:
 406 +                       spi_data |= buf[1] << 8;
 407 +                       /* fall through */
 408 +               case 1:
 409 +                       spi_data |= buf[0] & 0xff;
 410 +                       break;
 411 +               default:
 412 +                       break;
 413 +               }
 414 +
 415 +               spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
 416 +               opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
 417 +                       (to & 0x00ffffff) << 8;
 418 +               spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
 419 +
 420 +               reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
 421 +               reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 422 +               reg |= (read_len + 4) | SPI_CTL_START;
 423 +               spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 424 +
 425 +               spiflash_wait_complete(priv, 1);
 426 +
 427 +               bytes_left -= read_len;
 428 +               to += read_len;
 429 +               buf += read_len;
 430 +
 431 +               *retlen += read_len;
 432 +       } while (bytes_left != 0);
 433 +
 434 +       return 0;
 435 +}
 436 +
 437 +
 438 +#ifdef CONFIG_MTD_PARTITIONS
 439 +static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
 440 +#endif
 441 +
 442 +
 443 +static int
 444 +spiflash_probe(struct platform_device *pdev)
 445 +{
 446 +       struct spiflash_priv *priv;
 447 +       struct mtd_partition *parts;
 448 +       struct mtd_info *mtd;
 449 +       int index, num_parts;
 450 +       int result = 0;
 451 +
 452 +       priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
 453 +       spin_lock_init(&priv->lock);
 454 +       init_waitqueue_head(&priv->wq);
 455 +       priv->state = FL_READY;
 456 +       mtd = &priv->mtd;
 457 +
 458 +       priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
 459 +       if (!priv->mmraddr) {
 460 +               printk(KERN_WARNING SPIFLASH "Failed to map flash device\n");
 461 +               goto error;
 462 +       }
 463 +
 464 +       index = spiflash_probe_chip(priv);
 465 +       if (!index) {
 466 +               printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
 467 +               goto error;
 468 +       }
 469 +
 470 +       priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
 471 +       if (!priv->readaddr) {
 472 +               printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
 473 +               goto error;
 474 +       }
 475 +
 476 +       platform_set_drvdata(pdev, priv);
 477 +       mtd->name = "spiflash";
 478 +       mtd->type = MTD_NORFLASH;
 479 +       mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
 480 +       mtd->size = flashconfig_tbl[index].byte_cnt;
 481 +       mtd->erasesize = flashconfig_tbl[index].sector_size;
 482 +       mtd->writesize = 1;
 483 +       mtd->numeraseregions = 0;
 484 +       mtd->eraseregions = NULL;
 485 +       mtd->erase = spiflash_erase;
 486 +       mtd->read = spiflash_read;
 487 +       mtd->write = spiflash_write;
 488 +       mtd->owner = THIS_MODULE;
 489 +
 490 +#ifdef CONFIG_MTD_PARTITIONS
 491 +       /* parse redboot partitions */
 492 +       num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0);
 493 +       if (!num_parts)
 494 +               goto error;
 495 +
 496 +       result = add_mtd_partitions(mtd, parts, num_parts);
 497 +#endif
 498 +
 499 +       return result;
 500 +
 501 +error:
 502 +       if (priv->mmraddr)
 503 +               iounmap(priv->mmraddr);
 504 +       kfree(priv);
 505 +       return -ENXIO;
 506 +}
 507 +
 508 +static int
 509 +spiflash_remove (struct platform_device *pdev)
 510 +{
 511 +       struct spiflash_priv *priv = platform_get_drvdata(pdev);
 512 +       struct mtd_info *mtd = &priv->mtd;
 513 +
 514 +       del_mtd_partitions(mtd);
 515 +       iounmap(priv->mmraddr);
 516 +       iounmap(priv->readaddr);
 517 +       kfree(priv);
 518 +
 519 +       return 0;
 520 +}
 521 +
 522 +struct platform_driver spiflash_driver = {
 523 +       .driver.name = "spiflash",
 524 +       .probe = spiflash_probe,
 525 +       .remove = spiflash_remove,
 526 +};
 527 +
 528 +int __init
 529 +spiflash_init (void)
 530 +{
 531 +       return platform_driver_register(&spiflash_driver);
 532 +}
 533 +
 534 +void __exit
 535 +spiflash_exit (void)
 536 +{
 537 +       return platform_driver_unregister(&spiflash_driver);
 538 +}
 539 +
 540 +module_init (spiflash_init);
 541 +module_exit (spiflash_exit);
 542 +
 543 +MODULE_LICENSE("GPL");
 544 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
 545 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
 546 +
 547 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
 548 ===================================================================
 549 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 550 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h  2010-02-03 17:01:08.858429535 +0100
 551 @@ -0,0 +1,116 @@
 552 +/*
 553 + * SPI Flash Memory support header file.
 554 + *
 555 + * Copyright (c) 2005, Atheros Communications Inc.
 556 + * Copyright (C) 2006 FON Technology, SL.
 557 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 558 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
 559 + *
 560 + * This code is free software; you can redistribute it and/or modify
 561 + * it under the terms of the GNU General Public License version 2 as
 562 + * published by the Free Software Foundation.
 563 + *
 564 + */
 565 +#ifndef __AR2315_SPIFLASH_H
 566 +#define __AR2315_SPIFLASH_H
 567 +
 568 +#define STM_PAGE_SIZE           256
 569 +
 570 +#define SFI_WRITE_BUFFER_SIZE   4
 571 +#define SFI_FLASH_ADDR_MASK     0x00ffffff
 572 +
 573 +#define STM_8MBIT_SIGNATURE     0x13
 574 +#define STM_M25P80_BYTE_COUNT   1048576
 575 +#define STM_M25P80_SECTOR_COUNT 16
 576 +#define STM_M25P80_SECTOR_SIZE  0x10000
 577 +
 578 +#define STM_16MBIT_SIGNATURE    0x14
 579 +#define STM_M25P16_BYTE_COUNT   2097152
 580 +#define STM_M25P16_SECTOR_COUNT 32
 581 +#define STM_M25P16_SECTOR_SIZE  0x10000
 582 +
 583 +#define STM_32MBIT_SIGNATURE    0x15
 584 +#define STM_M25P32_BYTE_COUNT   4194304
 585 +#define STM_M25P32_SECTOR_COUNT 64
 586 +#define STM_M25P32_SECTOR_SIZE  0x10000
 587 +
 588 +#define STM_64MBIT_SIGNATURE    0x16
 589 +#define STM_M25P64_BYTE_COUNT   8388608
 590 +#define STM_M25P64_SECTOR_COUNT 128
 591 +#define STM_M25P64_SECTOR_SIZE  0x10000
 592 +
 593 +#define STM_128MBIT_SIGNATURE   0x17
 594 +#define STM_M25P128_BYTE_COUNT   16777216
 595 +#define STM_M25P128_SECTOR_COUNT 256
 596 +#define STM_M25P128_SECTOR_SIZE  0x10000
 597 +
 598 +#define STM_1MB_BYTE_COUNT   STM_M25P80_BYTE_COUNT
 599 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
 600 +#define STM_1MB_SECTOR_SIZE  STM_M25P80_SECTOR_SIZE
 601 +#define STM_2MB_BYTE_COUNT   STM_M25P16_BYTE_COUNT
 602 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
 603 +#define STM_2MB_SECTOR_SIZE  STM_M25P16_SECTOR_SIZE
 604 +#define STM_4MB_BYTE_COUNT   STM_M25P32_BYTE_COUNT
 605 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
 606 +#define STM_4MB_SECTOR_SIZE  STM_M25P32_SECTOR_SIZE
 607 +#define STM_8MB_BYTE_COUNT   STM_M25P64_BYTE_COUNT
 608 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
 609 +#define STM_8MB_SECTOR_SIZE  STM_M25P64_SECTOR_SIZE
 610 +#define STM_16MB_BYTE_COUNT   STM_M25P128_BYTE_COUNT
 611 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
 612 +#define STM_16MB_SECTOR_SIZE  STM_M25P128_SECTOR_SIZE
 613 +
 614 +/*
 615 + * ST Microelectronics Opcodes for Serial Flash
 616 + */
 617 +
 618 +#define STM_OP_WR_ENABLE       0x06     /* Write Enable */
 619 +#define STM_OP_WR_DISABLE      0x04     /* Write Disable */
 620 +#define STM_OP_RD_STATUS       0x05     /* Read Status */
 621 +#define STM_OP_WR_STATUS       0x01     /* Write Status */
 622 +#define STM_OP_RD_DATA         0x03     /* Read Data */
 623 +#define STM_OP_FAST_RD_DATA    0x0b     /* Fast Read Data */
 624 +#define STM_OP_PAGE_PGRM       0x02     /* Page Program */
 625 +#define STM_OP_SECTOR_ERASE    0xd8     /* Sector Erase */
 626 +#define STM_OP_BULK_ERASE      0xc7     /* Bulk Erase */
 627 +#define STM_OP_DEEP_PWRDOWN    0xb9     /* Deep Power-Down Mode */
 628 +#define STM_OP_RD_SIG          0xab     /* Read Electronic Signature */
 629 +
 630 +#define STM_STATUS_WIP       0x01       /* Write-In-Progress */
 631 +#define STM_STATUS_WEL       0x02       /* Write Enable Latch */
 632 +#define STM_STATUS_BP0       0x04       /* Block Protect 0 */
 633 +#define STM_STATUS_BP1       0x08       /* Block Protect 1 */
 634 +#define STM_STATUS_BP2       0x10       /* Block Protect 2 */
 635 +#define STM_STATUS_SRWD      0x80       /* Status Register Write Disable */
 636 +
 637 +/*
 638 + * SPI Flash Interface Registers
 639 + */
 640 +#define AR531XPLUS_SPI_READ     0x08000000
 641 +#define AR531XPLUS_SPI_MMR      0x11300000
 642 +#define AR531XPLUS_SPI_MMR_SIZE 12
 643 +
 644 +#define AR531XPLUS_SPI_CTL      0x00
 645 +#define AR531XPLUS_SPI_OPCODE   0x04
 646 +#define AR531XPLUS_SPI_DATA     0x08
 647 +
 648 +#define SPI_FLASH_READ          AR531XPLUS_SPI_READ
 649 +#define SPI_FLASH_MMR           AR531XPLUS_SPI_MMR
 650 +#define SPI_FLASH_MMR_SIZE      AR531XPLUS_SPI_MMR_SIZE
 651 +#define SPI_FLASH_CTL           AR531XPLUS_SPI_CTL
 652 +#define SPI_FLASH_OPCODE        AR531XPLUS_SPI_OPCODE
 653 +#define SPI_FLASH_DATA          AR531XPLUS_SPI_DATA
 654 +
 655 +#define SPI_CTL_START           0x00000100
 656 +#define SPI_CTL_BUSY            0x00010000
 657 +#define SPI_CTL_TXCNT_MASK      0x0000000f
 658 +#define SPI_CTL_RXCNT_MASK      0x000000f0
 659 +#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 660 +#define SPI_CTL_SIZE_MASK       0x00060000
 661 +
 662 +#define SPI_CTL_CLK_SEL_MASK    0x03000000
 663 +#define SPI_OPCODE_MASK         0x000000ff
 664 +
 665 +#define SPI_STATUS_WIP         STM_STATUS_WIP
 666 +
 667 +#endif