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ar71xx: add platform data for the RB750 NAND driver
[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
26
27 #include "common.h"
28 #include "dev-eth.h"
29
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
31
32 static struct resource ath79_mdio0_resources[] = {
33 {
34 .name = "mdio_base",
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
38 }
39 };
40
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
42
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
45 .id = 0,
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
48 .dev = {
49 .platform_data = &ath79_mdio0_data,
50 },
51 };
52
53 static struct resource ath79_mdio1_resources[] = {
54 {
55 .name = "mdio_base",
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
59 }
60 };
61
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
63
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
66 .id = 1,
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
69 .dev = {
70 .platform_data = &ath79_mdio1_data,
71 },
72 };
73
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
75 {
76 void __iomem *base;
77 u32 t;
78
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
80
81 t = __raw_readl(base + cfg_reg);
82 t &= ~(3 << shift);
83 t |= (2 << shift);
84 __raw_writel(t, base + cfg_reg);
85 udelay(100);
86
87 __raw_writel(pll_val, base + pll_reg);
88
89 t |= (3 << shift);
90 __raw_writel(t, base + cfg_reg);
91 udelay(100);
92
93 t &= ~(3 << shift);
94 __raw_writel(t, base + cfg_reg);
95 udelay(100);
96
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
99
100 iounmap(base);
101 }
102
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
104 unsigned int mii_if)
105 {
106 void __iomem *base;
107 u32 t;
108
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
110
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
115
116 iounmap(base);
117 }
118
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
120 {
121 void __iomem *base;
122 unsigned int mii_speed;
123 u32 t;
124
125 switch (speed) {
126 case SPEED_10:
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
128 break;
129 case SPEED_100:
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
131 break;
132 case SPEED_1000:
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
134 break;
135 default:
136 BUG();
137 }
138
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
140
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
145
146 iounmap(base);
147 }
148
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
150 {
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
153 unsigned int max_id;
154
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
158 max_id = 1;
159 else
160 max_id = 0;
161
162 if (id > max_id) {
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
164 return;
165 }
166
167 switch (ath79_soc) {
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
173 break;
174
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
178 if (id == 0) {
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
181 } else {
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
184 }
185 break;
186
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
191 /* fall through */
192 default:
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
195 break;
196 }
197
198 mdio_data->phy_mask = phy_mask;
199
200 switch (ath79_soc) {
201 case ATH79_SOC_AR7240:
202 case ATH79_SOC_AR7241:
203 case ATH79_SOC_AR9330:
204 case ATH79_SOC_AR9331:
205 mdio_data->is_ar7240 = 1;
206 break;
207
208 case ATH79_SOC_AR9341:
209 case ATH79_SOC_AR9342:
210 case ATH79_SOC_AR9344:
211 if (id == 1)
212 mdio_data->is_ar7240 = 1;
213 break;
214
215 default:
216 break;
217 }
218
219 platform_device_register(mdio_dev);
220 }
221
222 struct ath79_eth_pll_data ath79_eth0_pll_data;
223 struct ath79_eth_pll_data ath79_eth1_pll_data;
224
225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
226 {
227 struct ath79_eth_pll_data *pll_data;
228 u32 pll_val;
229
230 switch (mac) {
231 case 0:
232 pll_data = &ath79_eth0_pll_data;
233 break;
234 case 1:
235 pll_data = &ath79_eth1_pll_data;
236 break;
237 default:
238 BUG();
239 }
240
241 switch (speed) {
242 case SPEED_10:
243 pll_val = pll_data->pll_10;
244 break;
245 case SPEED_100:
246 pll_val = pll_data->pll_100;
247 break;
248 case SPEED_1000:
249 pll_val = pll_data->pll_1000;
250 break;
251 default:
252 BUG();
253 }
254
255 return pll_val;
256 }
257
258 static void ath79_set_speed_ge0(int speed)
259 {
260 u32 val = ath79_get_eth_pll(0, speed);
261
262 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263 val, AR71XX_ETH0_PLL_SHIFT);
264 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
265 }
266
267 static void ath79_set_speed_ge1(int speed)
268 {
269 u32 val = ath79_get_eth_pll(1, speed);
270
271 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272 val, AR71XX_ETH1_PLL_SHIFT);
273 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
274 }
275
276 static void ar7242_set_speed_ge0(int speed)
277 {
278 u32 val = ath79_get_eth_pll(0, speed);
279 void __iomem *base;
280
281 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
282 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
283 iounmap(base);
284 }
285
286 static void ar91xx_set_speed_ge0(int speed)
287 {
288 u32 val = ath79_get_eth_pll(0, speed);
289
290 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
291 val, AR913X_ETH0_PLL_SHIFT);
292 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
293 }
294
295 static void ar91xx_set_speed_ge1(int speed)
296 {
297 u32 val = ath79_get_eth_pll(1, speed);
298
299 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
300 val, AR913X_ETH1_PLL_SHIFT);
301 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
302 }
303
304 static void ar934x_set_speed_ge0(int speed)
305 {
306 void __iomem *base;
307 u32 val = ath79_get_eth_pll(0, speed);
308
309 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
310 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
311 iounmap(base);
312 }
313
314 static void ath79_set_speed_dummy(int speed)
315 {
316 }
317
318 static void ath79_ddr_no_flush(void)
319 {
320 }
321
322 static void ath79_ddr_flush_ge0(void)
323 {
324 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
325 }
326
327 static void ath79_ddr_flush_ge1(void)
328 {
329 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
330 }
331
332 static void ar724x_ddr_flush_ge0(void)
333 {
334 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
335 }
336
337 static void ar724x_ddr_flush_ge1(void)
338 {
339 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
340 }
341
342 static void ar91xx_ddr_flush_ge0(void)
343 {
344 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
345 }
346
347 static void ar91xx_ddr_flush_ge1(void)
348 {
349 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
350 }
351
352 static void ar933x_ddr_flush_ge0(void)
353 {
354 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
355 }
356
357 static void ar933x_ddr_flush_ge1(void)
358 {
359 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
360 }
361
362 static struct resource ath79_eth0_resources[] = {
363 {
364 .name = "mac_base",
365 .flags = IORESOURCE_MEM,
366 .start = AR71XX_GE0_BASE,
367 .end = AR71XX_GE0_BASE + 0x200 - 1,
368 }, {
369 .name = "mac_irq",
370 .flags = IORESOURCE_IRQ,
371 .start = ATH79_CPU_IRQ_GE0,
372 .end = ATH79_CPU_IRQ_GE0,
373 },
374 };
375
376 struct ag71xx_platform_data ath79_eth0_data = {
377 .reset_bit = AR71XX_RESET_GE0_MAC,
378 };
379
380 struct platform_device ath79_eth0_device = {
381 .name = "ag71xx",
382 .id = 0,
383 .resource = ath79_eth0_resources,
384 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
385 .dev = {
386 .platform_data = &ath79_eth0_data,
387 },
388 };
389
390 static struct resource ath79_eth1_resources[] = {
391 {
392 .name = "mac_base",
393 .flags = IORESOURCE_MEM,
394 .start = AR71XX_GE1_BASE,
395 .end = AR71XX_GE1_BASE + 0x200 - 1,
396 }, {
397 .name = "mac_irq",
398 .flags = IORESOURCE_IRQ,
399 .start = ATH79_CPU_IRQ_GE1,
400 .end = ATH79_CPU_IRQ_GE1,
401 },
402 };
403
404 struct ag71xx_platform_data ath79_eth1_data = {
405 .reset_bit = AR71XX_RESET_GE1_MAC,
406 };
407
408 struct platform_device ath79_eth1_device = {
409 .name = "ag71xx",
410 .id = 1,
411 .resource = ath79_eth1_resources,
412 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
413 .dev = {
414 .platform_data = &ath79_eth1_data,
415 },
416 };
417
418 struct ag71xx_switch_platform_data ath79_switch_data;
419
420 #define AR71XX_PLL_VAL_1000 0x00110000
421 #define AR71XX_PLL_VAL_100 0x00001099
422 #define AR71XX_PLL_VAL_10 0x00991099
423
424 #define AR724X_PLL_VAL_1000 0x00110000
425 #define AR724X_PLL_VAL_100 0x00001099
426 #define AR724X_PLL_VAL_10 0x00991099
427
428 #define AR7242_PLL_VAL_1000 0x16000000
429 #define AR7242_PLL_VAL_100 0x00000101
430 #define AR7242_PLL_VAL_10 0x00001616
431
432 #define AR913X_PLL_VAL_1000 0x1a000000
433 #define AR913X_PLL_VAL_100 0x13000a44
434 #define AR913X_PLL_VAL_10 0x00441099
435
436 #define AR933X_PLL_VAL_1000 0x00110000
437 #define AR933X_PLL_VAL_100 0x00001099
438 #define AR933X_PLL_VAL_10 0x00991099
439
440 #define AR934X_PLL_VAL_1000 0x16000000
441 #define AR934X_PLL_VAL_100 0x00000101
442 #define AR934X_PLL_VAL_10 0x00001616
443
444 static void __init ath79_init_eth_pll_data(unsigned int id)
445 {
446 struct ath79_eth_pll_data *pll_data;
447 u32 pll_10, pll_100, pll_1000;
448
449 switch (id) {
450 case 0:
451 pll_data = &ath79_eth0_pll_data;
452 break;
453 case 1:
454 pll_data = &ath79_eth1_pll_data;
455 break;
456 default:
457 BUG();
458 }
459
460 switch (ath79_soc) {
461 case ATH79_SOC_AR7130:
462 case ATH79_SOC_AR7141:
463 case ATH79_SOC_AR7161:
464 pll_10 = AR71XX_PLL_VAL_10;
465 pll_100 = AR71XX_PLL_VAL_100;
466 pll_1000 = AR71XX_PLL_VAL_1000;
467 break;
468
469 case ATH79_SOC_AR7240:
470 case ATH79_SOC_AR7241:
471 pll_10 = AR724X_PLL_VAL_10;
472 pll_100 = AR724X_PLL_VAL_100;
473 pll_1000 = AR724X_PLL_VAL_1000;
474 break;
475
476 case ATH79_SOC_AR7242:
477 pll_10 = AR7242_PLL_VAL_10;
478 pll_100 = AR7242_PLL_VAL_100;
479 pll_1000 = AR7242_PLL_VAL_1000;
480 break;
481
482 case ATH79_SOC_AR9130:
483 case ATH79_SOC_AR9132:
484 pll_10 = AR913X_PLL_VAL_10;
485 pll_100 = AR913X_PLL_VAL_100;
486 pll_1000 = AR913X_PLL_VAL_1000;
487 break;
488
489 case ATH79_SOC_AR9330:
490 case ATH79_SOC_AR9331:
491 pll_10 = AR933X_PLL_VAL_10;
492 pll_100 = AR933X_PLL_VAL_100;
493 pll_1000 = AR933X_PLL_VAL_1000;
494 break;
495
496 case ATH79_SOC_AR9341:
497 case ATH79_SOC_AR9342:
498 case ATH79_SOC_AR9344:
499 pll_10 = AR934X_PLL_VAL_10;
500 pll_100 = AR934X_PLL_VAL_100;
501 pll_1000 = AR934X_PLL_VAL_1000;
502 break;
503
504 default:
505 BUG();
506 }
507
508 if (!pll_data->pll_10)
509 pll_data->pll_10 = pll_10;
510
511 if (!pll_data->pll_100)
512 pll_data->pll_100 = pll_100;
513
514 if (!pll_data->pll_1000)
515 pll_data->pll_1000 = pll_1000;
516 }
517
518 static int __init ath79_setup_phy_if_mode(unsigned int id,
519 struct ag71xx_platform_data *pdata)
520 {
521 unsigned int mii_if;
522
523 switch (id) {
524 case 0:
525 switch (ath79_soc) {
526 case ATH79_SOC_AR7130:
527 case ATH79_SOC_AR7141:
528 case ATH79_SOC_AR7161:
529 case ATH79_SOC_AR9130:
530 case ATH79_SOC_AR9132:
531 switch (pdata->phy_if_mode) {
532 case PHY_INTERFACE_MODE_MII:
533 mii_if = AR71XX_MII0_CTRL_IF_MII;
534 break;
535 case PHY_INTERFACE_MODE_GMII:
536 mii_if = AR71XX_MII0_CTRL_IF_GMII;
537 break;
538 case PHY_INTERFACE_MODE_RGMII:
539 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
540 break;
541 case PHY_INTERFACE_MODE_RMII:
542 mii_if = AR71XX_MII0_CTRL_IF_RMII;
543 break;
544 default:
545 return -EINVAL;
546 }
547 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
548 break;
549
550 case ATH79_SOC_AR7240:
551 case ATH79_SOC_AR7241:
552 case ATH79_SOC_AR9330:
553 case ATH79_SOC_AR9331:
554 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
555 break;
556
557 case ATH79_SOC_AR7242:
558 /* FIXME */
559
560 case ATH79_SOC_AR9341:
561 case ATH79_SOC_AR9342:
562 case ATH79_SOC_AR9344:
563 switch (pdata->phy_if_mode) {
564 case PHY_INTERFACE_MODE_MII:
565 case PHY_INTERFACE_MODE_GMII:
566 case PHY_INTERFACE_MODE_RGMII:
567 case PHY_INTERFACE_MODE_RMII:
568 break;
569 default:
570 return -EINVAL;
571 }
572 break;
573
574 default:
575 BUG();
576 }
577 break;
578 case 1:
579 switch (ath79_soc) {
580 case ATH79_SOC_AR7130:
581 case ATH79_SOC_AR7141:
582 case ATH79_SOC_AR7161:
583 case ATH79_SOC_AR9130:
584 case ATH79_SOC_AR9132:
585 switch (pdata->phy_if_mode) {
586 case PHY_INTERFACE_MODE_RMII:
587 mii_if = AR71XX_MII1_CTRL_IF_RMII;
588 break;
589 case PHY_INTERFACE_MODE_RGMII:
590 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
591 break;
592 default:
593 return -EINVAL;
594 }
595 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
596 break;
597
598 case ATH79_SOC_AR7240:
599 case ATH79_SOC_AR7241:
600 case ATH79_SOC_AR9330:
601 case ATH79_SOC_AR9331:
602 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
603 break;
604
605 case ATH79_SOC_AR7242:
606 /* FIXME */
607
608 case ATH79_SOC_AR9341:
609 case ATH79_SOC_AR9342:
610 case ATH79_SOC_AR9344:
611 switch (pdata->phy_if_mode) {
612 case PHY_INTERFACE_MODE_MII:
613 case PHY_INTERFACE_MODE_GMII:
614 break;
615 default:
616 return -EINVAL;
617 }
618 break;
619
620 default:
621 BUG();
622 }
623 break;
624 }
625
626 return 0;
627 }
628
629 static int ath79_eth_instance __initdata;
630 void __init ath79_register_eth(unsigned int id)
631 {
632 struct platform_device *pdev;
633 struct ag71xx_platform_data *pdata;
634 int err;
635
636 if (id > 1) {
637 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
638 return;
639 }
640
641 ath79_init_eth_pll_data(id);
642
643 if (id == 0)
644 pdev = &ath79_eth0_device;
645 else
646 pdev = &ath79_eth1_device;
647
648 pdata = pdev->dev.platform_data;
649
650 err = ath79_setup_phy_if_mode(id, pdata);
651 if (err) {
652 printk(KERN_ERR
653 "ar71xx: invalid PHY interface mode for GE%u\n", id);
654 return;
655 }
656
657 switch (ath79_soc) {
658 case ATH79_SOC_AR7130:
659 if (id == 0) {
660 pdata->ddr_flush = ath79_ddr_flush_ge0;
661 pdata->set_speed = ath79_set_speed_ge0;
662 } else {
663 pdata->ddr_flush = ath79_ddr_flush_ge1;
664 pdata->set_speed = ath79_set_speed_ge1;
665 }
666 break;
667
668 case ATH79_SOC_AR7141:
669 case ATH79_SOC_AR7161:
670 if (id == 0) {
671 pdata->ddr_flush = ath79_ddr_flush_ge0;
672 pdata->set_speed = ath79_set_speed_ge0;
673 } else {
674 pdata->ddr_flush = ath79_ddr_flush_ge1;
675 pdata->set_speed = ath79_set_speed_ge1;
676 }
677 pdata->has_gbit = 1;
678 break;
679
680 case ATH79_SOC_AR7242:
681 if (id == 0) {
682 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
683 AR71XX_RESET_GE0_PHY;
684 pdata->ddr_flush = ar724x_ddr_flush_ge0;
685 pdata->set_speed = ar7242_set_speed_ge0;
686 } else {
687 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
688 AR71XX_RESET_GE1_PHY;
689 pdata->ddr_flush = ar724x_ddr_flush_ge1;
690 pdata->set_speed = ath79_set_speed_dummy;
691 }
692 pdata->has_gbit = 1;
693 pdata->is_ar724x = 1;
694
695 if (!pdata->fifo_cfg1)
696 pdata->fifo_cfg1 = 0x0010ffff;
697 if (!pdata->fifo_cfg2)
698 pdata->fifo_cfg2 = 0x015500aa;
699 if (!pdata->fifo_cfg3)
700 pdata->fifo_cfg3 = 0x01f00140;
701 break;
702
703 case ATH79_SOC_AR7241:
704 if (id == 0)
705 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
706 else
707 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
708 /* fall through */
709 case ATH79_SOC_AR7240:
710 if (id == 0) {
711 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
712 pdata->ddr_flush = ar724x_ddr_flush_ge0;
713 pdata->set_speed = ath79_set_speed_dummy;
714
715 pdata->phy_mask = BIT(4);
716 } else {
717 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
718 pdata->ddr_flush = ar724x_ddr_flush_ge1;
719 pdata->set_speed = ath79_set_speed_dummy;
720
721 pdata->speed = SPEED_1000;
722 pdata->duplex = DUPLEX_FULL;
723 pdata->switch_data = &ath79_switch_data;
724 }
725 pdata->has_gbit = 1;
726 pdata->is_ar724x = 1;
727 if (ath79_soc == ATH79_SOC_AR7240)
728 pdata->is_ar7240 = 1;
729
730 if (!pdata->fifo_cfg1)
731 pdata->fifo_cfg1 = 0x0010ffff;
732 if (!pdata->fifo_cfg2)
733 pdata->fifo_cfg2 = 0x015500aa;
734 if (!pdata->fifo_cfg3)
735 pdata->fifo_cfg3 = 0x01f00140;
736 break;
737
738 case ATH79_SOC_AR9130:
739 if (id == 0) {
740 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
741 pdata->set_speed = ar91xx_set_speed_ge0;
742 } else {
743 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
744 pdata->set_speed = ar91xx_set_speed_ge1;
745 }
746 pdata->is_ar91xx = 1;
747 break;
748
749 case ATH79_SOC_AR9132:
750 if (id == 0) {
751 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
752 pdata->set_speed = ar91xx_set_speed_ge0;
753 } else {
754 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
755 pdata->set_speed = ar91xx_set_speed_ge1;
756 }
757 pdata->is_ar91xx = 1;
758 pdata->has_gbit = 1;
759 break;
760
761 case ATH79_SOC_AR9330:
762 case ATH79_SOC_AR9331:
763 if (id == 0) {
764 pdata->reset_bit = AR933X_RESET_GE0_MAC |
765 AR933X_RESET_GE0_MDIO;
766 pdata->ddr_flush = ar933x_ddr_flush_ge0;
767 pdata->set_speed = ath79_set_speed_dummy;
768
769 pdata->phy_mask = BIT(4);
770 } else {
771 pdata->reset_bit = AR933X_RESET_GE1_MAC |
772 AR933X_RESET_GE1_MDIO;
773 pdata->ddr_flush = ar933x_ddr_flush_ge1;
774 pdata->set_speed = ath79_set_speed_dummy;
775
776 pdata->speed = SPEED_1000;
777 pdata->duplex = DUPLEX_FULL;
778 pdata->switch_data = &ath79_switch_data;
779 }
780
781 pdata->has_gbit = 1;
782 pdata->is_ar724x = 1;
783
784 if (!pdata->fifo_cfg1)
785 pdata->fifo_cfg1 = 0x0010ffff;
786 if (!pdata->fifo_cfg2)
787 pdata->fifo_cfg2 = 0x015500aa;
788 if (!pdata->fifo_cfg3)
789 pdata->fifo_cfg3 = 0x01f00140;
790 break;
791
792 case ATH79_SOC_AR9341:
793 case ATH79_SOC_AR9342:
794 case ATH79_SOC_AR9344:
795 if (id == 0) {
796 pdata->reset_bit = AR934X_RESET_GE0_MAC |
797 AR934X_RESET_GE0_MDIO;
798 pdata->set_speed = ar934x_set_speed_ge0;
799 } else {
800 pdata->reset_bit = AR934X_RESET_GE1_MAC |
801 AR934X_RESET_GE1_MDIO;
802 pdata->set_speed = ath79_set_speed_dummy;
803
804 pdata->switch_data = &ath79_switch_data;
805
806 /* reset the built-in switch */
807 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
808 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
809 }
810
811 pdata->ddr_flush = ath79_ddr_no_flush;
812 pdata->has_gbit = 1;
813 pdata->is_ar724x = 1;
814
815 if (!pdata->fifo_cfg1)
816 pdata->fifo_cfg1 = 0x0010ffff;
817 if (!pdata->fifo_cfg2)
818 pdata->fifo_cfg2 = 0x015500aa;
819 if (!pdata->fifo_cfg3)
820 pdata->fifo_cfg3 = 0x01f00140;
821 break;
822
823 default:
824 BUG();
825 }
826
827 switch (pdata->phy_if_mode) {
828 case PHY_INTERFACE_MODE_GMII:
829 case PHY_INTERFACE_MODE_RGMII:
830 if (!pdata->has_gbit) {
831 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
832 id);
833 return;
834 }
835 /* fallthrough */
836 default:
837 break;
838 }
839
840 if (!is_valid_ether_addr(pdata->mac_addr)) {
841 random_ether_addr(pdata->mac_addr);
842 printk(KERN_DEBUG
843 "ar71xx: using random MAC address for eth%d\n",
844 ath79_eth_instance);
845 }
846
847 if (pdata->mii_bus_dev == NULL) {
848 switch (ath79_soc) {
849 case ATH79_SOC_AR9341:
850 case ATH79_SOC_AR9342:
851 case ATH79_SOC_AR9344:
852 if (id == 0)
853 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
854 else
855 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
856 break;
857
858 case ATH79_SOC_AR7241:
859 case ATH79_SOC_AR9330:
860 case ATH79_SOC_AR9331:
861 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
862 break;
863
864 default:
865 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
866 break;
867 }
868 }
869
870 /* Reset the device */
871 ath79_device_reset_set(pdata->reset_bit);
872 mdelay(100);
873
874 ath79_device_reset_clear(pdata->reset_bit);
875 mdelay(100);
876
877 platform_device_register(pdev);
878 ath79_eth_instance++;
879 }
880
881 void __init ath79_set_mac_base(unsigned char *mac)
882 {
883 memcpy(ath79_mac_base, mac, ETH_ALEN);
884 }
885
886 void __init ath79_parse_mac_addr(char *mac_str)
887 {
888 u8 tmp[ETH_ALEN];
889 int t;
890
891 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
892 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
893
894 if (t != ETH_ALEN)
895 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
896 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
897
898 if (t == ETH_ALEN)
899 ath79_set_mac_base(tmp);
900 else
901 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
902 "\"%s\"\n", mac_str);
903 }
904
905 static int __init ath79_ethaddr_setup(char *str)
906 {
907 ath79_parse_mac_addr(str);
908 return 1;
909 }
910 __setup("ethaddr=", ath79_ethaddr_setup);
911
912 static int __init ath79_kmac_setup(char *str)
913 {
914 ath79_parse_mac_addr(str);
915 return 1;
916 }
917 __setup("kmac=", ath79_kmac_setup);
918
919 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
920 int offset)
921 {
922 int t;
923
924 if (!is_valid_ether_addr(src)) {
925 memset(dst, '\0', ETH_ALEN);
926 return;
927 }
928
929 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
930 t += offset;
931
932 dst[0] = src[0];
933 dst[1] = src[1];
934 dst[2] = src[2];
935 dst[3] = (t >> 16) & 0xff;
936 dst[4] = (t >> 8) & 0xff;
937 dst[5] = t & 0xff;
938 }
939
940 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
941 {
942 int i;
943
944 if (!is_valid_ether_addr(src)) {
945 memset(dst, '\0', ETH_ALEN);
946 return;
947 }
948
949 for (i = 0; i < ETH_ALEN; i++)
950 dst[i] = src[i];
951 dst[0] |= 0x02;
952 }
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