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generic: generic: remove MIPS device tree backport patch from 2.6.36
[openwrt.git] / package / uboot-xburst / files / cpu / mips / jz_mmc.c
1 /*
2 * (C) Copyright 2003
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <config.h>
25 #include <common.h>
26 #include <part.h>
27
28 #if defined CONFIG_JZ4740
29 #include <asm-mips/jz4740.h>
30
31 #include "jz_mmc.h"
32
33 #define CFG_MMC_BASE 0x80600000
34 static int sd2_0 = 0;
35
36 /*
37 * GPIO definition
38 */
39 #if defined(CONFIG_SAKC)
40
41 #define __msc_init_io() \
42 do { \
43 __gpio_as_input(GPIO_SD_CD_N); \
44 } while (0)
45
46 #else
47 #define __msc_init_io() \
48 do { \
49 __gpio_as_output(GPIO_SD_VCC_EN_N); \
50 __gpio_as_input(GPIO_SD_CD_N); \
51 } while (0)
52
53 #define __msc_enable_power() \
54 do { \
55 __gpio_clear_pin(GPIO_SD_VCC_EN_N); \
56 } while (0)
57
58 #define __msc_disable_power() \
59 do { \
60 __gpio_set_pin(GPIO_SD_VCC_EN_N); \
61 } while (0)
62
63 #endif /* CONFIG_SAKE */
64
65 #define __msc_card_detected() \
66 ({ \
67 int detected = 1; \
68 __gpio_as_input(GPIO_SD_CD_N); \
69 __gpio_disable_pull(GPIO_SD_CD_N); \
70 if (!__gpio_get_pin(GPIO_SD_CD_N)) \
71 detected = 0; \
72 detected; \
73 })
74
75 /*
76 * Local functions
77 */
78
79 #ifdef CONFIG_MMC
80 extern int
81 fat_register_device(block_dev_desc_t *dev_desc, int part_no);
82
83 static block_dev_desc_t mmc_dev;
84
85 block_dev_desc_t * mmc_get_dev(int dev)
86 {
87 return ((block_dev_desc_t *)&mmc_dev);
88 }
89
90 /*
91 * FIXME needs to read cid and csd info to determine block size
92 * and other parameters
93 */
94 static uchar mmc_buf[MMC_BLOCK_SIZE];
95 static int mmc_ready = 0;
96 static mmc_csd_t mmc_csd;
97 static int use_4bit; /* Use 4-bit data bus */
98 /*
99 * MMC Events
100 */
101 #define MMC_EVENT_NONE 0x00 /* No events */
102 #define MMC_EVENT_RX_DATA_DONE 0x01 /* Rx data done */
103 #define MMC_EVENT_TX_DATA_DONE 0x02 /* Tx data done */
104 #define MMC_EVENT_PROG_DONE 0x04 /* Programming is done */
105
106
107 #define MMC_IRQ_MASK() \
108 do { \
109 REG_MSC_IMASK = 0xffff; \
110 REG_MSC_IREG = 0xffff; \
111 } while (0)
112
113 /* Stop the MMC clock and wait while it happens */
114 static inline int jz_mmc_stop_clock(void)
115 {
116 int timeout = 1000;
117
118 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
119
120 while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
121 timeout--;
122 if (timeout == 0) {
123 return MMC_ERROR_TIMEOUT;
124 }
125 udelay(1);
126 }
127 return MMC_NO_ERROR;
128 }
129
130 /* Start the MMC clock and operation */
131 static inline int jz_mmc_start_clock(void)
132 {
133 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
134 return MMC_NO_ERROR;
135 }
136
137 static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
138 {
139 u32 clkrt;
140 u32 clk_src = is_sd ? 24000000: 16000000;
141
142 clkrt = 0;
143 while (rate < clk_src)
144 {
145 clkrt ++;
146 clk_src >>= 1;
147 }
148 return clkrt;
149 }
150
151 /* Set the MMC clock frequency */
152 void jz_mmc_set_clock(int sd, u32 rate)
153 {
154 jz_mmc_stop_clock();
155
156 /* Select clock source of MSC */
157 __cpm_select_msc_clk(sd);
158
159 /* Set clock dividor of MSC */
160 REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate);
161 }
162
163 static int jz_mmc_check_status(struct mmc_request *request)
164 {
165 u32 status = REG_MSC_STAT;
166
167 /* Checking for response or data timeout */
168 if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) {
169 printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd);
170 return MMC_ERROR_TIMEOUT;
171 }
172
173 /* Checking for CRC error */
174 if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) {
175 printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status);
176 return MMC_ERROR_CRC;
177 }
178
179 return MMC_NO_ERROR;
180 }
181
182 /* Obtain response to the command and store it to response buffer */
183 static void jz_mmc_get_response(struct mmc_request *request)
184 {
185 int i;
186 u8 *buf;
187 u32 data;
188
189 DEBUG(3, "fetch response for request %d, cmd %d\n", request->rtype, request->cmd);
190
191 buf = request->response;
192 request->result = MMC_NO_ERROR;
193
194 switch (request->rtype) {
195 case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6:
196 case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5:
197 {
198 data = REG_MSC_RES;
199 buf[0] = (data >> 8) & 0xff;
200 buf[1] = data & 0xff;
201 data = REG_MSC_RES;
202 buf[2] = (data >> 8) & 0xff;
203 buf[3] = data & 0xff;
204 data = REG_MSC_RES;
205 buf[4] = data & 0xff;
206
207 DEBUG(3, "request %d, response [%02x %02x %02x %02x %02x]\n",
208 request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]);
209 break;
210 }
211 case RESPONSE_R2_CID: case RESPONSE_R2_CSD:
212 {
213 for (i = 0; i < 16; i += 2) {
214 data = REG_MSC_RES;
215 buf[i] = (data >> 8) & 0xff;
216 buf[i+1] = data & 0xff;
217 }
218 DEBUG(3, "request %d, response [", request->rtype);
219 #if CONFIG_MMC_DEBUG_VERBOSE > 2
220 if (g_mmc_debug >= 3) {
221 int n;
222 for (n = 0; n < 17; n++)
223 printk("%02x ", buf[n]);
224 printk("]\n");
225 }
226 #endif
227 break;
228 }
229 case RESPONSE_NONE:
230 DEBUG(3, "No response\n");
231 break;
232
233 default:
234 DEBUG(3, "unhandled response type for request %d\n", request->rtype);
235 break;
236 }
237 }
238
239 static int jz_mmc_receive_data(struct mmc_request *req)
240 {
241 u32 stat, timeout, data, cnt;
242 u8 *buf = req->buffer;
243 u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
244
245 timeout = 0x3ffffff;
246
247 while (timeout) {
248 timeout--;
249 stat = REG_MSC_STAT;
250
251 if (stat & MSC_STAT_TIME_OUT_READ)
252 return MMC_ERROR_TIMEOUT;
253 else if (stat & MSC_STAT_CRC_READ_ERROR)
254 return MMC_ERROR_CRC;
255 else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
256 || (stat & MSC_STAT_DATA_FIFO_AFULL)) {
257 /* Ready to read data */
258 break;
259 }
260 udelay(1);
261 }
262 if (!timeout)
263 return MMC_ERROR_TIMEOUT;
264
265 /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
266 cnt = wblocklen;
267 while (cnt) {
268 data = REG_MSC_RXFIFO;
269 {
270 *buf++ = (u8)(data >> 0);
271 *buf++ = (u8)(data >> 8);
272 *buf++ = (u8)(data >> 16);
273 *buf++ = (u8)(data >> 24);
274 }
275 cnt --;
276 while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY))
277 ;
278 }
279 return MMC_NO_ERROR;
280 }
281
282 static int jz_mmc_transmit_data(struct mmc_request *req)
283 {
284 #if 0
285 u32 nob = req->nob;
286 u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
287 u8 *buf = req->buffer;
288 u32 *wbuf = (u32 *)buf;
289 u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */
290 u32 stat, timeout, data, cnt;
291
292 for (nob; nob >= 1; nob--) {
293 timeout = 0x3FFFFFF;
294
295 while (timeout) {
296 timeout--;
297 stat = REG_MSC_STAT;
298
299 if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS))
300 return MMC_ERROR_CRC;
301 else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) {
302 /* Ready to write data */
303 break;
304 }
305
306 udelay(1);
307 }
308
309 if (!timeout)
310 return MMC_ERROR_TIMEOUT;
311
312 /* Write data to TXFIFO */
313 cnt = wblocklen;
314 while (cnt) {
315 while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL)
316 ;
317
318 if (waligned) {
319 REG_MSC_TXFIFO = *wbuf++;
320 }
321 else {
322 data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24);
323 REG_MSC_TXFIFO = data;
324 }
325
326 cnt--;
327 }
328 }
329 #endif
330 return MMC_NO_ERROR;
331 }
332
333
334 /*
335 * Name: int jz_mmc_exec_cmd()
336 * Function: send command to the card, and get a response
337 * Input: struct mmc_request *req : MMC/SD request
338 * Output: 0: right >0: error code
339 */
340 int jz_mmc_exec_cmd(struct mmc_request *request)
341 {
342 u32 cmdat = 0, events = 0;
343 int retval, timeout = 0x3fffff;
344
345 /* Indicate we have no result yet */
346 request->result = MMC_NO_RESPONSE;
347 if (request->cmd == MMC_CIM_RESET) {
348 /* On reset, 1-bit bus width */
349 use_4bit = 0;
350
351 /* Reset MMC/SD controller */
352 __msc_reset();
353
354 /* On reset, drop MMC clock down */
355 jz_mmc_set_clock(0, MMC_CLOCK_SLOW);
356
357 /* On reset, stop MMC clock */
358 jz_mmc_stop_clock();
359 }
360 if (request->cmd == MMC_SEND_OP_COND) {
361 DEBUG(3, "Have an MMC card\n");
362 /* always use 1bit for MMC */
363 use_4bit = 0;
364 }
365 if (request->cmd == SET_BUS_WIDTH) {
366 if (request->arg == 0x2) {
367 printf("Use 4-bit bus width\n");
368 use_4bit = 1;
369 }
370 else {
371 printf("Use 1-bit bus width\n");
372 use_4bit = 0;
373 }
374 }
375
376 /* stop clock */
377 jz_mmc_stop_clock();
378
379 /* mask all interrupts */
380 REG_MSC_IMASK = 0xffff;
381
382 /* clear status */
383 REG_MSC_IREG = 0xffff;
384
385 /* use 4-bit bus width when possible */
386 if (use_4bit)
387 cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
388
389 /* Set command type and events */
390 switch (request->cmd) {
391 /* MMC core extra command */
392 case MMC_CIM_RESET:
393 cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
394 break;
395
396 /* bc - broadcast - no response */
397 case MMC_GO_IDLE_STATE:
398 case MMC_SET_DSR:
399 break;
400
401 /* bcr - broadcast with response */
402 case MMC_SEND_OP_COND:
403 case MMC_ALL_SEND_CID:
404 case MMC_GO_IRQ_STATE:
405 break;
406
407 /* adtc - addressed with data transfer */
408 case MMC_READ_DAT_UNTIL_STOP:
409 case MMC_READ_SINGLE_BLOCK:
410 case MMC_READ_MULTIPLE_BLOCK:
411 case SEND_SCR:
412 cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
413 events = MMC_EVENT_RX_DATA_DONE;
414 break;
415
416 case MMC_WRITE_DAT_UNTIL_STOP:
417 case MMC_WRITE_BLOCK:
418 case MMC_WRITE_MULTIPLE_BLOCK:
419 case MMC_PROGRAM_CID:
420 case MMC_PROGRAM_CSD:
421 case MMC_SEND_WRITE_PROT:
422 case MMC_GEN_CMD:
423 case MMC_LOCK_UNLOCK:
424 cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
425 events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE;
426
427 break;
428
429 case MMC_STOP_TRANSMISSION:
430 events = MMC_EVENT_PROG_DONE;
431 break;
432
433 /* ac - no data transfer */
434 default:
435 break;
436 }
437
438 /* Set response type */
439 switch (request->rtype) {
440 case RESPONSE_NONE:
441 break;
442
443 case RESPONSE_R1B:
444 cmdat |= MSC_CMDAT_BUSY;
445 /*FALLTHRU*/
446 case RESPONSE_R1:
447 cmdat |= MSC_CMDAT_RESPONSE_R1;
448 break;
449 case RESPONSE_R2_CID:
450 case RESPONSE_R2_CSD:
451 cmdat |= MSC_CMDAT_RESPONSE_R2;
452 break;
453 case RESPONSE_R3:
454 cmdat |= MSC_CMDAT_RESPONSE_R3;
455 break;
456 case RESPONSE_R4:
457 cmdat |= MSC_CMDAT_RESPONSE_R4;
458 break;
459 case RESPONSE_R5:
460 cmdat |= MSC_CMDAT_RESPONSE_R5;
461 break;
462 case RESPONSE_R6:
463 cmdat |= MSC_CMDAT_RESPONSE_R6;
464 break;
465 default:
466 break;
467 }
468
469 /* Set command index */
470 if (request->cmd == MMC_CIM_RESET) {
471 REG_MSC_CMD = MMC_GO_IDLE_STATE;
472 } else {
473 REG_MSC_CMD = request->cmd;
474 }
475
476 /* Set argument */
477 REG_MSC_ARG = request->arg;
478
479 /* Set block length and nob */
480 if (request->cmd == SEND_SCR) { /* get SCR from DataFIFO */
481 REG_MSC_BLKLEN = 8;
482 REG_MSC_NOB = 1;
483 } else {
484 REG_MSC_BLKLEN = request->block_len;
485 REG_MSC_NOB = request->nob;
486 }
487
488 /* Set command */
489 REG_MSC_CMDAT = cmdat;
490
491 DEBUG(1, "Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd,
492 cmdat, request->arg, request->rtype);
493
494 /* Start MMC/SD clock and send command to card */
495 jz_mmc_start_clock();
496
497 /* Wait for command completion */
498 while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES))
499 ;
500
501 if (timeout == 0)
502 return MMC_ERROR_TIMEOUT;
503
504 REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */
505
506 /* Check for status */
507 retval = jz_mmc_check_status(request);
508 if (retval) {
509 return retval;
510 }
511
512 /* Complete command with no response */
513 if (request->rtype == RESPONSE_NONE) {
514 return MMC_NO_ERROR;
515 }
516
517 /* Get response */
518 jz_mmc_get_response(request);
519
520 /* Start data operation */
521 if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) {
522 if (events & MMC_EVENT_RX_DATA_DONE) {
523 if (request->cmd == SEND_SCR) {
524 /* SD card returns SCR register as data.
525 MMC core expect it in the response buffer,
526 after normal response. */
527 request->buffer = (u8 *)((u32)request->response + 5);
528 }
529 jz_mmc_receive_data(request);
530 }
531
532 if (events & MMC_EVENT_TX_DATA_DONE) {
533 jz_mmc_transmit_data(request);
534 }
535
536 /* Wait for Data Done */
537 while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE))
538 ;
539 REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
540 }
541
542 /* Wait for Prog Done event */
543 if (events & MMC_EVENT_PROG_DONE) {
544 while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE))
545 ;
546 REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
547 }
548
549 /* Command completed */
550
551 return MMC_NO_ERROR; /* return successfully */
552 }
553
554 int mmc_block_read(u8 *dst, ulong src, ulong len)
555 {
556
557 struct mmc_request request;
558 struct mmc_response_r1 r1;
559 int retval;
560
561 if (len == 0) {
562 return 0;
563 }
564 mmc_simple_cmd(&request, MMC_SEND_STATUS, mmcinfo.rca, RESPONSE_R1);
565 retval = mmc_unpack_r1(&request, &r1, 0);
566 if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) {
567 return retval;
568 }
569
570 mmc_simple_cmd(&request, MMC_SET_BLOCKLEN, len, RESPONSE_R1);
571 if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
572 return retval;
573 }
574
575 if (sd2_0)
576 src /= len;
577
578 mmc_send_cmd(&request, MMC_READ_SINGLE_BLOCK, src, 1,len, RESPONSE_R1, dst);
579 if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
580 return retval;
581 }
582 return retval;
583 }
584
585 int mmc_block_write(ulong dst, uchar *src, int len)
586 {
587 return 0;
588 }
589
590 int mmc_read(ulong src, uchar *dst, int size)
591 {
592 ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
593 ulong mmc_block_size, mmc_block_address;
594
595 if (size == 0) {
596 return 0;
597 }
598
599 if (!mmc_ready) {
600 printf("MMC card is not ready\n");
601 return -1;
602 }
603
604 mmc_block_size = MMC_BLOCK_SIZE;
605 mmc_block_address = ~(mmc_block_size - 1);
606
607 src -= CFG_MMC_BASE;
608 end = src + size;
609 part_start = ~mmc_block_address & src;
610 part_end = ~mmc_block_address & end;
611 aligned_start = mmc_block_address & src;
612 aligned_end = mmc_block_address & end;
613 /* all block aligned accesses */
614 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
615 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
616 if (part_start) {
617 part_len = mmc_block_size - part_start;
618 debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
619 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
620 if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
621 return -1;
622 }
623 memcpy(dst, mmc_buf+part_start, part_len);
624 dst += part_len;
625 src += part_len;
626 }
627 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
628 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
629 for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
630 debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
631 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
632
633 if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
634 return -1;
635 }
636 }
637 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
638 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
639
640 if (part_end && src < end) {
641 if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
642 return -1;
643 }
644 memcpy(dst, mmc_buf, part_end);
645 }
646 return 0;
647
648 }
649
650 int mmc_write(uchar *src, ulong dst, int size)
651 {
652 ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
653 ulong mmc_block_size, mmc_block_address;
654
655 if (size == 0) {
656 return 0;
657 }
658
659 if (!mmc_ready) {
660 printf("MMC card is not ready\n");
661 return -1;
662 }
663
664 mmc_block_size = MMC_BLOCK_SIZE;
665 mmc_block_address = ~(mmc_block_size - 1);
666
667 dst -= CFG_MMC_BASE;
668 end = dst + size;
669 part_start = ~mmc_block_address & dst;
670 part_end = ~mmc_block_address & end;
671 aligned_start = mmc_block_address & dst;
672 aligned_end = mmc_block_address & end;
673
674 /* all block aligned accesses */
675 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
676 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
677 if (part_start) {
678 part_len = mmc_block_size - part_start;
679 debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
680 (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
681 if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
682 return -1;
683 }
684 memcpy(mmc_buf+part_start, src, part_len);
685 if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
686 return -1;
687 }
688 dst += part_len;
689 src += part_len;
690 }
691 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
692 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
693 for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
694 debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
695 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
696 if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
697 return -1;
698 }
699 }
700 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
701 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
702 if (part_end && dst < end) {
703 debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
704 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
705 if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
706 return -1;
707 }
708 memcpy(mmc_buf, src, part_end);
709 if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
710 return -1;
711 }
712 }
713 return 0;
714 }
715
716 ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
717 {
718 ulong src;
719 int mmc_block_size = MMC_BLOCK_SIZE;
720
721 src = blknr * mmc_block_size + CFG_MMC_BASE;
722 mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
723 return blkcnt;
724 }
725
726 int mmc_select_card(void)
727 {
728 struct mmc_request request;
729 struct mmc_response_r1 r1;
730 int retval;
731
732 mmc_simple_cmd(&request, MMC_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B);
733 retval = mmc_unpack_r1(&request, &r1, 0);
734 if (retval) {
735 return retval;
736 }
737
738 if (mmcinfo.sd) {
739 mmc_simple_cmd(&request, MMC_APP_CMD, mmcinfo.rca, RESPONSE_R1);
740 retval = mmc_unpack_r1(&request,&r1,0);
741 if (retval) {
742 return retval;
743 }
744 #if defined(MMC_BUS_WIDTH_1BIT)
745 mmc_simple_cmd(&request, SET_BUS_WIDTH, 1, RESPONSE_R1);
746 #else
747 mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1);
748 #endif
749 retval = mmc_unpack_r1(&request,&r1,0);
750 if (retval) {
751 return retval;
752 }
753 }
754 return 0;
755 }
756
757 /*
758 * Configure card
759 */
760 static void mmc_configure_card(void)
761 {
762 u32 rate;
763
764 /* Get card info */
765 if (sd2_0)
766 mmcinfo.block_num = (mmcinfo.csd.c_size + 1) << 10;
767 else
768 mmcinfo.block_num = (mmcinfo.csd.c_size + 1) * (1 << (mmcinfo.csd.c_size_mult + 2));
769
770 mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len;
771
772 /* Fix the clock rate */
773 rate = mmc_tran_speed(mmcinfo.csd.tran_speed);
774 if (rate < MMC_CLOCK_SLOW)
775 rate = MMC_CLOCK_SLOW;
776 if ((mmcinfo.sd == 0) && (rate > MMC_CLOCK_FAST))
777 rate = MMC_CLOCK_FAST;
778 if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST))
779 rate = SD_CLOCK_FAST;
780
781 DEBUG(2,"mmc_configure_card: block_len=%d block_num=%d rate=%d\n", mmcinfo.block_len, mmcinfo.block_num, rate);
782
783 jz_mmc_set_clock(mmcinfo.sd, rate);
784 }
785
786 /*
787 * State machine routines to initialize card(s)
788 */
789
790 /*
791 CIM_SINGLE_CARD_ACQ (frequency at 400 kHz)
792 --- Must enter from GO_IDLE_STATE ---
793 1. SD_SEND_OP_COND (SD Card) [CMD55] + [CMD41]
794 2. SEND_OP_COND (Full Range) [CMD1] {optional}
795 3. SEND_OP_COND (Set Range ) [CMD1]
796 If busy, delay and repeat step 2
797 4. ALL_SEND_CID [CMD2]
798 If timeout, set an error (no cards found)
799 5. SET_RELATIVE_ADDR [CMD3]
800 6. SEND_CSD [CMD9]
801 7. SET_DSR [CMD4] Only call this if (csd.dsr_imp).
802 8. Set clock frequency (check available in csd.tran_speed)
803 */
804
805 #define MMC_INIT_DOING 0
806 #define MMC_INIT_PASSED 1
807 #define MMC_INIT_FAILED 2
808
809 static int mmc_init_card_state(struct mmc_request *request)
810 {
811 struct mmc_response_r1 r1;
812 struct mmc_response_r3 r3;
813 int retval;
814 int ocr = 0x40300000;
815 int limit_41 = 0;
816
817 DEBUG(2,"mmc_init_card_state\n");
818
819 switch (request->cmd) {
820 case MMC_GO_IDLE_STATE: /* No response to parse */
821 if (mmcinfo.sd)
822 mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1);
823 else
824 mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
825 break;
826
827 case 8:
828 retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
829 mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
830 break;
831
832 case MMC_APP_CMD:
833 retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
834 if (retval & (limit_41 < 100)) {
835 DEBUG(0, "mmc_init_card_state: unable to MMC_APP_CMD error=%d (%s)\n",
836 retval, mmc_result_to_string(retval));
837 limit_41++;
838 mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
839 } else if (limit_41 < 100) {
840 limit_41++;
841 mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
842 } else{
843 /* reset the card to idle*/
844 mmc_simple_cmd(request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
845 mmcinfo.sd = 0;
846 }
847 break;
848
849 case SD_SEND_OP_COND:
850 retval = mmc_unpack_r3(request, &r3);
851 if (retval) {
852 /* Try MMC card */
853 mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
854 break;
855 }
856
857 DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
858
859 if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){
860 udelay(10000);
861 mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
862 }
863 else {
864 /* Set the data bus width to 4 bits */
865 mmcinfo.sd = 1; /* SD Card ready */
866 mmcinfo.state = CARD_STATE_READY;
867 mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
868 }
869 break;
870
871 case MMC_SEND_OP_COND:
872 retval = mmc_unpack_r3(request, &r3);
873 if (retval) {
874 DEBUG(0,"mmc_init_card_state: failed SEND_OP_COND error=%d (%s)\n",
875 retval, mmc_result_to_string(retval));
876 return MMC_INIT_FAILED;
877 }
878
879 DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
880 if (!(r3.ocr & MMC_CARD_BUSY)) {
881 mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
882 }
883 else {
884 mmcinfo.sd = 0; /* MMC Card ready */
885 mmcinfo.state = CARD_STATE_READY;
886 mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
887 }
888 break;
889
890 case MMC_ALL_SEND_CID:
891 retval = mmc_unpack_cid( request, &mmcinfo.cid );
892 mmc_dev.if_type = IF_TYPE_MMC;
893 mmc_dev.part_type = PART_TYPE_DOS;
894 mmc_dev.dev = 0;
895 mmc_dev.lun = 0;
896 mmc_dev.type = 0;
897 /* FIXME fill in the correct size (is set to 32MByte) */
898 mmc_dev.blksz = 512;
899 mmc_dev.lba = 0x10000;
900 mmc_dev.removable = 0;
901
902 /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
903 if ( retval && (retval != MMC_ERROR_CRC)) {
904 DEBUG(0,"mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n",
905 retval, mmc_result_to_string(retval));
906 return MMC_INIT_FAILED;
907 }
908 mmcinfo.state = CARD_STATE_IDENT;
909 if(mmcinfo.sd)
910 mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, 0, RESPONSE_R6);
911 else
912 mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1);
913 break;
914
915 case MMC_SET_RELATIVE_ADDR:
916 if (mmcinfo.sd) {
917 retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca);
918 mmcinfo.rca = mmcinfo.rca << 16;
919 DEBUG(2, "mmc_init_card_state: Get RCA from SD: 0x%04x Status: %x\n", mmcinfo.rca, r1.status);
920 } else {
921 retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
922 mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16;
923 }
924 if (retval) {
925 DEBUG(0, "mmc_init_card_state: unable to SET_RELATIVE_ADDR error=%d (%s)\n",
926 retval, mmc_result_to_string(retval));
927 return MMC_INIT_FAILED;
928 }
929
930 mmcinfo.state = CARD_STATE_STBY;
931 mmc_simple_cmd(request, MMC_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD);
932
933 break;
934
935 case MMC_SEND_CSD:
936 retval = mmc_unpack_csd(request, &mmcinfo.csd);
937 mmc_csd_t *csd = (mmc_csd_t *)retval;
938 memcpy(&mmc_csd, csd, sizeof(csd));
939 mmc_ready = 1;
940
941 printf("MMC card is ready\n");
942 /* FIXME add verbose printout for csd */
943
944 /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
945 if (retval && (retval != MMC_ERROR_CRC)) {
946 DEBUG(0, "mmc_init_card_state: unable to SEND_CSD error=%d (%s)\n",
947 retval, mmc_result_to_string(retval));
948 return MMC_INIT_FAILED;
949 }
950 if (mmcinfo.csd.dsr_imp) {
951 DEBUG(0, "mmc_init_card_state: driver doesn't support setting DSR\n");
952 }
953 mmc_configure_card();
954 return MMC_INIT_PASSED;
955
956 default:
957 DEBUG(0, "mmc_init_card_state: error! Illegal last cmd %d\n", request->cmd);
958 return MMC_INIT_FAILED;
959 }
960
961 return MMC_INIT_DOING;
962 }
963
964 int mmc_init_card(void)
965 {
966 struct mmc_request request;
967 int retval;
968
969 mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */
970 mmc_simple_cmd(&request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
971 mmcinfo.sd = 1; /* assuming a SD card */
972
973 while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING)
974 ;
975
976 if (retval == MMC_INIT_PASSED)
977 return MMC_NO_ERROR;
978 else
979 return MMC_NO_RESPONSE;
980 }
981
982 int mmc_legacy_init(int verbose)
983 {
984 if (!__msc_card_detected())
985 return 1;
986
987 printf("MMC card found\n");
988
989 /* Step-1: init GPIO */
990 __gpio_as_msc();
991
992 __msc_init_io();
993
994 /* Step-2: turn on power of card */
995 #if !defined(CONFIG_SAKC)
996 __msc_enable_power();
997 #endif
998
999 /* Step-3: Reset MSC Controller. */
1000 __msc_reset();
1001
1002 /* Step-3: mask all IRQs. */
1003 MMC_IRQ_MASK();
1004
1005 /* Step-4: stop MMC/SD clock */
1006 jz_mmc_stop_clock();
1007 mmc_init_card();
1008 mmc_select_card();
1009
1010 mmc_dev.block_read = mmc_bread;
1011 fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
1012
1013 return 0;
1014 }
1015
1016 int mmc_ident(block_dev_desc_t *dev)
1017 {
1018 return 0;
1019 }
1020
1021 int mmc2info(ulong addr)
1022 {
1023 /* FIXME hard codes to 32 MB device */
1024 if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
1025 return 1;
1026 }
1027 return 0;
1028 }
1029 /*
1030 * Debugging functions
1031 */
1032
1033 static char * mmc_result_strings[] = {
1034 "NO_RESPONSE",
1035 "NO_ERROR",
1036 "ERROR_OUT_OF_RANGE",
1037 "ERROR_ADDRESS",
1038 "ERROR_BLOCK_LEN",
1039 "ERROR_ERASE_SEQ",
1040 "ERROR_ERASE_PARAM",
1041 "ERROR_WP_VIOLATION",
1042 "ERROR_CARD_IS_LOCKED",
1043 "ERROR_LOCK_UNLOCK_FAILED",
1044 "ERROR_COM_CRC",
1045 "ERROR_ILLEGAL_COMMAND",
1046 "ERROR_CARD_ECC_FAILED",
1047 "ERROR_CC",
1048 "ERROR_GENERAL",
1049 "ERROR_UNDERRUN",
1050 "ERROR_OVERRUN",
1051 "ERROR_CID_CSD_OVERWRITE",
1052 "ERROR_STATE_MISMATCH",
1053 "ERROR_HEADER_MISMATCH",
1054 "ERROR_TIMEOUT",
1055 "ERROR_CRC",
1056 "ERROR_DRIVER_FAILURE",
1057 };
1058
1059 char * mmc_result_to_string(int i)
1060 {
1061 return mmc_result_strings[i+1];
1062 }
1063
1064 static char * card_state_strings[] = {
1065 "empty",
1066 "idle",
1067 "ready",
1068 "ident",
1069 "stby",
1070 "tran",
1071 "data",
1072 "rcv",
1073 "prg",
1074 "dis",
1075 };
1076
1077 static inline char * card_state_to_string(int i)
1078 {
1079 return card_state_strings[i+1];
1080 }
1081
1082 /*
1083 * Utility functions
1084 */
1085
1086 #define PARSE_U32(_buf,_index) \
1087 (((u32)_buf[_index]) << 24) | (((u32)_buf[_index+1]) << 16) | \
1088 (((u32)_buf[_index+2]) << 8) | ((u32)_buf[_index+3]);
1089
1090 #define PARSE_U16(_buf,_index) \
1091 (((u16)_buf[_index]) << 8) | ((u16)_buf[_index+1]);
1092
1093 int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
1094 {
1095 u8 *buf = request->response;
1096 int num = 0;
1097
1098 if (request->result)
1099 return request->result;
1100
1101 csd->csd_structure = (buf[1] & 0xc0) >> 6;
1102 if (csd->csd_structure)
1103 sd2_0 = 1;
1104 else
1105 sd2_0 = 0;
1106
1107 switch (csd->csd_structure) {
1108 case 0 :
1109 csd->taac = buf[2];
1110 csd->nsac = buf[3];
1111 csd->tran_speed = buf[4];
1112 csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
1113 csd->read_bl_len = buf[6] & 0x0f;
1114 /* for support 2GB card*/
1115 if (csd->read_bl_len >= 10)
1116 {
1117 num = csd->read_bl_len - 9;
1118 csd->read_bl_len = 9;
1119 }
1120
1121 csd->read_bl_partial = (buf[7] & 0x80) ? 1 : 0;
1122 csd->write_blk_misalign = (buf[7] & 0x40) ? 1 : 0;
1123 csd->read_blk_misalign = (buf[7] & 0x20) ? 1 : 0;
1124 csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0;
1125 csd->c_size = ((((u16)buf[7]) & 0x03) << 10) | (((u16)buf[8]) << 2) | (((u16)buf[9]) & 0xc0) >> 6;
1126
1127 if (num)
1128 csd->c_size = csd->c_size << num;
1129
1130
1131 csd->vdd_r_curr_min = (buf[9] & 0x38) >> 3;
1132 csd->vdd_r_curr_max = buf[9] & 0x07;
1133 csd->vdd_w_curr_min = (buf[10] & 0xe0) >> 5;
1134 csd->vdd_w_curr_max = (buf[10] & 0x1c) >> 2;
1135 csd->c_size_mult = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7);
1136 switch (csd->csd_structure) {
1137 case CSD_STRUCT_VER_1_0:
1138 case CSD_STRUCT_VER_1_1:
1139 csd->erase.v22.sector_size = (buf[11] & 0x7c) >> 2;
1140 csd->erase.v22.erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
1141
1142 break;
1143 case CSD_STRUCT_VER_1_2:
1144 default:
1145 csd->erase.v31.erase_grp_size = (buf[11] & 0x7c) >> 2;
1146 csd->erase.v31.erase_grp_mult = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
1147 break;
1148 }
1149 csd->wp_grp_size = buf[12] & 0x1f;
1150 csd->wp_grp_enable = (buf[13] & 0x80) ? 1 : 0;
1151 csd->default_ecc = (buf[13] & 0x60) >> 5;
1152 csd->r2w_factor = (buf[13] & 0x1c) >> 2;
1153 csd->write_bl_len = ((buf[13] & 0x03) << 2) | ((buf[14] & 0xc0) >> 6);
1154 if (csd->write_bl_len >= 10)
1155 csd->write_bl_len = 9;
1156
1157 csd->write_bl_partial = (buf[14] & 0x20) ? 1 : 0;
1158 csd->file_format_grp = (buf[15] & 0x80) ? 1 : 0;
1159 csd->copy = (buf[15] & 0x40) ? 1 : 0;
1160 csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
1161 csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
1162 csd->file_format = (buf[15] & 0x0c) >> 2;
1163 csd->ecc = buf[15] & 0x03;
1164
1165 DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
1166 " ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
1167 " read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
1168 " vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
1169 " wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
1170 " write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
1171 " perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
1172 csd->csd_structure, csd->spec_vers,
1173 csd->taac, csd->nsac, csd->tran_speed,
1174 csd->ccc, csd->read_bl_len,
1175 csd->read_bl_partial, csd->write_blk_misalign,
1176 csd->read_blk_misalign, csd->dsr_imp,
1177 csd->c_size, csd->vdd_r_curr_min,
1178 csd->vdd_r_curr_max, csd->vdd_w_curr_min,
1179 csd->vdd_w_curr_max, csd->c_size_mult,
1180 csd->wp_grp_size, csd->wp_grp_enable,
1181 csd->default_ecc, csd->r2w_factor,
1182 csd->write_bl_len, csd->write_bl_partial,
1183 csd->file_format_grp, csd->copy,
1184 csd->perm_write_protect, csd->tmp_write_protect,
1185 csd->file_format, csd->ecc);
1186 switch (csd->csd_structure) {
1187 case CSD_STRUCT_VER_1_0:
1188 case CSD_STRUCT_VER_1_1:
1189 DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n",
1190 csd->erase.v22.sector_size,
1191 csd->erase.v22.erase_grp_size);
1192 break;
1193 case CSD_STRUCT_VER_1_2:
1194 default:
1195 DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n",
1196 csd->erase.v31.erase_grp_size,
1197 csd->erase.v31.erase_grp_mult);
1198 break;
1199
1200 }
1201 break;
1202
1203 case 1 :
1204 csd->taac = 0;
1205 csd->nsac = 0;
1206 csd->tran_speed = buf[4];
1207 csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
1208
1209 csd->read_bl_len = 9;
1210 csd->read_bl_partial = 0;
1211 csd->write_blk_misalign = 0;
1212 csd->read_blk_misalign = 0;
1213 csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0;
1214 csd->c_size = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ;
1215 switch (csd->csd_structure) {
1216 case CSD_STRUCT_VER_1_0:
1217 case CSD_STRUCT_VER_1_1:
1218 csd->erase.v22.sector_size = 0x7f;
1219 csd->erase.v22.erase_grp_size = 0;
1220 break;
1221 case CSD_STRUCT_VER_1_2:
1222 default:
1223 csd->erase.v31.erase_grp_size = 0x7f;
1224 csd->erase.v31.erase_grp_mult = 0;
1225 break;
1226 }
1227 csd->wp_grp_size = 0;
1228 csd->wp_grp_enable = 0;
1229 csd->default_ecc = (buf[13] & 0x60) >> 5;
1230 csd->r2w_factor = 4;/* Unused */
1231 csd->write_bl_len = 9;
1232
1233 csd->write_bl_partial = 0;
1234 csd->file_format_grp = 0;
1235 csd->copy = (buf[15] & 0x40) ? 1 : 0;
1236 csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
1237 csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
1238 csd->file_format = 0;
1239 csd->ecc = buf[15] & 0x03;
1240
1241 DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
1242 " ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
1243 " read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
1244 " vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
1245 " wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
1246 " write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
1247 " perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
1248 csd->csd_structure, csd->spec_vers,
1249 csd->taac, csd->nsac, csd->tran_speed,
1250 csd->ccc, csd->read_bl_len,
1251 csd->read_bl_partial, csd->write_blk_misalign,
1252 csd->read_blk_misalign, csd->dsr_imp,
1253 csd->c_size, csd->vdd_r_curr_min,
1254 csd->vdd_r_curr_max, csd->vdd_w_curr_min,
1255 csd->vdd_w_curr_max, csd->c_size_mult,
1256 csd->wp_grp_size, csd->wp_grp_enable,
1257 csd->default_ecc, csd->r2w_factor,
1258 csd->write_bl_len, csd->write_bl_partial,
1259 csd->file_format_grp, csd->copy,
1260 csd->perm_write_protect, csd->tmp_write_protect,
1261 csd->file_format, csd->ecc);
1262 switch (csd->csd_structure) {
1263 case CSD_STRUCT_VER_1_0:
1264 case CSD_STRUCT_VER_1_1:
1265 DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n",
1266 csd->erase.v22.sector_size,
1267 csd->erase.v22.erase_grp_size);
1268 break;
1269 case CSD_STRUCT_VER_1_2:
1270 default:
1271 DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n",
1272 csd->erase.v31.erase_grp_size,
1273 csd->erase.v31.erase_grp_mult);
1274 break;
1275 }
1276 }
1277
1278 if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
1279
1280 return 0;
1281 }
1282
1283 int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state)
1284 {
1285 u8 *buf = request->response;
1286
1287 if (request->result) return request->result;
1288
1289 r1->cmd = buf[0];
1290 r1->status = PARSE_U32(buf,1);
1291
1292 DEBUG(2, "mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status);
1293
1294 if (R1_STATUS(r1->status)) {
1295 if (r1->status & R1_OUT_OF_RANGE) return MMC_ERROR_OUT_OF_RANGE;
1296 if (r1->status & R1_ADDRESS_ERROR) return MMC_ERROR_ADDRESS;
1297 if (r1->status & R1_BLOCK_LEN_ERROR) return MMC_ERROR_BLOCK_LEN;
1298 if (r1->status & R1_ERASE_SEQ_ERROR) return MMC_ERROR_ERASE_SEQ;
1299 if (r1->status & R1_ERASE_PARAM) return MMC_ERROR_ERASE_PARAM;
1300 if (r1->status & R1_WP_VIOLATION) return MMC_ERROR_WP_VIOLATION;
1301 /*if (r1->status & R1_CARD_IS_LOCKED) return MMC_ERROR_CARD_IS_LOCKED; */
1302 if (r1->status & R1_LOCK_UNLOCK_FAILED) return MMC_ERROR_LOCK_UNLOCK_FAILED;
1303 if (r1->status & R1_COM_CRC_ERROR) return MMC_ERROR_COM_CRC;
1304 if (r1->status & R1_ILLEGAL_COMMAND) return MMC_ERROR_ILLEGAL_COMMAND;
1305 if (r1->status & R1_CARD_ECC_FAILED) return MMC_ERROR_CARD_ECC_FAILED;
1306 if (r1->status & R1_CC_ERROR) return MMC_ERROR_CC;
1307 if (r1->status & R1_ERROR) return MMC_ERROR_GENERAL;
1308 if (r1->status & R1_UNDERRUN) return MMC_ERROR_UNDERRUN;
1309 if (r1->status & R1_OVERRUN) return MMC_ERROR_OVERRUN;
1310 if (r1->status & R1_CID_CSD_OVERWRITE) return MMC_ERROR_CID_CSD_OVERWRITE;
1311 }
1312
1313 if (buf[0] != request->cmd) return MMC_ERROR_HEADER_MISMATCH;
1314
1315 /* This should be last - it's the least dangerous error */
1316
1317 return 0;
1318 }
1319
1320 int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr)
1321 {
1322 u8 *buf = request->response;
1323 if (request->result) return request->result;
1324
1325 *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */
1326 return mmc_unpack_r1(request, r1, state);
1327
1328 }
1329
1330 int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca)
1331 {
1332 u8 *buf = request->response;
1333
1334 if (request->result) return request->result;
1335
1336 *rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */
1337
1338 *(buf+1) = 0;
1339 *(buf+2) = 0;
1340
1341 return mmc_unpack_r1(request, r1, state);
1342 }
1343
1344 int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid)
1345 {
1346 u8 *buf = request->response;
1347 int i;
1348
1349 if (request->result) return request->result;
1350
1351 cid->mid = buf[1];
1352 cid->oid = PARSE_U16(buf,2);
1353 for (i = 0 ; i < 6 ; i++)
1354 cid->pnm[i] = buf[4+i];
1355 cid->pnm[6] = 0;
1356 cid->prv = buf[10];
1357 cid->psn = PARSE_U32(buf,11);
1358 cid->mdt = buf[15];
1359
1360 DEBUG(2,"mmc_unpack_cid: mid=%d oid=%d pnm=%s prv=%d.%d psn=%08x mdt=%d/%d\n",
1361 cid->mid, cid->oid, cid->pnm,
1362 (cid->prv>>4), (cid->prv&0xf),
1363 cid->psn, (cid->mdt>>4), (cid->mdt&0xf)+1997);
1364
1365 if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
1366 return 0;
1367 }
1368
1369 int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3)
1370 {
1371 u8 *buf = request->response;
1372
1373 if (request->result) return request->result;
1374
1375 r3->ocr = PARSE_U32(buf,1);
1376 DEBUG(2,"mmc_unpack_r3: ocr=%08x\n", r3->ocr);
1377
1378 if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
1379 return 0;
1380 }
1381
1382 #define KBPS 1
1383 #define MBPS 1000
1384
1385 static u32 ts_exp[] = { 100*KBPS, 1*MBPS, 10*MBPS, 100*MBPS, 0, 0, 0, 0 };
1386 static u32 ts_mul[] = { 0, 1000, 1200, 1300, 1500, 2000, 2500, 3000,
1387 3500, 4000, 4500, 5000, 5500, 6000, 7000, 8000 };
1388
1389 u32 mmc_tran_speed(u8 ts)
1390 {
1391 u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3];
1392
1393 if (rate <= 0) {
1394 DEBUG(0, "mmc_tran_speed: error - unrecognized speed 0x%02x\n", ts);
1395 return 1;
1396 }
1397
1398 return rate;
1399 }
1400
1401 void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg,
1402 u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer)
1403 {
1404 request->cmd = cmd;
1405 request->arg = arg;
1406 request->rtype = rtype;
1407 request->nob = nob;
1408 request->block_len = block_len;
1409 request->buffer = buffer;
1410 request->cnt = nob * block_len;
1411
1412 jz_mmc_exec_cmd(request);
1413 }
1414
1415 #endif /* CONFIG_MMC */
1416 #endif /* CONFIG_JZ4740 */
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