target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom ChipCommon core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12 #include <linux/ssb/ssb_regs.h>
  13 #include <linux/pci.h>
  14
  15 #include "../ssb_private.h"
  16
  17
  18 /* Clock sources */
  19 enum {
  20         /* PCI clock */
  21         SSB_CHIPCO_CLKSRC_PCI,
  22         /* Crystal slow clock oscillator */
  23         SSB_CHIPCO_CLKSRC_XTALOS,
  24         /* Low power oscillator */
  25         SSB_CHIPCO_CLKSRC_LOPWROS,
  26 };
  27
  28
  29 static inline u32 chipco_read32(struct ssb_chipcommon *cc,
  30                                 u16 offset)
  31 {
  32         return ssb_read32(cc->dev, offset);
  33 }
  34
  35 static inline void chipco_write32(struct ssb_chipcommon *cc,
  36                                   u16 offset,
  37                                   u32 value)
  38 {
  39         ssb_write32(cc->dev, offset, value);
  40 }
  41
  42
  43 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
  44                               enum ssb_clkmode mode)
  45 {
  46         struct ssb_device *ccdev = cc->dev;
  47         struct ssb_bus *bus;
  48         u32 tmp;
  49
  50         if (!ccdev)
  51                 return;
  52         bus = ccdev->bus;
  53         /* chipcommon cores prior to rev6 don't support dynamic clock control */
  54         if (ccdev->id.revision < 6)
  55                 return;
  56         /* chipcommon cores rev10 are a whole new ball game */
  57         if (ccdev->id.revision >= 10)
  58                 return;
  59         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
  60                 return;
  61
  62         switch (mode) {
  63         case SSB_CLKMODE_SLOW:
  64                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  65                 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  66                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  67                 break;
  68         case SSB_CLKMODE_FAST:
  69                 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
  70                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  71                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  72                 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
  73                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  74                 break;
  75         case SSB_CLKMODE_DYNAMIC:
  76                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  77                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  78                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
  79                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  80                 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
  81                         tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  82                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  83
  84                 /* for dynamic control, we have to release our xtal_pu "force on" */
  85                 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
  86                         ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
  87                 break;
  88         default:
  89                 assert(0);
  90         }
  91 }
  92 EXPORT_SYMBOL(ssb_chipco_set_clockmode);
  93
  94 /* Get the Slow Clock Source */
  95 static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
  96 {
  97         struct ssb_bus *bus = cc->dev->bus;
  98         u32 tmp = 0;
  99
 100         if (cc->dev->id.revision < 6) {
 101                 if (bus->bustype == SSB_BUSTYPE_SSB /*TODO ||
 102                     bus->bustype == SSB_BUSTYPE_PCMCIA*/)
 103                         return SSB_CHIPCO_CLKSRC_XTALOS;
 104                 if (bus->bustype == SSB_BUSTYPE_PCI) {
 105                         pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
 106                         if (tmp & 0x10)
 107                                 return SSB_CHIPCO_CLKSRC_PCI;
 108                         return SSB_CHIPCO_CLKSRC_XTALOS;
 109                 }
 110         }
 111         if (cc->dev->id.revision < 10) {
 112                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 113                 tmp &= 0x7;
 114                 if (tmp == 0)
 115                         return SSB_CHIPCO_CLKSRC_LOPWROS;
 116                 if (tmp == 1)
 117                         return SSB_CHIPCO_CLKSRC_XTALOS;
 118                 if (tmp == 2)
 119                         return SSB_CHIPCO_CLKSRC_PCI;
 120         }
 121
 122         return SSB_CHIPCO_CLKSRC_XTALOS;
 123 }
 124
 125 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
 126 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
 127 {
 128         int limit;
 129         int clocksrc;
 130         int divisor;
 131         u32 tmp;
 132
 133         clocksrc = chipco_pctl_get_slowclksrc(cc);
 134         if (cc->dev->id.revision < 6) {
 135                 switch (clocksrc) {
 136                 case SSB_CHIPCO_CLKSRC_PCI:
 137                         divisor = 64;
 138                         break;
 139                 case SSB_CHIPCO_CLKSRC_XTALOS:
 140                         divisor = 32;
 141                         break;
 142                 default:
 143                         assert(0);
 144                         divisor = 1;
 145                 }
 146         } else if (cc->dev->id.revision < 10) {
 147                 switch (clocksrc) {
 148                 case SSB_CHIPCO_CLKSRC_LOPWROS:
 149                         divisor = 1;
 150                         break;
 151                 case SSB_CHIPCO_CLKSRC_XTALOS:
 152                 case SSB_CHIPCO_CLKSRC_PCI:
 153                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 154                         divisor = (tmp >> 16) + 1;
 155                         divisor *= 4;
 156                         break;
 157                 default:
 158                         assert(0);
 159                         divisor = 1;
 160                 }
 161         } else {
 162                 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
 163                 divisor = (tmp >> 16) + 1;
 164                 divisor *= 4;
 165         }
 166
 167         switch (clocksrc) {
 168         case SSB_CHIPCO_CLKSRC_LOPWROS:
 169                 if (get_max)
 170                         limit = 43000;
 171                 else
 172                         limit = 25000;
 173                 break;
 174         case SSB_CHIPCO_CLKSRC_XTALOS:
 175                 if (get_max)
 176                         limit = 20200000;
 177                 else
 178                         limit = 19800000;
 179                 break;
 180         case SSB_CHIPCO_CLKSRC_PCI:
 181                 if (get_max)
 182                         limit = 34000000;
 183                 else
 184                         limit = 25000000;
 185                 break;
 186         default:
 187                 assert(0);
 188                 limit = 0;
 189         }
 190         limit /= divisor;
 191
 192         return limit;
 193 }
 194
 195 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
 196 {
 197         struct ssb_bus *bus = cc->dev->bus;
 198
 199         if (bus->chip_id == 0x4321) {
 200                 if (bus->chip_rev == 0)
 201                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
 202                 else if (bus->chip_rev == 1)
 203                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
 204         }
 205
 206         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 207                 return;
 208
 209         if (cc->dev->id.revision >= 10) {
 210                 /* Set Idle Power clock rate to 1Mhz */
 211                 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
 212                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
 213                                 0x0000FFFF) | 0x00040000);
 214         } else {
 215                 int maxfreq;
 216
 217                 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
 218                 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
 219                                (maxfreq * 150 + 999999) / 1000000);
 220                 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
 221                                (maxfreq * 15 + 999999) / 1000000);
 222         }
 223 }
 224
 225 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
 226 {
 227         struct ssb_bus *bus = cc->dev->bus;
 228         int minfreq;
 229         unsigned int tmp;
 230         u32 pll_on_delay;
 231
 232         if (bus->bustype != SSB_BUSTYPE_PCI)
 233                 return;
 234         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 235                 return;
 236
 237         minfreq = chipco_pctl_clockfreqlimit(cc, 0);
 238         pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
 239         tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
 240         assert((tmp & ~0xFFFF) == 0);
 241
 242         cc->fast_pwrup_delay = tmp;
 243 }
 244
 245 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 246 {
 247         if (!cc->dev)
 248                 return; /* We don't have a ChipCommon */
 249         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 250         chipco_powercontrol_init(cc);
 251         calc_fast_powerup_delay(cc);
 252 }
 253
 254 void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
 255 {
 256         if (!cc->dev)
 257                 return;
 258         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
 259 }
 260
 261 void ssb_chipco_resume(struct ssb_chipcommon *cc)
 262 {
 263         if (!cc->dev)
 264                 return;
 265         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 266         chipco_powercontrol_init(cc);
 267 }
 268
 269 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id, u32 *rate,
 270                              u32 *plltype, u32 *n, u32 *m)
 271 {
 272         *rate = 0;
 273         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 274         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 275         switch (*plltype) {
 276                 case SSB_PLLTYPE_2:
 277                 case SSB_PLLTYPE_4:
 278                 case SSB_PLLTYPE_6:
 279                 case SSB_PLLTYPE_7:
 280                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 281                         break;
 282                 case SSB_PLLTYPE_5:
 283                         *rate = 200000000;
 284                         break;
 285                 case SSB_PLLTYPE_3:
 286                         /* 5350 uses m2 to control mips */
 287                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 288                         break;
 289                 default:
 290                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 291                         break;
 292         }
 293
 294         if (*rate == 0 && chip_id == 0x5365)
 295                 *rate = 200000000;
 296 }
 297
 298 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
 299                                  u32 *plltype, u32 *n, u32 *m)
 300 {
 301         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 302         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 303         switch (*plltype) {
 304         case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
 305                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 306                 break;
 307         case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
 308                 if (cc->dev->bus->chip_id != 0x5365) {
 309                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 310                         break;
 311                 }
 312                 /* Fallthough */
 313         default:
 314                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 315         }
 316 }
 317
 318 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
 319                             unsigned long ns)
 320 {
 321         struct ssb_device *dev = cc->dev;
 322         struct ssb_bus *bus = dev->bus;
 323         u32 tmp;
 324
 325         /* set register for external IO to control LED. */
 326         chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
 327         tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;         /* Waitcount-3 = 10ns */
 328         tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;        /* Waitcount-1 = 40ns */
 329         tmp |= ceildiv(240, ns);                                /* Waitcount-0 = 240ns */
 330         chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
 331
 332         /* Set timing for the flash */
 333         tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT;        /* Waitcount-3 = 10nS */
 334         tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT;       /* Waitcount-1 = 10nS */
 335         tmp |= ceildiv(120, ns);                                /* Waitcount-0 = 120nS */
 336         if ((bus->chip_id == 0x5365) ||
 337             (dev->id.revision < 9))
 338                 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
 339         if ((bus->chip_id == 0x5365) ||
 340             (dev->id.revision < 9) ||
 341             ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
 342                 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
 343
 344         if (bus->chip_id == 0x5350) {
 345                 /* Enable EXTIF */
 346                 tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;   /* Waitcount-3 = 10ns */
 347                 tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
 348                 tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
 349                 tmp |= ceildiv(120, ns);                          /* Waitcount-0 = 120ns */
 350                 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
 351         }
 352 }
 353
 354 #ifdef CONFIG_SSB_SERIAL
 355 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
 356                            struct ssb_serial_port *ports)
 357 {
 358         struct ssb_bus *bus = cc->dev->bus;
 359         int nr_ports = 0;
 360         u32 plltype;
 361         unsigned int irq;
 362         u32 baud_base, div;
 363         u32 i, n;
 364
 365         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 366         irq = ssb_mips_irq(cc->dev);
 367
 368         if (plltype == SSB_PLLTYPE_1) {
 369                 /* PLL clock */
 370                 baud_base = ssb_calc_clock_rate(plltype,
 371                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
 372                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
 373                 div = 1;
 374         } else {
 375                 if (cc->dev->id.revision >= 11) {
 376                         /* Fixed ALP clock */
 377                         baud_base = 20000000;
 378                         div = 1;
 379                         /* Set the override bit so we don't divide it */
 380                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 381                                        SSB_CHIPCO_CORECTL_UARTCLK0);
 382                 } else if (cc->dev->id.revision >= 3) {
 383                         /* Internal backplane clock */
 384                         baud_base = ssb_clockspeed(bus);
 385                         div = 2; /* Minimum divisor */
 386                         chipco_write32(cc, SSB_CHIPCO_CLKDIV,
 387                                        (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
 388                                         & ~SSB_CHIPCO_CLKDIV_UART) | div);
 389                 } else {
 390                         /* Fixed internal backplane clock */
 391                         baud_base = 88000000;
 392                         div = 48;
 393                 }
 394
 395                 /* Clock source depends on strapping if UartClkOverride is unset */
 396                 if ((cc->dev->id.revision > 0) &&
 397                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
 398                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
 399                             SSB_CHIPCO_CAP_UARTCLK_INT) {
 400                                 /* Internal divided backplane clock */
 401                                 baud_base /= div;
 402                         } else {
 403                                 /* Assume external clock of 1.8432 MHz */
 404                                 baud_base = 1843200;
 405                         }
 406                 }
 407         }
 408
 409         /* Determine the registers of the UARTs */
 410         n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
 411         for (i = 0; i < n; i++) {
 412                 void __iomem *cc_mmio;
 413                 void __iomem *uart_regs;
 414
 415                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
 416                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
 417                 /* Offset changed at after rev 0 */
 418                 if (cc->dev->id.revision == 0)
 419                         uart_regs += (i * 8);
 420                 else
 421                         uart_regs += (i * 256);
 422
 423                 nr_ports++;
 424                 ports[i].regs = uart_regs;
 425                 ports[i].irq = irq;
 426                 ports[i].baud_base = baud_base;
 427                 ports[i].reg_shift = 0;
 428         }
 429
 430         return nr_ports;
 431 }
 432 #endif /* CONFIG_SSB_SERIAL */
 433
 434 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 435 int
 436 ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks)
 437 {
 438         /* instant NMI */
 439         chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 440         return 0;
 441 }
 442 EXPORT_SYMBOL(ssb_chipco_watchdog);