1 --- a/arch/mips/kernel/cevt-r4k.c
2 +++ b/arch/mips/kernel/cevt-r4k.c
4 #include <asm/cevt-r4k.h>
7 + * Compare interrupt can be routed and latched outside the core,
8 + * so a single execution hazard barrier may not be enough to give
9 + * it time to clear as seen in the Cause register. 4 time the
10 + * pipeline depth seems reasonably conservative, and empirically
11 + * works better in configurations with high CPU/bus clock ratios.
14 +#define compare_change_hazard() \
16 + irq_disable_hazard(); \
17 + irq_disable_hazard(); \
18 + irq_disable_hazard(); \
19 + irq_disable_hazard(); \
23 * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
24 * of these routines with SMTC-specific variants.
26 @@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
27 cnt = read_c0_count();
29 write_c0_compare(cnt);
30 + compare_change_hazard();
31 res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
34 @@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
35 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
39 - * Compare interrupt can be routed and latched outside the core,
40 - * so a single execution hazard barrier may not be enough to give
41 - * it time to clear as seen in the Cause register. 4 time the
42 - * pipeline depth seems reasonably conservative, and empirically
43 - * works better in configurations with high CPU/bus clock ratios.
46 -#define compare_change_hazard() \
48 - irq_disable_hazard(); \
49 - irq_disable_hazard(); \
50 - irq_disable_hazard(); \
51 - irq_disable_hazard(); \
54 int c0_compare_int_usable(void)