package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S

   1 /*
   2  *  Memory sub-system initialization code for Danube board.
   3  *  Andre Messerschmidt
   4  *  Copyright (c) 2005  Infineon Technologies AG
   5  *
   6  *  Based on Inca-IP code
   7  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /* History:
  28       peng liu May 25, 2006, for PLL setting after reset, 05252006
  29  */
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/regdef.h>
  33
  34 #if defined(CONFIG_USE_DDR_RAM)
  35
  36 #if defined(CONFIG_USE_DDR_RAM_CFG_111M)
  37 #include "ddr_settings_r111.h"
  38 #define DDR111
  39 #elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
  40 #include "ddr_settings_r166.h"
  41 #define DDR166
  42 #elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
  43 #include "ddr_settings_e111.h"
  44 #define DDR111
  45 #elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
  46 #include "ddr_settings_e166.h"
  47 #define DDR166
  48 #elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
  49 #include "ddr_settings_PROMOSDDR400.h"
  50 #define DDR166
  51 #elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
  52 #include "ddr_settings_Samsung_166.h"
  53 #define DDR166
  54 #elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
  55 #include "ddr_settings_psc_166.h"
  56 #define DDR166
  57 #else
  58 #warning "missing definition for ddr_settings.h, use default!"
  59 #include "ddr_settings.h"
  60 #endif
  61 #endif /* CONFIG_USE_DDR_RAM */
  62
  63 #if defined(CONFIG_USE_DDR_RAM) &&  !defined(MC_DC0_VALUE)
  64 #error "missing include of ddr_settings.h"
  65 #endif
  66
  67 #define EBU_MODUL_BASE          0xBE105300
  68 #define EBU_CLC(value)          0x0000(value)
  69 #define EBU_CON(value)          0x0010(value)
  70 #define EBU_ADDSEL0(value)      0x0020(value)
  71 #define EBU_ADDSEL1(value)      0x0024(value)
  72 #define EBU_ADDSEL2(value)      0x0028(value)
  73 #define EBU_ADDSEL3(value)      0x002C(value)
  74 #define EBU_BUSCON0(value)      0x0060(value)
  75 #define EBU_BUSCON1(value)      0x0064(value)
  76 #define EBU_BUSCON2(value)      0x0068(value)
  77 #define EBU_BUSCON3(value)      0x006C(value)
  78
  79 #define MC_MODUL_BASE           0xBF800000
  80 #define MC_ERRCAUSE(value)      0x0010(value)
  81 #define MC_ERRADDR(value)       0x0020(value)
  82 #define MC_CON(value)           0x0060(value)
  83
  84 #define MC_SRAM_ENABLE          0x00000004
  85 #define MC_SDRAM_ENABLE         0x00000002
  86 #define MC_DDRRAM_ENABLE        0x00000001
  87
  88 #define MC_SDR_MODUL_BASE       0xBF800200
  89 #define MC_IOGP(value)          0x0000(value)
  90 #define MC_CTRLENA(value)       0x0010(value)
  91 #define MC_MRSCODE(value)       0x0020(value)
  92 #define MC_CFGDW(value)         0x0030(value)
  93 #define MC_CFGPB0(value)        0x0040(value)
  94 #define MC_LATENCY(value)       0x0080(value)
  95 #define MC_TREFRESH(value)      0x0090(value)
  96 #define MC_SELFRFSH(value)      0x00A0(value)
  97
  98 #define MC_DDR_MODUL_BASE       0xBF801000
  99 #define MC_DC00(value)          0x0000(value)
 100 #define MC_DC01(value)          0x0010(value)
 101 #define MC_DC02(value)          0x0020(value)
 102 #define MC_DC03(value)          0x0030(value)
 103 #define MC_DC04(value)          0x0040(value)
 104 #define MC_DC05(value)          0x0050(value)
 105 #define MC_DC06(value)          0x0060(value)
 106 #define MC_DC07(value)          0x0070(value)
 107 #define MC_DC08(value)          0x0080(value)
 108 #define MC_DC09(value)          0x0090(value)
 109 #define MC_DC10(value)          0x00A0(value)
 110 #define MC_DC11(value)          0x00B0(value)
 111 #define MC_DC12(value)          0x00C0(value)
 112 #define MC_DC13(value)          0x00D0(value)
 113 #define MC_DC14(value)          0x00E0(value)
 114 #define MC_DC15(value)          0x00F0(value)
 115 #define MC_DC16(value)          0x0100(value)
 116 #define MC_DC17(value)          0x0110(value)
 117 #define MC_DC18(value)          0x0120(value)
 118 #define MC_DC19(value)          0x0130(value)
 119 #define MC_DC20(value)          0x0140(value)
 120 #define MC_DC21(value)          0x0150(value)
 121 #define MC_DC22(value)          0x0160(value)
 122 #define MC_DC23(value)          0x0170(value)
 123 #define MC_DC24(value)          0x0180(value)
 124 #define MC_DC25(value)          0x0190(value)
 125 #define MC_DC26(value)          0x01A0(value)
 126 #define MC_DC27(value)          0x01B0(value)
 127 #define MC_DC28(value)          0x01C0(value)
 128 #define MC_DC29(value)          0x01D0(value)
 129 #define MC_DC30(value)          0x01E0(value)
 130 #define MC_DC31(value)          0x01F0(value)
 131 #define MC_DC32(value)          0x0200(value)
 132 #define MC_DC33(value)          0x0210(value)
 133 #define MC_DC34(value)          0x0220(value)
 134 #define MC_DC35(value)          0x0230(value)
 135 #define MC_DC36(value)          0x0240(value)
 136 #define MC_DC37(value)          0x0250(value)
 137 #define MC_DC38(value)          0x0260(value)
 138 #define MC_DC39(value)          0x0270(value)
 139 #define MC_DC40(value)          0x0280(value)
 140 #define MC_DC41(value)          0x0290(value)
 141 #define MC_DC42(value)          0x02A0(value)
 142 #define MC_DC43(value)          0x02B0(value)
 143 #define MC_DC44(value)          0x02C0(value)
 144 #define MC_DC45(value)          0x02D0(value)
 145 #define MC_DC46(value)          0x02E0(value)
 146
 147 #define RCU_OFFSET  0xBF203000
 148 #define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
 149 #define RCU_STS          (RCU_OFFSET + 0x0014)
 150
 151 #define CGU_OFFSET  0xBF103000
 152 #define  PLL0_CFG     (CGU_OFFSET + 0x0004)
 153 #define  PLL1_CFG     (CGU_OFFSET + 0x0008)
 154 #define  PLL2_CFG     (CGU_OFFSET + 0x000C)
 155 #define  CGU_SYS      (CGU_OFFSET + 0x0010)
 156 #define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
 157 #define  IF_CLK       (CGU_OFFSET + 0x0018)
 158 #define  CGU_SMD      (CGU_OFFSET + 0x0020)
 159 #define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
 160 #define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
 161 #define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
 162 #define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
 163 #define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
 164 #define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
 165 #define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
 166
 167 //05252006
 168 #define  pll0_35MHz_CONFIG 0x9D861059
 169 #define  pll1_35MHz_CONFIG 0x1A260CD9
 170 #define  pll2_35MHz_CONFIG 0x8000f1e5
 171 #define  pll0_36MHz_CONFIG 0x1000125D
 172 #define  pll1_36MHz_CONFIG 0x1B1E0C99
 173 #define  pll2_36MHz_CONFIG 0x8002f2a1
 174 //05252006
 175
 176 //06063001-joelin disable the PCI CFRAME mask -start
 177 /*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
 178 But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
 179
 180 The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
 181 The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
 182 */
 183 #define PCI_CR_PR_OFFSET  0xBE105400
 184 #define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
 185 #define PCI_CONFIG_SPACE  0xB7000000
 186 #define CS_CFM          (PCI_CONFIG_SPACE + 0x6C)
 187 //06063001-joelin disable the PCI CFRAME mask -end
 188         .set    noreorder
 189
 190
 191 /*
 192  * void ebu_init(void)
 193  */
 194         .globl  ebu_init
 195         .ent    ebu_init
 196 ebu_init:
 197
 198 #if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
 199         defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
 200         defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
 201         defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
 202
 203         li      t1, EBU_MODUL_BASE
 204 #if defined(CONFIG_EBU_ADDSEL0)
 205         li      t2, CONFIG_EBU_ADDSEL0
 206         sw      t2, EBU_ADDSEL0(t1)
 207 #endif
 208 #if defined(CONFIG_EBU_ADDSEL1)
 209         li      t2, CONFIG_EBU_ADDSEL1
 210         sw      t2, EBU_ADDSEL1(t1)
 211 #endif
 212 #if defined(CONFIG_EBU_ADDSEL2)
 213         li      t2, CONFIG_EBU_ADDSEL2
 214         sw      t2, EBU_ADDSEL2(t1)
 215 #endif
 216 #if defined(CONFIG_EBU_ADDSEL3)
 217         li      t2, CONFIG_EBU_ADDSEL3
 218         sw      t2, EBU_ADDSEL3(t1)
 219 #endif
 220
 221 #if defined(CONFIG_EBU_BUSCON0)
 222         li      t2, CONFIG_EBU_BUSCON0
 223         sw      t2, EBU_BUSCON0(t1)
 224 #endif
 225 #if defined(CONFIG_EBU_BUSCON1)
 226         li      t2, CONFIG_EBU_BUSCON1
 227         sw      t2, EBU_BUSCON1(t1)
 228 #endif
 229 #if defined(CONFIG_EBU_BUSCON2)
 230         li      t2, CONFIG_EBU_BUSCON2
 231         sw      t2, EBU_BUSCON2(t1)
 232 #endif
 233 #if defined(CONFIG_EBU_BUSCON3)
 234         li      t2, CONFIG_EBU_BUSCON3
 235         sw      t2, EBU_BUSCON3(t1)
 236 #endif
 237
 238 #endif
 239
 240         j       ra
 241         nop
 242
 243         .end    ebu_init
 244
 245
 246 /*
 247  * void cgu_init(long)
 248  *
 249  * a0 has the clock value
 250  */
 251         .globl  cgu_init
 252         .ent    cgu_init
 253 cgu_init:
 254         li  t2, CGU_SYS
 255         lw  t2,0(t2)
 256         beq t2,a0,freq_up2date
 257         nop
 258
 259         li  t2, RCU_STS
 260         lw  t2, 0(t2)
 261         and t2,0x00020000
 262         beq t2,0x00020000,boot_36MHZ
 263         nop
 264 //05252006
 265         li  t1, PLL0_CFG
 266         li  t2, pll0_35MHz_CONFIG
 267         sw      t2,0(t1)
 268         li  t1, PLL1_CFG
 269         li  t2, pll1_35MHz_CONFIG
 270         sw      t2,0(t1)
 271         li  t1, PLL2_CFG
 272         li  t2, pll2_35MHz_CONFIG
 273         sw      t2,0(t1)
 274         li  t1, CGU_SYS
 275         sw      a0,0(t1)
 276         li  t1, RCU_RST_REQ
 277         li  t2, 0x40000008
 278         sw      t2,0(t1)
 279         b   wait_reset
 280         nop
 281 boot_36MHZ:
 282         li  t1, PLL0_CFG
 283         li  t2, pll0_36MHz_CONFIG
 284         sw      t2,0(t1)
 285         li  t1, PLL1_CFG
 286         li  t2, pll1_36MHz_CONFIG
 287         sw      t2,0(t1)
 288         li  t1, PLL2_CFG
 289         li  t2, pll2_36MHz_CONFIG
 290         sw      t2,0(t1)
 291         li  t1, CGU_SYS
 292         sw      a0,0(t1)
 293         li  t1, RCU_RST_REQ
 294         li  t2, 0x40000008
 295         sw      t2,0(t1)
 296 //05252006
 297
 298 wait_reset:
 299         b   wait_reset
 300         nop
 301 freq_up2date:
 302         j ra
 303         nop
 304
 305         .end    cgu_init
 306
 307 #ifndef CONFIG_USE_DDR_RAM
 308 /*
 309  * void sdram_init(long)
 310  *
 311  * a0 has the clock value
 312  */
 313         .globl  sdram_init
 314         .ent    sdram_init
 315 sdram_init:
 316
 317         /* SDRAM Initialization
 318          */
 319         li      t1, MC_MODUL_BASE
 320
 321         /* Clear Error log registers */
 322         sw      zero, MC_ERRCAUSE(t1)
 323         sw      zero, MC_ERRADDR(t1)
 324
 325         /* Enable SDRAM module in memory controller */
 326         li      t3, MC_SDRAM_ENABLE
 327         lw      t2, MC_CON(t1)
 328         or      t3, t2, t3
 329         sw      t3, MC_CON(t1)
 330
 331         li      t1, MC_SDR_MODUL_BASE
 332
 333         /* disable the controller */
 334         li      t2, 0
 335         sw      t2, MC_CTRLENA(t1)
 336
 337         li      t2, 0x822
 338         sw      t2, MC_IOGP(t1)
 339
 340         li      t2, 0x2
 341         sw      t2, MC_CFGDW(t1)
 342
 343         /* Set CAS Latency */
 344         li      t2, 0x00000020
 345         sw      t2, MC_MRSCODE(t1)
 346
 347         /* Set CS0 to SDRAM parameters */
 348         li      t2, 0x000014d8
 349         sw      t2, MC_CFGPB0(t1)
 350
 351         /* Set SDRAM latency parameters */
 352         li      t2, 0x00036325;   /* BC PC100 */
 353         sw      t2, MC_LATENCY(t1)
 354
 355         /* Set SDRAM refresh rate */
 356         li      t2, 0x00000C30
 357         sw      t2, MC_TREFRESH(t1)
 358
 359         /* Clear Power-down registers */
 360         sw      zero, MC_SELFRFSH(t1)
 361
 362         /* Finally enable the controller */
 363         li      t2, 1
 364         sw      t2, MC_CTRLENA(t1)
 365
 366         j       ra
 367         nop
 368
 369         .end    sdram_init
 370
 371 #endif /* !CONFIG_USE_DDR_RAM */
 372
 373 #ifdef CONFIG_USE_DDR_RAM
 374 /*
 375  * void ddrram_init(long)
 376  *
 377  * a0 has the clock value
 378  */
 379         .globl  ddrram_init
 380         .ent    ddrram_init
 381 ddrram_init:
 382
 383         /* DDR-DRAM Initialization
 384          */
 385         li      t1, MC_MODUL_BASE
 386
 387         /* Clear Error log registers */
 388         sw      zero, MC_ERRCAUSE(t1)
 389         sw      zero, MC_ERRADDR(t1)
 390
 391         /* Enable DDR module in memory controller */
 392         li      t3, MC_DDRRAM_ENABLE
 393         lw      t2, MC_CON(t1)
 394         or      t3, t2, t3
 395         sw      t3, MC_CON(t1)
 396
 397         li      t1, MC_DDR_MODUL_BASE
 398
 399         /* Write configuration to DDR controller registers */
 400         li      t2, MC_DC0_VALUE
 401         sw      t2, MC_DC00(t1)
 402
 403         li      t2, MC_DC1_VALUE
 404         sw      t2, MC_DC01(t1)
 405
 406         li      t2, MC_DC2_VALUE
 407         sw      t2, MC_DC02(t1)
 408
 409         li      t2, MC_DC3_VALUE
 410         sw      t2, MC_DC03(t1)
 411
 412         li      t2, MC_DC4_VALUE
 413         sw      t2, MC_DC04(t1)
 414
 415         li      t2, MC_DC5_VALUE
 416         sw      t2, MC_DC05(t1)
 417
 418         li      t2, MC_DC6_VALUE
 419         sw      t2, MC_DC06(t1)
 420
 421         li      t2, MC_DC7_VALUE
 422         sw      t2, MC_DC07(t1)
 423
 424         li      t2, MC_DC8_VALUE
 425         sw      t2, MC_DC08(t1)
 426
 427         li      t2, MC_DC9_VALUE
 428         sw      t2, MC_DC09(t1)
 429
 430         li      t2, MC_DC10_VALUE
 431         sw      t2, MC_DC10(t1)
 432
 433         li      t2, MC_DC11_VALUE
 434         sw      t2, MC_DC11(t1)
 435
 436         li      t2, MC_DC12_VALUE
 437         sw      t2, MC_DC12(t1)
 438
 439         li      t2, MC_DC13_VALUE
 440         sw      t2, MC_DC13(t1)
 441
 442         li      t2, MC_DC14_VALUE
 443         sw      t2, MC_DC14(t1)
 444
 445         li      t2, MC_DC15_VALUE
 446         sw      t2, MC_DC15(t1)
 447
 448         li      t2, MC_DC16_VALUE
 449         sw      t2, MC_DC16(t1)
 450
 451         li      t2, MC_DC17_VALUE
 452         sw      t2, MC_DC17(t1)
 453
 454         li      t2, MC_DC18_VALUE
 455         sw      t2, MC_DC18(t1)
 456
 457         li      t2, MC_DC19_VALUE
 458         sw      t2, MC_DC19(t1)
 459
 460         li      t2, MC_DC20_VALUE
 461         sw      t2, MC_DC20(t1)
 462
 463         li      t2, MC_DC21_VALUE
 464         sw      t2, MC_DC21(t1)
 465
 466         li      t2, MC_DC22_VALUE
 467         sw      t2, MC_DC22(t1)
 468
 469         li      t2, MC_DC23_VALUE
 470         sw      t2, MC_DC23(t1)
 471
 472         li      t2, MC_DC24_VALUE
 473         sw      t2, MC_DC24(t1)
 474
 475         li      t2, MC_DC25_VALUE
 476         sw      t2, MC_DC25(t1)
 477
 478         li      t2, MC_DC26_VALUE
 479         sw      t2, MC_DC26(t1)
 480
 481         li      t2, MC_DC27_VALUE
 482         sw      t2, MC_DC27(t1)
 483
 484         li      t2, MC_DC28_VALUE
 485         sw      t2, MC_DC28(t1)
 486
 487         li      t2, MC_DC29_VALUE
 488         sw      t2, MC_DC29(t1)
 489
 490         li      t2, MC_DC30_VALUE
 491         sw      t2, MC_DC30(t1)
 492
 493         li      t2, MC_DC31_VALUE
 494         sw      t2, MC_DC31(t1)
 495
 496         li      t2, MC_DC32_VALUE
 497         sw      t2, MC_DC32(t1)
 498
 499         li      t2, MC_DC33_VALUE
 500         sw      t2, MC_DC33(t1)
 501
 502         li      t2, MC_DC34_VALUE
 503         sw      t2, MC_DC34(t1)
 504
 505         li      t2, MC_DC35_VALUE
 506         sw      t2, MC_DC35(t1)
 507
 508         li      t2, MC_DC36_VALUE
 509         sw      t2, MC_DC36(t1)
 510
 511         li      t2, MC_DC37_VALUE
 512         sw      t2, MC_DC37(t1)
 513
 514         li      t2, MC_DC38_VALUE
 515         sw      t2, MC_DC38(t1)
 516
 517         li      t2, MC_DC39_VALUE
 518         sw      t2, MC_DC39(t1)
 519
 520         li      t2, MC_DC40_VALUE
 521         sw      t2, MC_DC40(t1)
 522
 523         li      t2, MC_DC41_VALUE
 524         sw      t2, MC_DC41(t1)
 525
 526         li      t2, MC_DC42_VALUE
 527         sw      t2, MC_DC42(t1)
 528
 529         li      t2, MC_DC43_VALUE
 530         sw      t2, MC_DC43(t1)
 531
 532         li      t2, MC_DC44_VALUE
 533         sw      t2, MC_DC44(t1)
 534
 535         li      t2, MC_DC45_VALUE
 536         sw      t2, MC_DC45(t1)
 537
 538         li      t2, MC_DC46_VALUE
 539         sw      t2, MC_DC46(t1)
 540
 541         li      t2, 0x00000100
 542         sw      t2, MC_DC03(t1)
 543
 544         j       ra
 545         nop
 546
 547         .end    ddrram_init
 548 #endif /* CONFIG_USE_DDR_RAM */
 549
 550         .globl  lowlevel_init
 551         .ent    lowlevel_init
 552 lowlevel_init:
 553         /* EBU, CGU and SDRAM/DDR-RAM Initialization.
 554          */
 555         move    t0, ra
 556         /* We rely on the fact that non of the following ..._init() functions
 557          * modify t0
 558          */
 559 #if defined(DDR166)
 560         /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
 561         li  a0,0xe8
 562 #elif defined(DDR133)
 563         /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
 564         li  a0,0xe9
 565 #else /* defined(DDR111) */
 566         /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
 567         li  a0,0xea
 568 #endif
 569         bal     cgu_init
 570         nop
 571
 572         bal     ebu_init
 573         nop
 574
 575 //06063001-joelin disable the PCI CFRAME mask-start
 576 #ifdef DISABLE_CFRAME
 577         li  t1, PCI_CR_PCI      //mw bf103034 80000000
 578         li  t2, 0x80000000
 579         sw      t2,0(t1)
 580
 581         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 582         li  t2, 0x103
 583         sw  t2,0(t1)
 584
 585         li  t1, CS_CFM                  //mw b700006c 0
 586         li  t2, 0x00
 587         sw  t2, 0(t1)
 588
 589         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 590         li  t2, 0x1000103
 591         sw  t2, 0(t1)
 592 #endif
 593 //06063001-joelin disable the PCI CFRAME mask-end
 594
 595 #ifdef CONFIG_USE_DDR_RAM
 596         bal     ddrram_init
 597         nop
 598 #else
 599         bal     sdram_init
 600         nop
 601 #endif
 602         move    ra, t0
 603         j       ra
 604         nop
 605
 606         .end    lowlevel_init