2 * Lantiq switch ethernet driver for Danube family.
4 * Based on INCA-IP driver:
5 * (C) Copyright 2003-2004
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef __DRIVERS_IFX_SW_H__
26 #define __DRIVERS_IFX_SW_H__
28 #define DANUBE_PPE32_BASE 0xBE180000
29 #define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
31 #define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
32 #define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
33 #define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
34 #define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
35 #define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
36 #define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
37 #define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
38 #define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
39 #define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
40 #define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
41 #define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
42 #define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
43 #define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
44 #define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
45 #define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
46 #define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
47 #define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
48 #define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
49 #define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
50 #define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
51 #define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
52 #define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
53 #define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
54 #define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
58 #define DANUBE_DMA_BASE 0xBE104100
60 typedef struct IfxDMA_s
62 unsigned long dma_clc
; /*0x0000*/
63 unsigned long dma_rsvd1
[1]; /* for mapping */ /*0x0004*/
64 unsigned long dma_id
; /*0x0008*/
65 unsigned long dma_rsvd2
[1]; /* for mapping */ /*0x000C*/
66 unsigned long dma_ctrl
; /*0x0010*/
67 unsigned long dma_cpoll
; /*0x0014*/
68 unsigned long dma_cs
; /*0x0018*/
69 unsigned long dma_cctrl
; /*0x001C*/
70 unsigned long dma_cdba
; /*0x0020*/
71 unsigned long dma_cdlen
; /*0x0024*/
72 unsigned long dma_cis
; /*0x0028*/
73 unsigned long dma_cie
; /*0x002C*/
74 unsigned long dma_rsvd3
[4]; /* for mapping */ /*0x0030*/
75 unsigned long dma_ps
; /*0x0040*/
76 unsigned long dma_pctrl
; /*0x0044*/
77 unsigned long dma_rsvd4
[43]; /* for mapping */ /*0x0048*/
78 unsigned long dma_irnen
; /*0x00F4*/
79 unsigned long dma_irncr
; /*0x00F8*/
80 unsigned long dma_irnicr
; /*0x00FC*/
83 /* Register access macros */
84 #define dma_readl(reg) \
86 #define dma_writel(reg,value) \
87 writel((value), &pDma->reg)
89 int lq_eth_initialize(bd_t
* bis
);
91 #endif /* __DRIVERS_IFX_SW_H__ */
This page took 0.052948 seconds and 5 git commands to generate.