[ar7] refresh patches and remove trailing whitespaces
[openwrt.git] / package / uboot-lantiq / files / drivers / serial / ifx_asc.c
1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * (C) Copyright 2009
5 * Infineon Technologies AG, http://www.infineon.com
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <config.h>
27 #include <common.h>
28 #include <asm/io.h>
29 #include <asm/addrspace.h>
30
31 #include "ifx_asc.h"
32
33 #define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask))
34 #define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask))
35 #define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
36
37 #undef DEBUG_ASC_RAW
38 #ifdef DEBUG_ASC_RAW
39 #define DEBUG_ASC_RAW_RX_BUF 0xA0800000
40 #define DEBUG_ASC_RAW_TX_BUF 0xA0900000
41 #endif
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
46
47 /*
48 * FDV fASC
49 * BaudRate = ----- * --------------------
50 * 512 16 * (ReloadValue+1)
51 */
52
53 /*
54 * FDV fASC
55 * ReloadValue = ( ----- * --------------- ) - 1
56 * 512 16 * BaudRate
57 */
58 static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
59 {
60 u32 clock = fasc / 16;
61
62 u32 fdv; /* best fdv */
63 u32 reload = 0; /* best reload */
64 u32 diff; /* smallest diff */
65 u32 idiff; /* current diff */
66 u32 ireload; /* current reload */
67 u32 i; /* current fdv */
68 u32 result; /* current resulting baudrate */
69
70 if (clock > 0x7FFFFF)
71 clock /= 512;
72 else
73 baudrate *= 512;
74
75 fdv = 512; /* start with 1:1 fraction */
76 diff = baudrate; /* highest possible */
77
78 /* i is the test fdv value -- start with the largest possible */
79 for (i = 512; i > 0; i--)
80 {
81 ireload = (clock * i) / baudrate;
82 if (ireload < 1)
83 break; /* already invalid */
84 result = (clock * i) / ireload;
85
86 idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
87 if (idiff == 0)
88 {
89 fdv = i;
90 reload = ireload;
91 break; /* can't do better */
92 }
93 else if (idiff < diff)
94 {
95 fdv = i; /* best so far */
96 reload = ireload;
97 diff = idiff; /* update lowest diff*/
98 }
99 }
100
101 *pfdv = (fdv == 512) ? 0 : fdv;
102 *preload = reload - 1;
103 }
104
105
106 void serial_setbrg (void)
107 {
108 u32 ReloadValue, fdv;
109
110 serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
111
112 /* Disable Baud Rate Generator; BG should only be written when R=0 */
113 CLEAR_BIT(asc_con, ASCCON_R);
114
115 /* Enable Fractional Divider */
116 SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */
117
118 /* Set fractional divider value */
119 asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
120
121 /* Set reload value in BG */
122 asc_writel(asc_bg, ReloadValue);
123
124 /* Enable Baud Rate Generator */
125 SET_BIT(asc_con, ASCCON_R); /* R = 1 */
126 }
127
128
129 int serial_init (void)
130 {
131
132 /* and we have to set CLC register*/
133 CLEAR_BIT(asc_clc, ASCCLC_DISS);
134 SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
135
136 /* initialy we are in async mode */
137 asc_writel(asc_con, ASCCON_M_8ASYNC);
138
139 /* select input port */
140 asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
141
142 /* TXFIFO's filling level */
143 SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
144 ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
145 /* enable TXFIFO */
146 SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
147
148 /* RXFIFO's filling level */
149 SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
150 ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
151 /* enable RXFIFO */
152 SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
153
154 /* set baud rate */
155 serial_setbrg();
156
157 /* enable error signals & Receiver enable */
158 SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
159
160 return 0;
161 }
162
163
164 void serial_putc (const char c)
165 {
166 u32 txFl = 0;
167 #ifdef DEBUG_ASC_RAW
168 static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
169 *debug++=c;
170 #endif
171 if (c == '\n')
172 serial_putc ('\r');
173 /* check do we have a free space in the TX FIFO */
174 /* get current filling level */
175 do {
176 txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
177 }
178 while ( txFl == ASC_TXFIFO_FULL );
179
180 asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
181
182 /* check for errors */
183 if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
184 SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
185 return;
186 }
187 }
188
189 void serial_puts (const char *s)
190 {
191 while (*s) {
192 serial_putc (*s++);
193 }
194 }
195
196 int serial_getc (void)
197 {
198 char c;
199 while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
200 c = (char)(asc_readl(asc_rbuf) & 0xff);
201
202 #ifdef DEBUG_ASC_RAW
203 static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
204 *debug++=c;
205 #endif
206 return c;
207 }
208
209
210 int serial_tstc (void)
211 {
212 int res = 1;
213
214 if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
215 res = 0;
216 }
217 return res;
218 }
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