[ar7] refresh patches and remove trailing whitespaces
[openwrt.git] / package / uboot-lantiq / files / include / configs / easy50712.h
1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * This file contains the configuration parameters for the Danube reference board.
26 */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /* #define DEBUG */
32
33 #define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
34 #define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
35 #define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
36 #define CONFIG_EASY50712 1 /* on the Danube Reference Board */
37
38 #define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */
39
40 #define CONFIG_SYS_MAX_RAM 32*1024*1024
41
42 #define CONFIG_FLASH_CFI_DRIVER 1
43
44 #define CONFIG_SYS_INIT_RAM_LOCK_MIPS
45 #ifdef CONFIG_SYS_RAMBOOT
46 //#warning CONFIG_SYS_RAMBOOT
47 #define CONFIG_SKIP_LOWLEVEL_INIT
48 #else /* CONFIG_SYS_RAMBOOT */
49
50 #define CONFIG_SYS_EBU_BOOT
51
52 #ifdef CONFIG_USE_DDR_RAM
53 /* FIXME: should not need these workarounds */
54 #define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */
55 #endif
56
57 #define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
58
59 #endif /* CONFIG_SYS_RAMBOOT */
60
61 #if 1
62 #ifndef CPU_CLOCK_RATE
63 #define CPU_CLOCK_RATE (ifx_get_cpuclk())
64 #endif
65 #endif
66
67 #define CONFIG_SYS_PROMPT "DANUBE => " /* Monitor Command Prompt */
68
69 #undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
70
71 /*
72 * Include common defines/options for all Infineon boards
73 */
74 #include "ifx-common.h"
75
76 /*
77 * Cache Configuration (cpu/chip specific, Danube)
78 */
79 #define CONFIG_SYS_DCACHE_SIZE 16384
80 #define CONFIG_SYS_ICACHE_SIZE 16384
81 #define CONFIG_SYS_CACHELINE_SIZE 32
82 #define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
83
84 #define CONFIG_NET_MULTI
85 #if 0
86 #define CONFIG_M4530_ETH
87 #define CONFIG_M4530_FPGA
88 #endif
89
90 #define CONFIG_IFX_ETOP
91 #define CLK_OUT2_25MHZ
92 #define CONFIG_EXTRA_SWITCH
93
94 #define CONFIG_RMII /* use interface in RMII mode */
95
96 #define CONFIG_MII
97 #define CONFIG_CMD_MII
98
99 #define CONFIG_IFX_ASC
100
101 #ifdef CONFIG_USE_ASC0
102 #define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
103 #else
104 #define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
105 #endif
106
107 #ifdef CONFIG_SYS_RAMBOOT
108 /* Configuration of EBU: */
109 /* starting address from 0xb0000000 */
110 /* make the flash available from RAM boot */
111 # define CONFIG_EBU_ADDSEL0 0x10000031
112 # define CONFIG_EBU_BUSCON0 0x0001D7FF
113 #endif
114
115 #define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
116
117 #endif /* __CONFIG_H */
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