package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S

   1 /*
   2  *  Memory sub-system initialization code for Danube board.
   3  *  Andre Messerschmidt
   4  *  Copyright (c) 2005  Infineon Technologies AG
   5  *
   6  *  Based on Inca-IP code
   7  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /* History:
  28       peng liu May 25, 2006, for PLL setting after reset, 05252006
  29  */
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/regdef.h>
  33
  34 #if defined(CONFIG_USE_DDR_PSC_32)
  35 #include "ddr_settings_psc_32.h"
  36 #define DDR166
  37 #elif defined(CONFIG_USE_DDR_PSC_64)
  38 #include "ddr_settings_psc_64.h"
  39 #define DDR166
  40 #else
  41 #error "missing definition for RAM"
  42 #endif
  43
  44 #define EBU_MODUL_BASE          0xBE105300
  45 #define EBU_CLC(value)          0x0000(value)
  46 #define EBU_CON(value)          0x0010(value)
  47 #define EBU_ADDSEL0(value)      0x0020(value)
  48 #define EBU_ADDSEL1(value)      0x0024(value)
  49 #define EBU_ADDSEL2(value)      0x0028(value)
  50 #define EBU_ADDSEL3(value)      0x002C(value)
  51 #define EBU_BUSCON0(value)      0x0060(value)
  52 #define EBU_BUSCON1(value)      0x0064(value)
  53 #define EBU_BUSCON2(value)      0x0068(value)
  54 #define EBU_BUSCON3(value)      0x006C(value)
  55
  56 #define MC_MODUL_BASE           0xBF800000
  57 #define MC_ERRCAUSE(value)      0x0010(value)
  58 #define MC_ERRADDR(value)       0x0020(value)
  59 #define MC_CON(value)           0x0060(value)
  60
  61 #define MC_SRAM_ENABLE          0x00000004
  62 #define MC_SDRAM_ENABLE         0x00000002
  63 #define MC_DDRRAM_ENABLE        0x00000001
  64
  65 #define MC_SDR_MODUL_BASE       0xBF800200
  66 #define MC_IOGP(value)          0x0000(value)
  67 #define MC_CTRLENA(value)       0x0010(value)
  68 #define MC_MRSCODE(value)       0x0020(value)
  69 #define MC_CFGDW(value)         0x0030(value)
  70 #define MC_CFGPB0(value)        0x0040(value)
  71 #define MC_LATENCY(value)       0x0080(value)
  72 #define MC_TREFRESH(value)      0x0090(value)
  73 #define MC_SELFRFSH(value)      0x00A0(value)
  74
  75 #define MC_DDR_MODUL_BASE       0xBF801000
  76 #define MC_DC00(value)          0x0000(value)
  77 #define MC_DC01(value)          0x0010(value)
  78 #define MC_DC02(value)          0x0020(value)
  79 #define MC_DC03(value)          0x0030(value)
  80 #define MC_DC04(value)          0x0040(value)
  81 #define MC_DC05(value)          0x0050(value)
  82 #define MC_DC06(value)          0x0060(value)
  83 #define MC_DC07(value)          0x0070(value)
  84 #define MC_DC08(value)          0x0080(value)
  85 #define MC_DC09(value)          0x0090(value)
  86 #define MC_DC10(value)          0x00A0(value)
  87 #define MC_DC11(value)          0x00B0(value)
  88 #define MC_DC12(value)          0x00C0(value)
  89 #define MC_DC13(value)          0x00D0(value)
  90 #define MC_DC14(value)          0x00E0(value)
  91 #define MC_DC15(value)          0x00F0(value)
  92 #define MC_DC16(value)          0x0100(value)
  93 #define MC_DC17(value)          0x0110(value)
  94 #define MC_DC18(value)          0x0120(value)
  95 #define MC_DC19(value)          0x0130(value)
  96 #define MC_DC20(value)          0x0140(value)
  97 #define MC_DC21(value)          0x0150(value)
  98 #define MC_DC22(value)          0x0160(value)
  99 #define MC_DC23(value)          0x0170(value)
 100 #define MC_DC24(value)          0x0180(value)
 101 #define MC_DC25(value)          0x0190(value)
 102 #define MC_DC26(value)          0x01A0(value)
 103 #define MC_DC27(value)          0x01B0(value)
 104 #define MC_DC28(value)          0x01C0(value)
 105 #define MC_DC29(value)          0x01D0(value)
 106 #define MC_DC30(value)          0x01E0(value)
 107 #define MC_DC31(value)          0x01F0(value)
 108 #define MC_DC32(value)          0x0200(value)
 109 #define MC_DC33(value)          0x0210(value)
 110 #define MC_DC34(value)          0x0220(value)
 111 #define MC_DC35(value)          0x0230(value)
 112 #define MC_DC36(value)          0x0240(value)
 113 #define MC_DC37(value)          0x0250(value)
 114 #define MC_DC38(value)          0x0260(value)
 115 #define MC_DC39(value)          0x0270(value)
 116 #define MC_DC40(value)          0x0280(value)
 117 #define MC_DC41(value)          0x0290(value)
 118 #define MC_DC42(value)          0x02A0(value)
 119 #define MC_DC43(value)          0x02B0(value)
 120 #define MC_DC44(value)          0x02C0(value)
 121 #define MC_DC45(value)          0x02D0(value)
 122 #define MC_DC46(value)          0x02E0(value)
 123
 124 #define RCU_OFFSET  0xBF203000
 125 #define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
 126 #define RCU_STS          (RCU_OFFSET + 0x0014)
 127
 128 #define CGU_OFFSET  0xBF103000
 129 #define  PLL0_CFG     (CGU_OFFSET + 0x0004)
 130 #define  PLL1_CFG     (CGU_OFFSET + 0x0008)
 131 #define  PLL2_CFG     (CGU_OFFSET + 0x000C)
 132 #define  CGU_SYS      (CGU_OFFSET + 0x0010)
 133 #define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
 134 #define  IF_CLK       (CGU_OFFSET + 0x0018)
 135 #define  CGU_SMD      (CGU_OFFSET + 0x0020)
 136 #define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
 137 #define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
 138 #define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
 139 #define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
 140 #define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
 141 #define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
 142 #define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
 143
 144 //05252006
 145 #define  pll0_35MHz_CONFIG 0x9D861059
 146 #define  pll1_35MHz_CONFIG 0x1A260CD9
 147 #define  pll2_35MHz_CONFIG 0x8000f1e5
 148 #define  pll0_36MHz_CONFIG 0x1000125D
 149 #define  pll1_36MHz_CONFIG 0x1B1E0C99
 150 #define  pll2_36MHz_CONFIG 0x8002f2a1
 151 //05252006
 152
 153 //06063001-joelin disable the PCI CFRAME mask -start
 154 /*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
 155 But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
 156
 157 The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
 158 The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
 159 */
 160 #define PCI_CR_PR_OFFSET  0xBE105400
 161 #define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
 162 #define PCI_CONFIG_SPACE  0xB7000000
 163 #define CS_CFM          (PCI_CONFIG_SPACE + 0x6C)
 164 //06063001-joelin disable the PCI CFRAME mask -end
 165         .set    noreorder
 166
 167
 168 /*
 169  * void ebu_init(void)
 170  */
 171         .globl  ebu_init
 172         .ent    ebu_init
 173 ebu_init:
 174
 175         j       ra
 176         nop
 177
 178         .end    ebu_init
 179
 180
 181 /*
 182  * void cgu_init(long)
 183  *
 184  * a0 has the clock value
 185  */
 186         .globl  cgu_init
 187         .ent    cgu_init
 188 cgu_init:
 189         li  t2, CGU_SYS
 190         lw  t2,0(t2)
 191         beq t2,a0,freq_up2date
 192         nop
 193
 194         li  t2, RCU_STS
 195         lw  t2, 0(t2)
 196         and t2,0x00020000
 197         beq t2,0x00020000,boot_36MHZ
 198         nop
 199 //05252006
 200         li  t1, PLL0_CFG
 201         li  t2, pll0_35MHz_CONFIG
 202         sw      t2,0(t1)
 203         li  t1, PLL1_CFG
 204         li  t2, pll1_35MHz_CONFIG
 205         sw      t2,0(t1)
 206         li  t1, PLL2_CFG
 207         li  t2, pll2_35MHz_CONFIG
 208         sw      t2,0(t1)
 209         li  t1, CGU_SYS
 210         sw      a0,0(t1)
 211         li  t1, RCU_RST_REQ
 212         li  t2, 0x40000008
 213         sw      t2,0(t1)
 214         b   wait_reset
 215         nop
 216 boot_36MHZ:
 217         li  t1, PLL0_CFG
 218         li  t2, pll0_36MHz_CONFIG
 219         sw      t2,0(t1)
 220         li  t1, PLL1_CFG
 221         li  t2, pll1_36MHz_CONFIG
 222         sw      t2,0(t1)
 223         li  t1, PLL2_CFG
 224         li  t2, pll2_36MHz_CONFIG
 225         sw      t2,0(t1)
 226         li  t1, CGU_SYS
 227         sw      a0,0(t1)
 228         li  t1, RCU_RST_REQ
 229         li  t2, 0x40000008
 230         sw      t2,0(t1)
 231 //05252006
 232
 233 wait_reset:
 234         b   wait_reset
 235         nop
 236 freq_up2date:
 237         j ra
 238         nop
 239
 240         .end    cgu_init
 241
 242         .globl  lowlevel_init
 243         .ent    lowlevel_init
 244 lowlevel_init:
 245         /* EBU, CGU and SDRAM/DDR-RAM Initialization.
 246          */
 247         move    t0, ra
 248         /* We rely on the fact that non of the following ..._init() functions
 249          * modify t0
 250          */
 251
 252         bal     ebu_init
 253         nop
 254
 255 //06063001-joelin disable the PCI CFRAME mask-start
 256 #ifdef DISABLE_CFRAME
 257         li  t1, PCI_CR_PCI      //mw bf103034 80000000
 258         li  t2, 0x80000000
 259         sw      t2,0(t1)
 260
 261         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 262         li  t2, 0x103
 263         sw  t2,0(t1)
 264
 265         li  t1, CS_CFM                  //mw b700006c 0
 266         li  t2, 0x00
 267         sw  t2, 0(t1)
 268
 269         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 270         li  t2, 0x1000103
 271         sw  t2, 0(t1)
 272 #endif
 273 //06063001-joelin disable the PCI CFRAME mask-end
 274
 275         move    ra, t0
 276         j       ra
 277         nop
 278
 279         .end    lowlevel_init