package/rt2x00/src/rt2500pci.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: Data structures and registers for the rt2500pci module.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #ifndef RT2500PCI_H
  28 #define RT2500PCI_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF2522                          0x0000
  34 #define RF2523                          0x0001
  35 #define RF2524                          0x0002
  36 #define RF2525                          0x0003
  37 #define RF2525E                         0x0004
  38 #define RF5222                          0x0010
  39
  40 /*
  41  * RT2560 version
  42  */
  43 #define RT2560_VERSION_B                2
  44 #define RT2560_VERSION_C                3
  45 #define RT2560_VERSION_D                4
  46
  47 /*
  48  * Signal information.
  49  */
  50 #define MAX_RX_SSI                      -1
  51 #define MAX_RX_NOISE                    -110
  52 #define DEFAULT_RSSI_OFFSET             121
  53
  54 /*
  55  * Register layout information.
  56  */
  57 #define CSR_REG_BASE                    0x0000
  58 #define CSR_REG_SIZE                    0x0174
  59 #define EEPROM_BASE                     0x0000
  60 #define EEPROM_SIZE                     0x0200
  61 #define BBP_SIZE                        0x0040
  62
  63 /*
  64  * Control/Status Registers(CSR).
  65  * Some values are set in TU, whereas 1 TU == 1024 us.
  66  */
  67
  68 /*
  69  * CSR0: ASIC revision number.
  70  */
  71 #define CSR0                            0x0000
  72
  73 /*
  74  * CSR1: System control register.
  75  * SOFT_RESET: Software reset, 1: reset, 0: normal.
  76  * BBP_RESET: Hardware reset, 1: reset, 0, release.
  77  * HOST_READY: Host ready after initialization.
  78  */
  79 #define CSR1                            0x0004
  80 #define CSR1_SOFT_RESET                 FIELD32(0x00000001)
  81 #define CSR1_BBP_RESET                  FIELD32(0x00000002)
  82 #define CSR1_HOST_READY                 FIELD32(0x00000004)
  83
  84 /*
  85  * CSR2: System admin status register (invalid).
  86  */
  87 #define CSR2                            0x0008
  88
  89 /*
  90  * CSR3: STA MAC address register 0.
  91  */
  92 #define CSR3                            0x000c
  93 #define CSR3_BYTE0                      FIELD32(0x000000ff)
  94 #define CSR3_BYTE1                      FIELD32(0x0000ff00)
  95 #define CSR3_BYTE2                      FIELD32(0x00ff0000)
  96 #define CSR3_BYTE3                      FIELD32(0xff000000)
  97
  98 /*
  99  * CSR4: STA MAC address register 1.
 100  */
 101 #define CSR4                            0x0010
 102 #define CSR4_BYTE4                      FIELD32(0x000000ff)
 103 #define CSR4_BYTE5                      FIELD32(0x0000ff00)
 104
 105 /*
 106  * CSR5: BSSID register 0.
 107  */
 108 #define CSR5                            0x0014
 109 #define CSR5_BYTE0                      FIELD32(0x000000ff)
 110 #define CSR5_BYTE1                      FIELD32(0x0000ff00)
 111 #define CSR5_BYTE2                      FIELD32(0x00ff0000)
 112 #define CSR5_BYTE3                      FIELD32(0xff000000)
 113
 114 /*
 115  * CSR6: BSSID register 1.
 116  */
 117 #define CSR6                            0x0018
 118 #define CSR6_BYTE4                      FIELD32(0x000000ff)
 119 #define CSR6_BYTE5                      FIELD32(0x0000ff00)
 120
 121 /*
 122  * CSR7: Interrupt source register.
 123  * Write 1 to clear.
 124  * TBCN_EXPIRE: Beacon timer expired interrupt.
 125  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 126  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 127  * TXDONE_TXRING: Tx ring transmit done interrupt.
 128  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 129  * TXDONE_PRIORING: Priority ring transmit done interrupt.
 130  * RXDONE: Receive done interrupt.
 131  * DECRYPTION_DONE: Decryption done interrupt.
 132  * ENCRYPTION_DONE: Encryption done interrupt.
 133  * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
 134  * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
 135  * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
 136  * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
 137  * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
 138  * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
 139  * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
 140  * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
 141  * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
 142  * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
 143  * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
 144
 145  */
 146 #define CSR7                            0x001c
 147 #define CSR7_TBCN_EXPIRE                FIELD32(0x00000001)
 148 #define CSR7_TWAKE_EXPIRE               FIELD32(0x00000002)
 149 #define CSR7_TATIMW_EXPIRE              FIELD32(0x00000004)
 150 #define CSR7_TXDONE_TXRING              FIELD32(0x00000008)
 151 #define CSR7_TXDONE_ATIMRING            FIELD32(0x00000010)
 152 #define CSR7_TXDONE_PRIORING            FIELD32(0x00000020)
 153 #define CSR7_RXDONE                     FIELD32(0x00000040)
 154 #define CSR7_DECRYPTION_DONE            FIELD32(0x00000080)
 155 #define CSR7_ENCRYPTION_DONE            FIELD32(0x00000100)
 156 #define CSR7_UART1_TX_TRESHOLD          FIELD32(0x00000200)
 157 #define CSR7_UART1_RX_TRESHOLD          FIELD32(0x00000400)
 158 #define CSR7_UART1_IDLE_TRESHOLD        FIELD32(0x00000800)
 159 #define CSR7_UART1_TX_BUFF_ERROR        FIELD32(0x00001000)
 160 #define CSR7_UART1_RX_BUFF_ERROR        FIELD32(0x00002000)
 161 #define CSR7_UART2_TX_TRESHOLD          FIELD32(0x00004000)
 162 #define CSR7_UART2_RX_TRESHOLD          FIELD32(0x00008000)
 163 #define CSR7_UART2_IDLE_TRESHOLD        FIELD32(0x00010000)
 164 #define CSR7_UART2_TX_BUFF_ERROR        FIELD32(0x00020000)
 165 #define CSR7_UART2_RX_BUFF_ERROR        FIELD32(0x00040000)
 166 #define CSR7_TIMER_CSR3_EXPIRE          FIELD32(0x00080000)
 167
 168 /*
 169  * CSR8: Interrupt mask register.
 170  * Write 1 to mask interrupt.
 171  * TBCN_EXPIRE: Beacon timer expired interrupt.
 172  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 173  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 174  * TXDONE_TXRING: Tx ring transmit done interrupt.
 175  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 176  * TXDONE_PRIORING: Priority ring transmit done interrupt.
 177  * RXDONE: Receive done interrupt.
 178  * DECRYPTION_DONE: Decryption done interrupt.
 179  * ENCRYPTION_DONE: Encryption done interrupt.
 180  * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
 181  * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
 182  * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
 183  * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
 184  * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
 185  * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
 186  * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
 187  * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
 188  * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
 189  * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
 190  * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
 191  */
 192 #define CSR8                            0x0020
 193 #define CSR8_TBCN_EXPIRE                FIELD32(0x00000001)
 194 #define CSR8_TWAKE_EXPIRE               FIELD32(0x00000002)
 195 #define CSR8_TATIMW_EXPIRE              FIELD32(0x00000004)
 196 #define CSR8_TXDONE_TXRING              FIELD32(0x00000008)
 197 #define CSR8_TXDONE_ATIMRING            FIELD32(0x00000010)
 198 #define CSR8_TXDONE_PRIORING            FIELD32(0x00000020)
 199 #define CSR8_RXDONE                     FIELD32(0x00000040)
 200 #define CSR8_DECRYPTION_DONE            FIELD32(0x00000080)
 201 #define CSR8_ENCRYPTION_DONE            FIELD32(0x00000100)
 202 #define CSR8_UART1_TX_TRESHOLD          FIELD32(0x00000200)
 203 #define CSR8_UART1_RX_TRESHOLD          FIELD32(0x00000400)
 204 #define CSR8_UART1_IDLE_TRESHOLD        FIELD32(0x00000800)
 205 #define CSR8_UART1_TX_BUFF_ERROR        FIELD32(0x00001000)
 206 #define CSR8_UART1_RX_BUFF_ERROR        FIELD32(0x00002000)
 207 #define CSR8_UART2_TX_TRESHOLD          FIELD32(0x00004000)
 208 #define CSR8_UART2_RX_TRESHOLD          FIELD32(0x00008000)
 209 #define CSR8_UART2_IDLE_TRESHOLD        FIELD32(0x00010000)
 210 #define CSR8_UART2_TX_BUFF_ERROR        FIELD32(0x00020000)
 211 #define CSR8_UART2_RX_BUFF_ERROR        FIELD32(0x00040000)
 212 #define CSR8_TIMER_CSR3_EXPIRE          FIELD32(0x00080000)
 213
 214 /*
 215  * CSR9: Maximum frame length register.
 216  * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
 217  */
 218 #define CSR9                            0x0024
 219 #define CSR9_MAX_FRAME_UNIT             FIELD32(0x00000f80)
 220
 221 /*
 222  * SECCSR0: WEP control register.
 223  * KICK_DECRYPT: Kick decryption engine, self-clear.
 224  * ONE_SHOT: 0: ring mode, 1: One shot only mode.
 225  * DESC_ADDRESS: Descriptor physical address of frame.
 226  */
 227 #define SECCSR0                         0x0028
 228 #define SECCSR0_KICK_DECRYPT            FIELD32(0x00000001)
 229 #define SECCSR0_ONE_SHOT                FIELD32(0x00000002)
 230 #define SECCSR0_DESC_ADDRESS            FIELD32(0xfffffffc)
 231
 232 /*
 233  * CSR11: Back-off control register.
 234  * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
 235  * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
 236  * SLOT_TIME: Slot time, default is 20us for 802.11b
 237  * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
 238  * LONG_RETRY: Long retry count.
 239  * SHORT_RETRY: Short retry count.
 240  */
 241 #define CSR11                           0x002c
 242 #define CSR11_CWMIN                     FIELD32(0x0000000f)
 243 #define CSR11_CWMAX                     FIELD32(0x000000f0)
 244 #define CSR11_SLOT_TIME                 FIELD32(0x00001f00)
 245 #define CSR11_CW_SELECT                 FIELD32(0x00002000)
 246 #define CSR11_LONG_RETRY                FIELD32(0x00ff0000)
 247 #define CSR11_SHORT_RETRY               FIELD32(0xff000000)
 248
 249 /*
 250  * CSR12: Synchronization configuration register 0.
 251  * All units in 1/16 TU.
 252  * BEACON_INTERVAL: Beacon interval, default is 100 TU.
 253  * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
 254  */
 255 #define CSR12                           0x0030
 256 #define CSR12_BEACON_INTERVAL           FIELD32(0x0000ffff)
 257 #define CSR12_CFP_MAX_DURATION          FIELD32(0xffff0000)
 258
 259 /*
 260  * CSR13: Synchronization configuration register 1.
 261  * All units in 1/16 TU.
 262  * ATIMW_DURATION: Atim window duration.
 263  * CFP_PERIOD: Cfp period, default is 0 TU.
 264  */
 265 #define CSR13                           0x0034
 266 #define CSR13_ATIMW_DURATION            FIELD32(0x0000ffff)
 267 #define CSR13_CFP_PERIOD                FIELD32(0x00ff0000)
 268
 269 /*
 270  * CSR14: Synchronization control register.
 271  * TSF_COUNT: Enable tsf auto counting.
 272  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 273  * TBCN: Enable tbcn with reload value.
 274  * TCFP: Enable tcfp & cfp / cp switching.
 275  * TATIMW: Enable tatimw & atim window switching.
 276  * BEACON_GEN: Enable beacon generator.
 277  * CFP_COUNT_PRELOAD: Cfp count preload value.
 278  * TBCM_PRELOAD: Tbcn preload value in units of 64us.
 279  */
 280 #define CSR14                           0x0038
 281 #define CSR14_TSF_COUNT                 FIELD32(0x00000001)
 282 #define CSR14_TSF_SYNC                  FIELD32(0x00000006)
 283 #define CSR14_TBCN                      FIELD32(0x00000008)
 284 #define CSR14_TCFP                      FIELD32(0x00000010)
 285 #define CSR14_TATIMW                    FIELD32(0x00000020)
 286 #define CSR14_BEACON_GEN                FIELD32(0x00000040)
 287 #define CSR14_CFP_COUNT_PRELOAD         FIELD32(0x0000ff00)
 288 #define CSR14_TBCM_PRELOAD              FIELD32(0xffff0000)
 289
 290 /*
 291  * CSR15: Synchronization status register.
 292  * CFP: ASIC is in contention-free period.
 293  * ATIMW: ASIC is in ATIM window.
 294  * BEACON_SENT: Beacon is send.
 295  */
 296 #define CSR15                           0x003c
 297 #define CSR15_CFP                       FIELD32(0x00000001)
 298 #define CSR15_ATIMW                     FIELD32(0x00000002)
 299 #define CSR15_BEACON_SENT               FIELD32(0x00000004)
 300
 301 /*
 302  * CSR16: TSF timer register 0.
 303  */
 304 #define CSR16                           0x0040
 305 #define CSR16_LOW_TSFTIMER              FIELD32(0xffffffff)
 306
 307 /*
 308  * CSR17: TSF timer register 1.
 309  */
 310 #define CSR17                           0x0044
 311 #define CSR17_HIGH_TSFTIMER             FIELD32(0xffffffff)
 312
 313 /*
 314  * CSR18: IFS timer register 0.
 315  * SIFS: Sifs, default is 10 us.
 316  * PIFS: Pifs, default is 30 us.
 317  */
 318 #define CSR18                           0x0048
 319 #define CSR18_SIFS                      FIELD32(0x000001ff)
 320 #define CSR18_PIFS                      FIELD32(0x001f0000)
 321
 322 /*
 323  * CSR19: IFS timer register 1.
 324  * DIFS: Difs, default is 50 us.
 325  * EIFS: Eifs, default is 364 us.
 326  */
 327 #define CSR19                           0x004c
 328 #define CSR19_DIFS                      FIELD32(0x0000ffff)
 329 #define CSR19_EIFS                      FIELD32(0xffff0000)
 330
 331 /*
 332  * CSR20: Wakeup timer register.
 333  * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
 334  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 335  * AUTOWAKE: Enable auto wakeup / sleep mechanism.
 336  */
 337 #define CSR20                           0x0050
 338 #define CSR20_DELAY_AFTER_TBCN          FIELD32(0x0000ffff)
 339 #define CSR20_TBCN_BEFORE_WAKEUP        FIELD32(0x00ff0000)
 340 #define CSR20_AUTOWAKE                  FIELD32(0x01000000)
 341
 342 /*
 343  * CSR21: EEPROM control register.
 344  * RELOAD: Write 1 to reload eeprom content.
 345  * TYPE_93C46: 1: 93c46, 0:93c66.
 346  */
 347 #define CSR21                           0x0054
 348 #define CSR21_RELOAD                    FIELD32(0x00000001)
 349 #define CSR21_EEPROM_DATA_CLOCK         FIELD32(0x00000002)
 350 #define CSR21_EEPROM_CHIP_SELECT        FIELD32(0x00000004)
 351 #define CSR21_EEPROM_DATA_IN            FIELD32(0x00000008)
 352 #define CSR21_EEPROM_DATA_OUT           FIELD32(0x00000010)
 353 #define CSR21_TYPE_93C46                FIELD32(0x00000020)
 354
 355 /*
 356  * CSR22: CFP control register.
 357  * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
 358  * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
 359  */
 360 #define CSR22                           0x0058
 361 #define CSR22_CFP_DURATION_REMAIN       FIELD32(0x0000ffff)
 362 #define CSR22_RELOAD_CFP_DURATION       FIELD32(0x00010000)
 363
 364 /*
 365  * Transmit related CSRs.
 366  * Some values are set in TU, whereas 1 TU == 1024 us.
 367  */
 368
 369 /*
 370  * TXCSR0: TX Control Register.
 371  * KICK_TX: Kick tx ring.
 372  * KICK_ATIM: Kick atim ring.
 373  * KICK_PRIO: Kick priority ring.
 374  * ABORT: Abort all transmit related ring operation.
 375  */
 376 #define TXCSR0                          0x0060
 377 #define TXCSR0_KICK_TX                  FIELD32(0x00000001)
 378 #define TXCSR0_KICK_ATIM                FIELD32(0x00000002)
 379 #define TXCSR0_KICK_PRIO                FIELD32(0x00000004)
 380 #define TXCSR0_ABORT                    FIELD32(0x00000008)
 381
 382 /*
 383  * TXCSR1: TX Configuration Register.
 384  * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
 385  * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
 386  * TSF_OFFSET: Insert tsf offset.
 387  * AUTORESPONDER: Enable auto responder which include ack & cts.
 388  */
 389 #define TXCSR1                          0x0064
 390 #define TXCSR1_ACK_TIMEOUT              FIELD32(0x000001ff)
 391 #define TXCSR1_ACK_CONSUME_TIME         FIELD32(0x0003fe00)
 392 #define TXCSR1_TSF_OFFSET               FIELD32(0x00fc0000)
 393 #define TXCSR1_AUTORESPONDER            FIELD32(0x01000000)
 394
 395 /*
 396  * TXCSR2: Tx descriptor configuration register.
 397  * TXD_SIZE: Tx descriptor size, default is 48.
 398  * NUM_TXD: Number of tx entries in ring.
 399  * NUM_ATIM: Number of atim entries in ring.
 400  * NUM_PRIO: Number of priority entries in ring.
 401  */
 402 #define TXCSR2                          0x0068
 403 #define TXCSR2_TXD_SIZE                 FIELD32(0x000000ff)
 404 #define TXCSR2_NUM_TXD                  FIELD32(0x0000ff00)
 405 #define TXCSR2_NUM_ATIM                 FIELD32(0x00ff0000)
 406 #define TXCSR2_NUM_PRIO                 FIELD32(0xff000000)
 407
 408 /*
 409  * TXCSR3: TX Ring Base address register.
 410  */
 411 #define TXCSR3                          0x006c
 412 #define TXCSR3_TX_RING_REGISTER         FIELD32(0xffffffff)
 413
 414 /*
 415  * TXCSR4: TX Atim Ring Base address register.
 416  */
 417 #define TXCSR4                          0x0070
 418 #define TXCSR4_ATIM_RING_REGISTER       FIELD32(0xffffffff)
 419
 420 /*
 421  * TXCSR5: TX Prio Ring Base address register.
 422  */
 423 #define TXCSR5                          0x0074
 424 #define TXCSR5_PRIO_RING_REGISTER       FIELD32(0xffffffff)
 425
 426 /*
 427  * TXCSR6: Beacon Base address register.
 428  */
 429 #define TXCSR6                          0x0078
 430 #define TXCSR6_BEACON_RING_REGISTER     FIELD32(0xffffffff)
 431
 432 /*
 433  * TXCSR7: Auto responder control register.
 434  * AR_POWERMANAGEMENT: Auto responder power management bit.
 435  */
 436 #define TXCSR7                          0x007c
 437 #define TXCSR7_AR_POWERMANAGEMENT       FIELD32(0x00000001)
 438
 439 /*
 440  * TXCSR8: CCK Tx BBP register.
 441  * CCK_SIGNAL: BBP rate field address for CCK.
 442  * CCK_SERVICE: BBP service field address for CCK.
 443  * CCK_LENGTH_LOW: BBP length low byte address for CCK.
 444  * CCK_LENGTH_HIGH: BBP length high byte address for CCK.
 445  */
 446 #define TXCSR8                          0x0098
 447 #define TXCSR8_CCK_SIGNAL               FIELD32(0x000000ff)
 448 #define TXCSR8_CCK_SERVICE              FIELD32(0x0000ff00)
 449 #define TXCSR8_CCK_LENGTH_LOW           FIELD32(0x00ff0000)
 450 #define TXCSR8_CCK_LENGTH_HIGH          FIELD32(0xff000000)
 451
 452 /*
 453  * TXCSR9: OFDM TX BBP registers
 454  * OFDM_SIGNAL: BBP rate field address for OFDM.
 455  * OFDM_SERVICE: BBP service field address for OFDM.
 456  * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
 457  * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
 458  */
 459 #define TXCSR9                          0x0094
 460 #define TXCSR9_OFDM_RATE                FIELD32(0x000000ff)
 461 #define TXCSR9_OFDM_SERVICE             FIELD32(0x0000ff00)
 462 #define TXCSR9_OFDM_LENGTH_LOW          FIELD32(0x00ff0000)
 463 #define TXCSR9_OFDM_LENGTH_HIGH         FIELD32(0xff000000)
 464
 465 /*
 466  * Receive related CSRs.
 467  * Some values are set in TU, whereas 1 TU == 1024 us.
 468  */
 469
 470 /*
 471  * RXCSR0: RX Control Register.
 472  * DISABLE_RX: Disable rx engine.
 473  * DROP_CRC: Drop crc error.
 474  * DROP_PHYSICAL: Drop physical error.
 475  * DROP_CONTROL: Drop control frame.
 476  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 477  * DROP_TODS: Drop frame tods bit is true.
 478  * DROP_VERSION_ERROR: Drop version error frame.
 479  * PASS_CRC: Pass all packets with crc attached.
 480  * PASS_CRC: Pass all packets with crc attached.
 481  * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
 482  * DROP_MCAST: Drop multicast frames.
 483  * DROP_BCAST: Drop broadcast frames.
 484  * ENABLE_QOS: Accept QOS data frame and parse QOS field.
 485  */
 486 #define RXCSR0                          0x0080
 487 #define RXCSR0_DISABLE_RX               FIELD32(0x00000001)
 488 #define RXCSR0_DROP_CRC                 FIELD32(0x00000002)
 489 #define RXCSR0_DROP_PHYSICAL            FIELD32(0x00000004)
 490 #define RXCSR0_DROP_CONTROL             FIELD32(0x00000008)
 491 #define RXCSR0_DROP_NOT_TO_ME           FIELD32(0x00000010)
 492 #define RXCSR0_DROP_TODS                FIELD32(0x00000020)
 493 #define RXCSR0_DROP_VERSION_ERROR       FIELD32(0x00000040)
 494 #define RXCSR0_PASS_CRC                 FIELD32(0x00000080)
 495 #define RXCSR0_PASS_PLCP                FIELD32(0x00000100)
 496 #define RXCSR0_DROP_MCAST               FIELD32(0x00000200)
 497 #define RXCSR0_DROP_BCAST               FIELD32(0x00000400)
 498 #define RXCSR0_ENABLE_QOS               FIELD32(0x00000800)
 499
 500 /*
 501  * RXCSR1: RX descriptor configuration register.
 502  * RXD_SIZE: Rx descriptor size, default is 32b.
 503  * NUM_RXD: Number of rx entries in ring.
 504  */
 505 #define RXCSR1                          0x0084
 506 #define RXCSR1_RXD_SIZE                 FIELD32(0x000000ff)
 507 #define RXCSR1_NUM_RXD                  FIELD32(0x0000ff00)
 508
 509 /*
 510  * RXCSR2: RX Ring base address register.
 511  */
 512 #define RXCSR2                          0x0088
 513 #define RXCSR2_RX_RING_REGISTER         FIELD32(0xffffffff)
 514
 515 /*
 516  * RXCSR3: BBP ID register for Rx operation.
 517  * BBP_ID#: BBP register # id.
 518  * BBP_ID#_VALID: BBP register # id is valid or not.
 519  */
 520 #define RXCSR3                          0x0090
 521 #define RXCSR3_BBP_ID0                  FIELD32(0x0000007f)
 522 #define RXCSR3_BBP_ID0_VALID            FIELD32(0x00000080)
 523 #define RXCSR3_BBP_ID1                  FIELD32(0x00007f00)
 524 #define RXCSR3_BBP_ID1_VALID            FIELD32(0x00008000)
 525 #define RXCSR3_BBP_ID2                  FIELD32(0x007f0000)
 526 #define RXCSR3_BBP_ID2_VALID            FIELD32(0x00800000)
 527 #define RXCSR3_BBP_ID3                  FIELD32(0x7f000000)
 528 #define RXCSR3_BBP_ID3_VALID            FIELD32(0x80000000)
 529
 530 /*
 531  * ARCSR1: Auto Responder PLCP config register 1.
 532  * AR_BBP_DATA#: Auto responder BBP register # data.
 533  * AR_BBP_ID#: Auto responder BBP register # Id.
 534  */
 535 #define ARCSR1                          0x009c
 536 #define ARCSR1_AR_BBP_DATA2             FIELD32(0x000000ff)
 537 #define ARCSR1_AR_BBP_ID2               FIELD32(0x0000ff00)
 538 #define ARCSR1_AR_BBP_DATA3             FIELD32(0x00ff0000)
 539 #define ARCSR1_AR_BBP_ID3               FIELD32(0xff000000)
 540
 541 /*
 542  * Miscellaneous Registers.
 543  * Some values are set in TU, whereas 1 TU == 1024 us.
 544
 545  */
 546
 547 /*
 548  * PCICSR: PCI control register.
 549  * BIG_ENDIAN: 1: big endian, 0: little endian.
 550  * RX_TRESHOLD: Rx threshold in dw to start pci access
 551  * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
 552  * TX_TRESHOLD: Tx threshold in dw to start pci access
 553  * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
 554  * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
 555  * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
 556  * READ_MULTIPLE: Enable memory read multiple.
 557  * WRITE_INVALID: Enable memory write & invalid.
 558  */
 559 #define PCICSR                          0x008c
 560 #define PCICSR_BIG_ENDIAN               FIELD32(0x00000001)
 561 #define PCICSR_RX_TRESHOLD              FIELD32(0x00000006)
 562 #define PCICSR_TX_TRESHOLD              FIELD32(0x00000018)
 563 #define PCICSR_BURST_LENTH              FIELD32(0x00000060)
 564 #define PCICSR_ENABLE_CLK               FIELD32(0x00000080)
 565 #define PCICSR_READ_MULTIPLE            FIELD32(0x00000100)
 566 #define PCICSR_WRITE_INVALID            FIELD32(0x00000200)
 567
 568 /*
 569  * CNT0: FCS error count.
 570  * FCS_ERROR: FCS error count, cleared when read.
 571  */
 572 #define CNT0                            0x00a0
 573 #define CNT0_FCS_ERROR                  FIELD32(0x0000ffff)
 574
 575 /*
 576  * Statistic Register.
 577  * CNT1: PLCP error count.
 578  * CNT2: Long error count.
 579  */
 580 #define TIMECSR2                        0x00a8
 581 #define CNT1                            0x00ac
 582 #define CNT2                            0x00b0
 583 #define TIMECSR3                        0x00b4
 584
 585 /*
 586  * CNT3: CCA false alarm count.
 587  */
 588 #define CNT3                            0x00b8
 589 #define CNT3_FALSE_CCA                  FIELD32(0x0000ffff)
 590
 591 /*
 592  * Statistic Register.
 593  * CNT4: Rx FIFO overflow count.
 594  * CNT5: Tx FIFO underrun count.
 595  */
 596 #define CNT4                            0x00bc
 597 #define CNT5                            0x00c0
 598
 599 /*
 600  * Baseband Control Register.
 601  */
 602
 603 /*
 604  * PWRCSR0: Power mode configuration register.
 605  */
 606 #define PWRCSR0                         0x00c4
 607
 608 /*
 609  * Power state transition time registers.
 610  */
 611 #define PSCSR0                          0x00c8
 612 #define PSCSR1                          0x00cc
 613 #define PSCSR2                          0x00d0
 614 #define PSCSR3                          0x00d4
 615
 616 /*
 617  * PWRCSR1: Manual power control / status register.
 618  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 619  * SET_STATE: Set state. Write 1 to trigger, self cleared.
 620  * BBP_DESIRE_STATE: BBP desired state.
 621  * RF_DESIRE_STATE: RF desired state.
 622  * BBP_CURR_STATE: BBP current state.
 623  * RF_CURR_STATE: RF current state.
 624  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 625  */
 626 #define PWRCSR1                         0x00d8
 627 #define PWRCSR1_SET_STATE               FIELD32(0x00000001)
 628 #define PWRCSR1_BBP_DESIRE_STATE        FIELD32(0x00000006)
 629 #define PWRCSR1_RF_DESIRE_STATE         FIELD32(0x00000018)
 630 #define PWRCSR1_BBP_CURR_STATE          FIELD32(0x00000060)
 631 #define PWRCSR1_RF_CURR_STATE           FIELD32(0x00000180)
 632 #define PWRCSR1_PUT_TO_SLEEP            FIELD32(0x00000200)
 633
 634 /*
 635  * TIMECSR: Timer control register.
 636  * US_COUNT: 1 us timer count in units of clock cycles.
 637  * US_64_COUNT: 64 us timer count in units of 1 us timer.
 638  * BEACON_EXPECT: Beacon expect window.
 639  */
 640 #define TIMECSR                         0x00dc
 641 #define TIMECSR_US_COUNT                FIELD32(0x000000ff)
 642 #define TIMECSR_US_64_COUNT             FIELD32(0x0000ff00)
 643 #define TIMECSR_BEACON_EXPECT           FIELD32(0x00070000)
 644
 645 /*
 646  * MACCSR0: MAC configuration register 0.
 647  */
 648 #define MACCSR0                         0x00e0
 649
 650 /*
 651  * MACCSR1: MAC configuration register 1.
 652  * KICK_RX: Kick one-shot rx in one-shot rx mode.
 653  * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
 654  * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
 655  * AUTO_TXBBP: Auto tx logic access bbp control register.
 656  * AUTO_RXBBP: Auto rx logic access bbp control register.
 657  * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
 658  * INTERSIL_IF: Intersil if calibration pin.
 659  */
 660 #define MACCSR1                         0x00e4
 661 #define MACCSR1_KICK_RX                 FIELD32(0x00000001)
 662 #define MACCSR1_ONESHOT_RXMODE          FIELD32(0x00000002)
 663 #define MACCSR1_BBPRX_RESET_MODE        FIELD32(0x00000004)
 664 #define MACCSR1_AUTO_TXBBP              FIELD32(0x00000008)
 665 #define MACCSR1_AUTO_RXBBP              FIELD32(0x00000010)
 666 #define MACCSR1_LOOPBACK                FIELD32(0x00000060)
 667 #define MACCSR1_INTERSIL_IF             FIELD32(0x00000080)
 668
 669 /*
 670  * RALINKCSR: Ralink Rx auto-reset BBCR.
 671  * AR_BBP_DATA#: Auto reset BBP register # data.
 672  * AR_BBP_ID#: Auto reset BBP register # id.
 673  */
 674 #define RALINKCSR                       0x00e8
 675 #define RALINKCSR_AR_BBP_DATA0          FIELD32(0x000000ff)
 676 #define RALINKCSR_AR_BBP_ID0            FIELD32(0x00007f00)
 677 #define RALINKCSR_AR_BBP_VALID0         FIELD32(0x00008000)
 678 #define RALINKCSR_AR_BBP_DATA1          FIELD32(0x00ff0000)
 679 #define RALINKCSR_AR_BBP_ID1            FIELD32(0x7f000000)
 680 #define RALINKCSR_AR_BBP_VALID1         FIELD32(0x80000000)
 681
 682 /*
 683  * BCNCSR: Beacon interval control register.
 684  * CHANGE: Write one to change beacon interval.
 685  * DELTATIME: The delta time value.
 686  * NUM_BEACON: Number of beacon according to mode.
 687  * MODE: Please refer to asic specs.
 688  * PLUS: Plus or minus delta time value.
 689  */
 690 #define BCNCSR                          0x00ec
 691 #define BCNCSR_CHANGE                   FIELD32(0x00000001)
 692 #define BCNCSR_DELTATIME                FIELD32(0x0000001e)
 693 #define BCNCSR_NUM_BEACON               FIELD32(0x00001fe0)
 694 #define BCNCSR_MODE                     FIELD32(0x00006000)
 695 #define BCNCSR_PLUS                     FIELD32(0x00008000)
 696
 697 /*
 698  * BBP / RF / IF Control Register.
 699  */
 700
 701 /*
 702  * BBPCSR: BBP serial control register.
 703  * VALUE: Register value to program into BBP.
 704  * REGNUM: Selected BBP register.
 705  * BUSY: 1: asic is busy execute BBP programming.
 706  * WRITE_CONTROL: 1: write BBP, 0: read BBP.
 707  */
 708 #define BBPCSR                          0x00f0
 709 #define BBPCSR_VALUE                    FIELD32(0x000000ff)
 710 #define BBPCSR_REGNUM                   FIELD32(0x00007f00)
 711 #define BBPCSR_BUSY                     FIELD32(0x00008000)
 712 #define BBPCSR_WRITE_CONTROL            FIELD32(0x00010000)
 713
 714 /*
 715  * RFCSR: RF serial control register.
 716  * VALUE: Register value + id to program into rf/if.
 717  * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 718  * IF_SELECT: Chip to program: 0: rf, 1: if.
 719  * PLL_LD: Rf pll_ld status.
 720  * BUSY: 1: asic is busy execute rf programming.
 721  */
 722 #define RFCSR                           0x00f4
 723 #define RFCSR_VALUE                     FIELD32(0x00ffffff)
 724 #define RFCSR_NUMBER_OF_BITS            FIELD32(0x1f000000)
 725 #define RFCSR_IF_SELECT                 FIELD32(0x20000000)
 726 #define RFCSR_PLL_LD                    FIELD32(0x40000000)
 727 #define RFCSR_BUSY                      FIELD32(0x80000000)
 728
 729 /*
 730  * LEDCSR: LED control register.
 731  * ON_PERIOD: On period, default 70ms.
 732  * OFF_PERIOD: Off period, default 30ms.
 733  * LINK: 0: linkoff, 1: linkup.
 734  * ACTIVITY: 0: idle, 1: active.
 735  * LINK_POLARITY: 0: active low, 1: active high.
 736  * ACTIVITY_POLARITY: 0: active low, 1: active high.
 737  * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
 738  */
 739 #define LEDCSR                          0x00f8
 740 #define LEDCSR_ON_PERIOD                FIELD32(0x000000ff)
 741 #define LEDCSR_OFF_PERIOD               FIELD32(0x0000ff00)
 742 #define LEDCSR_LINK                     FIELD32(0x00010000)
 743 #define LEDCSR_ACTIVITY                 FIELD32(0x00020000)
 744 #define LEDCSR_LINK_POLARITY            FIELD32(0x00040000)
 745 #define LEDCSR_ACTIVITY_POLARITY        FIELD32(0x00080000)
 746 #define LEDCSR_LED_DEFAULT              FIELD32(0x00100000)
 747
 748 /*
 749  * AES control register.
 750  */
 751 #define SECCSR3                         0x00fc
 752
 753 /*
 754  * ASIC pointer information.
 755  * RXPTR: Current RX ring address.
 756  * TXPTR: Current Tx ring address.
 757  * PRIPTR: Current Priority ring address.
 758  * ATIMPTR: Current ATIM ring address.
 759  */
 760 #define RXPTR                           0x0100
 761 #define TXPTR                           0x0104
 762 #define PRIPTR                          0x0108
 763 #define ATIMPTR                         0x010c
 764
 765 /*
 766  * TXACKCSR0: TX ACK timeout.
 767  */
 768 #define TXACKCSR0                       0x0110
 769
 770 /*
 771  * ACK timeout count registers.
 772  * ACKCNT0: TX ACK timeout count.
 773  * ACKCNT1: RX ACK timeout count.
 774  */
 775 #define ACKCNT0                         0x0114
 776 #define ACKCNT1                         0x0118
 777
 778 /*
 779  * GPIO and others.
 780  */
 781
 782 /*
 783  * GPIOCSR: GPIO control register.
 784  */
 785 #define GPIOCSR                         0x0120
 786 #define GPIOCSR_BIT0                    FIELD32(0x00000001)
 787 #define GPIOCSR_BIT1                    FIELD32(0x00000002)
 788 #define GPIOCSR_BIT2                    FIELD32(0x00000004)
 789 #define GPIOCSR_BIT3                    FIELD32(0x00000008)
 790 #define GPIOCSR_BIT4                    FIELD32(0x00000010)
 791 #define GPIOCSR_BIT5                    FIELD32(0x00000020)
 792 #define GPIOCSR_BIT6                    FIELD32(0x00000040)
 793 #define GPIOCSR_BIT7                    FIELD32(0x00000080)
 794 #define GPIOCSR_DIR0                    FIELD32(0x00000100)
 795 #define GPIOCSR_DIR1                    FIELD32(0x00000200)
 796 #define GPIOCSR_DIR2                    FIELD32(0x00000400)
 797 #define GPIOCSR_DIR3                    FIELD32(0x00000800)
 798 #define GPIOCSR_DIR4                    FIELD32(0x00001000)
 799 #define GPIOCSR_DIR5                    FIELD32(0x00002000)
 800 #define GPIOCSR_DIR6                    FIELD32(0x00004000)
 801 #define GPIOCSR_DIR7                    FIELD32(0x00008000)
 802
 803 /*
 804  * FIFO pointer registers.
 805  * FIFOCSR0: TX FIFO pointer.
 806  * FIFOCSR1: RX FIFO pointer.
 807  */
 808 #define FIFOCSR0                        0x0128
 809 #define FIFOCSR1                        0x012c
 810
 811 /*
 812  * BCNCSR1: Tx BEACON offset time control register.
 813  * PRELOAD: Beacon timer offset in units of usec.
 814  * BEACON_CWMIN: 2^CwMin.
 815  */
 816 #define BCNCSR1                         0x0130
 817 #define BCNCSR1_PRELOAD                 FIELD32(0x0000ffff)
 818 #define BCNCSR1_BEACON_CWMIN            FIELD32(0x000f0000)
 819
 820 /*
 821  * MACCSR2: TX_PE to RX_PE turn-around time control register
 822  * DELAY: RX_PE low width, in units of pci clock cycle.
 823  */
 824 #define MACCSR2                         0x0134
 825 #define MACCSR2_DELAY                   FIELD32(0x000000ff)
 826
 827 /*
 828  * TESTCSR: TEST mode selection register.
 829  */
 830 #define TESTCSR                         0x0138
 831
 832 /*
 833  * ARCSR2: 1 Mbps ACK/CTS PLCP.
 834  */
 835 #define ARCSR2                          0x013c
 836 #define ARCSR2_SIGNAL                   FIELD32(0x000000ff)
 837 #define ARCSR2_SERVICE                  FIELD32(0x0000ff00)
 838 #define ARCSR2_LENGTH                   FIELD32(0xffff0000)
 839
 840 /*
 841  * ARCSR3: 2 Mbps ACK/CTS PLCP.
 842  */
 843 #define ARCSR3                          0x0140
 844 #define ARCSR3_SIGNAL                   FIELD32(0x000000ff)
 845 #define ARCSR3_SERVICE                  FIELD32(0x0000ff00)
 846 #define ARCSR3_LENGTH                   FIELD32(0xffff0000)
 847
 848 /*
 849  * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
 850  */
 851 #define ARCSR4                          0x0144
 852 #define ARCSR4_SIGNAL                   FIELD32(0x000000ff)
 853 #define ARCSR4_SERVICE                  FIELD32(0x0000ff00)
 854 #define ARCSR4_LENGTH                   FIELD32(0xffff0000)
 855
 856 /*
 857  * ARCSR5: 11 Mbps ACK/CTS PLCP.
 858  */
 859 #define ARCSR5                          0x0148
 860 #define ARCSR5_SIGNAL                   FIELD32(0x000000ff)
 861 #define ARCSR5_SERVICE                  FIELD32(0x0000ff00)
 862 #define ARCSR5_LENGTH                   FIELD32(0xffff0000)
 863
 864 /*
 865  * ACK/CTS payload consumed time registers.
 866  * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
 867  * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
 868  * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
 869  */
 870 #define ARTCSR0                         0x014c
 871 #define ARTCSR1                         0x0150
 872 #define ARTCSR2                         0x0154
 873
 874 /*
 875  * SECCSR1_RT2509: WEP control register.
 876  * KICK_ENCRYPT: Kick encryption engine, self-clear.
 877  * ONE_SHOT: 0: ring mode, 1: One shot only mode.
 878  * DESC_ADDRESS: Descriptor physical address of frame.
 879  */
 880 #define SECCSR1                         0x0158
 881 #define SECCSR1_KICK_ENCRYPT            FIELD32(0x00000001)
 882 #define SECCSR1_ONE_SHOT                FIELD32(0x00000002)
 883 #define SECCSR1_DESC_ADDRESS            FIELD32(0xfffffffc)
 884
 885 /*
 886  * BBPCSR1: BBP TX configuration.
 887  */
 888 #define BBPCSR1                         0x015c
 889 #define BBPCSR1_CCK                     FIELD32(0x00000003)
 890 #define BBPCSR1_CCK_FLIP                FIELD32(0x00000004)
 891 #define BBPCSR1_OFDM                    FIELD32(0x00030000)
 892 #define BBPCSR1_OFDM_FLIP               FIELD32(0x00040000)
 893
 894 /*
 895  * Dual band configuration registers.
 896  * DBANDCSR0: Dual band configuration register 0.
 897  * DBANDCSR1: Dual band configuration register 1.
 898  */
 899 #define DBANDCSR0                       0x0160
 900 #define DBANDCSR1                       0x0164
 901
 902 /*
 903  * BBPPCSR: BBP Pin control register.
 904  */
 905 #define BBPPCSR                         0x0168
 906
 907 /*
 908  * MAC special debug mode selection registers.
 909  * DBGSEL0: MAC special debug mode selection register 0.
 910  * DBGSEL1: MAC special debug mode selection register 1.
 911  */
 912 #define DBGSEL0                         0x016c
 913 #define DBGSEL1                         0x0170
 914
 915 /*
 916  * BISTCSR: BBP BIST register.
 917  */
 918 #define BISTCSR                         0x0174
 919
 920 /*
 921  * Multicast filter registers.
 922  * MCAST0: Multicast filter register 0.
 923  * MCAST1: Multicast filter register 1.
 924  */
 925 #define MCAST0                          0x0178
 926 #define MCAST1                          0x017c
 927
 928 /*
 929  * UART registers.
 930  * UARTCSR0: UART1 TX register.
 931  * UARTCSR1: UART1 RX register.
 932  * UARTCSR3: UART1 frame control register.
 933  * UARTCSR4: UART1 buffer control register.
 934  * UART2CSR0: UART2 TX register.
 935  * UART2CSR1: UART2 RX register.
 936  * UART2CSR3: UART2 frame control register.
 937  * UART2CSR4: UART2 buffer control register.
 938  */
 939 #define UARTCSR0                        0x0180
 940 #define UARTCSR1                        0x0184
 941 #define UARTCSR3                        0x0188
 942 #define UARTCSR4                        0x018c
 943 #define UART2CSR0                       0x0190
 944 #define UART2CSR1                       0x0194
 945 #define UART2CSR3                       0x0198
 946 #define UART2CSR4                       0x019c
 947
 948 /*
 949  * RF registers
 950  */
 951 #define RF1_TUNER                       FIELD32(0x00020000)
 952 #define RF3_TUNER                       FIELD32(0x00000100)
 953 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 954
 955 /*
 956  * EEPROM content.
 957  * The wordsize of the EEPROM is 16 bits.
 958  */
 959
 960 /*
 961  * HW MAC address.
 962  */
 963 #define EEPROM_MAC_ADDR_0               0x0002
 964 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 965 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 966 #define EEPROM_MAC_ADDR1                0x0003
 967 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 968 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 969 #define EEPROM_MAC_ADDR_2               0x0004
 970 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 971 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 972
 973 /*
 974  * EEPROM antenna.
 975  * ANTENNA_NUM: Number of antenna's.
 976  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 977  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 978  * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
 979  * DYN_TXAGC: Dynamic TX AGC control.
 980  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 981  * RF_TYPE: Rf_type of this adapter.
 982  */
 983 #define EEPROM_ANTENNA                  0x10
 984 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 985 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 986 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 987 #define EEPROM_ANTENNA_LED_MODE         FIELD16(0x01c0)
 988 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 989 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 990 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 991
 992 /*
 993  * EEPROM NIC config.
 994  * CARDBUS_ACCEL: 0: enable, 1: disable.
 995  * DYN_BBP_TUNE: 0: enable, 1: disable.
 996  * CCK_TX_POWER: CCK TX power compensation.
 997  */
 998 #define EEPROM_NIC                      0x11
 999 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0001)
1000 #define EEPROM_NIC_DYN_BBP_TUNE         FIELD16(0x0002)
1001 #define EEPROM_NIC_CCK_TX_POWER         FIELD16(0x000c)
1002
1003 /*
1004  * EEPROM geography.
1005  * GEO: Default geography setting for device.
1006  */
1007 #define EEPROM_GEOGRAPHY                0x12
1008 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0x0f00)
1009
1010 /*
1011  * EEPROM BBP.
1012  */
1013 #define EEPROM_BBP_START                0x13
1014 #define EEPROM_BBP_SIZE                 16
1015 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
1016 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
1017
1018 /*
1019  * EEPROM TXPOWER
1020  */
1021 #define EEPROM_TXPOWER_START            0x23
1022 #define EEPROM_TXPOWER_SIZE             7
1023 #define EEPROM_TXPOWER_1                FIELD16(0x00ff)
1024 #define EEPROM_TXPOWER_2                FIELD16(0xff00)
1025
1026 /*
1027  * RSSI <-> dBm offset calibration
1028  */
1029 #define EEPROM_CALIBRATE_OFFSET         0x3e
1030 #define EEPROM_CALIBRATE_OFFSET_RSSI    FIELD16(0x00ff)
1031
1032 /*
1033  * BBP content.
1034  * The wordsize of the BBP is 8 bits.
1035  */
1036
1037 /*
1038  * BBP_R2: TX antenna control
1039  */
1040 #define BBP_R2_TX_ANTENNA               FIELD8(0x03)
1041 #define BBP_R2_TX_IQ_FLIP               FIELD8(0x04)
1042
1043 /*
1044  * BBP_R14: RX antenna control
1045  */
1046 #define BBP_R14_RX_ANTENNA              FIELD8(0x03)
1047 #define BBP_R14_RX_IQ_FLIP              FIELD8(0x04)
1048
1049 /*
1050  * BBP_R70
1051  */
1052 #define BBP_R70_JAPAN_FILTER            FIELD8(0x08)
1053
1054 /*
1055  * DMA descriptor defines.
1056  */
1057 #define TXD_DESC_SIZE                   ( 11 * sizeof(struct data_desc) )
1058 #define RXD_DESC_SIZE                   ( 11 * sizeof(struct data_desc) )
1059
1060 /*
1061  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
1062  */
1063
1064 /*
1065  * Word0
1066  */
1067 #define TXD_W0_OWNER_NIC                FIELD32(0x00000001)
1068 #define TXD_W0_VALID                    FIELD32(0x00000002)
1069 #define TXD_W0_RESULT                   FIELD32(0x0000001c)
1070 #define TXD_W0_RETRY_COUNT              FIELD32(0x000000e0)
1071 #define TXD_W0_MORE_FRAG                FIELD32(0x00000100)
1072 #define TXD_W0_ACK                      FIELD32(0x00000200)
1073 #define TXD_W0_TIMESTAMP                FIELD32(0x00000400)
1074 #define TXD_W0_OFDM                     FIELD32(0x00000800)
1075 #define TXD_W0_CIPHER_OWNER             FIELD32(0x00001000)
1076 #define TXD_W0_IFS                      FIELD32(0x00006000)
1077 #define TXD_W0_RETRY_MODE               FIELD32(0x00008000)
1078 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1079 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1080
1081 /*
1082  * Word1
1083  */
1084 #define TXD_W1_BUFFER_ADDRESS           FIELD32(0xffffffff)
1085
1086 /*
1087  * Word2
1088  */
1089 #define TXD_W2_IV_OFFSET                FIELD32(0x0000003f)
1090 #define TXD_W2_AIFS                     FIELD32(0x000000c0)
1091 #define TXD_W2_CWMIN                    FIELD32(0x00000f00)
1092 #define TXD_W2_CWMAX                    FIELD32(0x0000f000)
1093
1094 /*
1095  * Word3: PLCP information
1096  */
1097 #define TXD_W3_PLCP_SIGNAL              FIELD32(0x000000ff)
1098 #define TXD_W3_PLCP_SERVICE             FIELD32(0x0000ff00)
1099 #define TXD_W3_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
1100 #define TXD_W3_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
1101
1102 /*
1103  * Word4
1104  */
1105 #define TXD_W4_IV                       FIELD32(0xffffffff)
1106
1107 /*
1108  * Word5
1109  */
1110 #define TXD_W5_EIV                      FIELD32(0xffffffff)
1111
1112 /*
1113  * Word6-9: Key
1114  */
1115 #define TXD_W6_KEY                      FIELD32(0xffffffff)
1116 #define TXD_W7_KEY                      FIELD32(0xffffffff)
1117 #define TXD_W8_KEY                      FIELD32(0xffffffff)
1118 #define TXD_W9_KEY                      FIELD32(0xffffffff)
1119
1120 /*
1121  * Word10
1122  */
1123 #define TXD_W10_RTS                     FIELD32(0x00000001)
1124 #define TXD_W10_TX_RATE                 FIELD32(0x000000fe)
1125
1126 /*
1127  * RX descriptor format for RX Ring.
1128  */
1129
1130 /*
1131  * Word0
1132  */
1133 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
1134 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000002)
1135 #define RXD_W0_MULTICAST                FIELD32(0x00000004)
1136 #define RXD_W0_BROADCAST                FIELD32(0x00000008)
1137 #define RXD_W0_MY_BSS                   FIELD32(0x00000010)
1138 #define RXD_W0_CRC                      FIELD32(0x00000020)
1139 #define RXD_W0_OFDM                     FIELD32(0x00000040)
1140 #define RXD_W0_PHYSICAL_ERROR           FIELD32(0x00000080)
1141 #define RXD_W0_CIPHER_OWNER             FIELD32(0x00000100)
1142 #define RXD_W0_ICV_ERROR                FIELD32(0x00000200)
1143 #define RXD_W0_IV_OFFSET                FIELD32(0x0000fc00)
1144 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1145 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1146
1147 /*
1148  * Word1
1149  */
1150 #define RXD_W1_BUFFER_ADDRESS           FIELD32(0xffffffff)
1151
1152 /*
1153  * Word2
1154  */
1155 #define RXD_W2_SIGNAL                   FIELD32(0x000000ff)
1156 #define RXD_W2_RSSI                     FIELD32(0x0000ff00)
1157 #define RXD_W2_TA                       FIELD32(0xffff0000)
1158
1159 /*
1160  * Word3
1161  */
1162 #define RXD_W3_TA                       FIELD32(0xffffffff)
1163
1164 /*
1165  * Word4
1166  */
1167 #define RXD_W4_IV                       FIELD32(0xffffffff)
1168
1169 /*
1170  * Word5
1171  */
1172 #define RXD_W5_EIV                      FIELD32(0xffffffff)
1173
1174 /*
1175  * Word6-9: Key
1176  */
1177 #define RXD_W6_KEY                      FIELD32(0xffffffff)
1178 #define RXD_W7_KEY                      FIELD32(0xffffffff)
1179 #define RXD_W8_KEY                      FIELD32(0xffffffff)
1180 #define RXD_W9_KEY                      FIELD32(0xffffffff)
1181
1182 /*
1183  * Word10
1184  */
1185 #define RXD_W10_DROP                    FIELD32(0x00000001)
1186
1187 /*
1188  * Macro's for converting txpower from EEPROM to dscape value
1189  * and from dscape value to register value.
1190  */
1191 #define MIN_TXPOWER     0
1192 #define MAX_TXPOWER     31
1193 #define DEFAULT_TXPOWER 24
1194
1195 #define TXPOWER_FROM_DEV(__txpower)             \
1196 ({                                              \
1197         ((__txpower) > MAX_TXPOWER) ?           \
1198                 DEFAULT_TXPOWER : (__txpower);  \
1199 })
1200
1201 #define TXPOWER_TO_DEV(__txpower)                       \
1202 ({                                                      \
1203         ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
1204         (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
1205         (__txpower));                                   \
1206 })
1207
1208 #endif /* RT2500PCI_H */