2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt61pci module.
24 Supported chipsets: RT2561, RT2561s, RT2661.
42 #define MAX_RX_NOISE -110
43 #define DEFAULT_RSSI_OFFSET 120
46 * Register layout information.
48 #define CSR_REG_BASE 0x3000
49 #define CSR_REG_SIZE 0x04b0
50 #define EEPROM_BASE 0x0000
51 #define EEPROM_SIZE 0x0100
52 #define BBP_SIZE 0x0080
59 * PCI Configuration Header
61 #define PCI_CONFIG_HEADER_VENDOR 0x0000
62 #define PCI_CONFIG_HEADER_DEVICE 0x0002
65 * HOST_CMD_CSR: For HOST to interrupt embedded processor
67 #define HOST_CMD_CSR 0x0008
68 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
69 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
73 * SELECT_BANK: Select 8051 program bank.
74 * RESET: Enable 8051 reset state.
75 * READY: Ready state for 8051.
77 #define MCU_CNTL_CSR 0x000c
78 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
79 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
80 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
85 #define SOFT_RESET_CSR 0x0010
88 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
90 #define MCU_INT_SOURCE_CSR 0x0014
91 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
92 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
93 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
94 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
95 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
96 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
97 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
98 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
99 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
100 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
103 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
105 #define MCU_INT_MASK_CSR 0x0018
106 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
107 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
108 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
109 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
110 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
111 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
112 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
113 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
114 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
115 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
120 #define PCI_USEC_CSR 0x001c
123 * Security key table memory.
124 * 16 entries 32-byte for shared key table
125 * 64 entries 32-byte for pairwise key table
126 * 64 entries 8-byte for pairwise ta key table
128 #define SHARED_KEY_TABLE_BASE 0x1000
129 #define PAIRWISE_KEY_TABLE_BASE 0x1200
130 #define PAIRWISE_TA_TABLE_BASE 0x1a00
132 struct hw_key_entry
{
136 } __attribute__ ((packed
));
138 struct hw_pairwise_ta_entry
{
141 } __attribute__ ((packed
));
144 * Other on-chip shared memory space.
146 #define HW_CIS_BASE 0x2000
147 #define HW_NULL_BASE 0x2b00
150 * Since NULL frame won't be that long (256 byte),
151 * We steal 16 tail bytes to save debugging settings.
153 #define HW_DEBUG_SETTING_BASE 0x2bf0
156 * On-chip BEACON frame space.
158 #define HW_BEACON_BASE0 0x2c00
159 #define HW_BEACON_BASE1 0x2d00
160 #define HW_BEACON_BASE2 0x2e00
161 #define HW_BEACON_BASE3 0x2f00
162 #define HW_BEACON_OFFSET 0x0100
165 * HOST-MCU shared memory.
169 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
171 #define H2M_MAILBOX_CSR 0x2100
172 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
173 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
174 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
175 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
178 * MCU_LEDCS: LED control for MCU Mailbox.
180 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
181 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
182 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
183 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
184 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
185 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
186 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
187 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
188 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
189 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
190 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
191 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
196 #define M2H_CMD_DONE_CSR 0x2104
199 * MCU_TXOP_ARRAY_BASE.
201 #define MCU_TXOP_ARRAY_BASE 0x2110
204 * MAC Control/Status Registers(CSR).
205 * Some values are set in TU, whereas 1 TU == 1024 us.
209 * MAC_CSR0: ASIC revision number.
211 #define MAC_CSR0 0x3000
214 * MAC_CSR1: System control register.
215 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
216 * BBP_RESET: Hardware reset BBP.
217 * HOST_READY: Host is ready after initialization, 1: ready.
219 #define MAC_CSR1 0x3004
220 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
221 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
222 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
225 * MAC_CSR2: STA MAC register 0.
227 #define MAC_CSR2 0x3008
228 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
229 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
230 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
231 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
234 * MAC_CSR3: STA MAC register 1.
236 #define MAC_CSR3 0x300c
237 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
238 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
239 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
242 * MAC_CSR4: BSSID register 0.
244 #define MAC_CSR4 0x3010
245 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
246 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
247 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
248 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
251 * MAC_CSR5: BSSID register 1.
252 * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
254 #define MAC_CSR5 0x3014
255 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
256 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
257 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
260 * MAC_CSR6: Maximum frame length register.
262 #define MAC_CSR6 0x3018
263 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x000007ff)
268 #define MAC_CSR7 0x301c
271 * MAC_CSR8: SIFS/EIFS register.
272 * All units are in US.
274 #define MAC_CSR8 0x3020
275 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
276 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
277 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
280 * MAC_CSR9: Back-Off control register.
281 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
282 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
283 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
284 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
286 #define MAC_CSR9 0x3024
287 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
288 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
289 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
290 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
293 * MAC_CSR10: Power state configuration.
295 #define MAC_CSR10 0x3028
298 * MAC_CSR11: Power saving transition time register.
299 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
300 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
301 * WAKEUP_LATENCY: In unit of TU.
303 #define MAC_CSR11 0x302c
304 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
305 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
306 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
307 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
310 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
311 * CURRENT_STATE: 0:sleep, 1:awake.
312 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
313 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
315 #define MAC_CSR12 0x3030
316 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
317 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
318 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
319 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
324 #define MAC_CSR13 0x3034
325 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
326 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
327 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
328 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
329 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
330 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
331 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
332 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
335 * MAC_CSR14: LED control register.
336 * ON_PERIOD: On period, default 70ms.
337 * OFF_PERIOD: Off period, default 30ms.
338 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
339 * SW_LED: s/w LED, 1: ON, 0: OFF.
340 * HW_LED_POLARITY: 0: active low, 1: active high.
342 #define MAC_CSR14 0x3038
343 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
344 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
345 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
346 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
347 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
348 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
351 * MAC_CSR15: NAV control.
353 #define MAC_CSR15 0x303c
356 * TXRX control registers.
357 * Some values are set in TU, whereas 1 TU == 1024 us.
361 * TXRX_CSR0: TX/RX configuration register.
362 * TSF_OFFSET: Default is 24.
363 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
364 * DISABLE_RX: Disable Rx engine.
365 * DROP_CRC: Drop CRC error.
366 * DROP_PHYSICAL: Drop physical error.
367 * DROP_CONTROL: Drop control frame.
368 * DROP_NOT_TO_ME: Drop not to me unicast frame.
369 * DROP_TO_DS: Drop fram ToDs bit is true.
370 * DROP_VERSION_ERROR: Drop version error frame.
371 * DROP_MULTICAST: Drop multicast frames.
372 * DROP_BORADCAST: Drop broadcast frames.
373 * ROP_ACK_CTS: Drop received ACK and CTS.
375 #define TXRX_CSR0 0x3040
376 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
377 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
378 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
379 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
380 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
381 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
382 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
383 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
384 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
385 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
386 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
387 #define TXRX_CSR0_DROP_BORADCAST FIELD32(0x01000000)
388 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
389 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
394 #define TXRX_CSR1 0x3044
399 #define TXRX_CSR2 0x3048
404 #define TXRX_CSR3 0x304c
407 * TXRX_CSR4: Auto-Responder/Tx-retry register.
408 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
409 * OFDM_TX_RATE_DOWN: 1:enable.
410 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
411 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
413 #define TXRX_CSR4 0x3050
414 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
415 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
416 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
417 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
418 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
419 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
420 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
421 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
422 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
423 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
428 #define TXRX_CSR5 0x3054
431 * ACK/CTS payload consumed time registers.
433 #define TXRX_CSR6 0x3058
434 #define TXRX_CSR7 0x305c
435 #define TXRX_CSR8 0x3060
438 * TXRX_CSR9: Synchronization control register.
439 * BEACON_INTERVAL: In unit of 1/16 TU.
440 * TSF_TICKING: Enable TSF auto counting.
441 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
442 * BEACON_GEN: Enable beacon generator.
444 #define TXRX_CSR9 0x3064
445 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
446 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
447 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
448 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
449 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
450 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
453 * TXRX_CSR10: BEACON alignment.
455 #define TXRX_CSR10 0x3068
458 * TXRX_CSR11: AES mask.
460 #define TXRX_CSR11 0x306c
463 * TXRX_CSR12: TSF low 32.
465 #define TXRX_CSR12 0x3070
466 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
469 * TXRX_CSR13: TSF high 32.
471 #define TXRX_CSR13 0x3074
472 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
475 * TXRX_CSR14: TBTT timer.
477 #define TXRX_CSR14 0x3078
480 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
482 #define TXRX_CSR15 0x307c
486 * PHY control registers.
487 * Some values are set in TU, whereas 1 TU == 1024 us.
491 * PHY_CSR0: RF/PS control.
493 #define PHY_CSR0 0x3080
494 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
495 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
500 #define PHY_CSR1 0x3084
503 * PHY_CSR2: Pre-TX BBP control.
505 #define PHY_CSR2 0x3088
508 * PHY_CSR3: BBP serial control register.
509 * VALUE: Register value to program into BBP.
510 * REG_NUM: Selected BBP register.
511 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
512 * BUSY: 1: ASIC is busy execute BBP programming.
514 #define PHY_CSR3 0x308c
515 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
516 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
517 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
518 #define PHY_CSR3_BUSY FIELD32(0x00010000)
521 * PHY_CSR4: RF serial control register
522 * VALUE: Register value (include register id) serial out to RF/IF chip.
523 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
524 * IF_SELECT: 1: select IF to program, 0: select RF to program.
525 * PLL_LD: RF PLL_LD status.
526 * BUSY: 1: ASIC is busy execute RF programming.
528 #define PHY_CSR4 0x3090
529 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
530 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
531 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
532 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
533 #define PHY_CSR4_BUSY FIELD32(0x80000000)
536 * PHY_CSR5: RX to TX signal switch timing control.
538 #define PHY_CSR5 0x3094
541 * PHY_CSR6: TX to RX signal timing control.
543 #define PHY_CSR6 0x3098
546 * PHY_CSR7: TX DAC switching timing control.
548 #define PHY_CSR7 0x309c
551 * Security control register.
555 * SEC_CSR0: Shared key table control.
557 #define SEC_CSR0 0x30a0
560 * SEC_CSR1: Shared key table security mode register.
562 #define SEC_CSR1 0x30a4
563 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
564 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
565 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
566 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
567 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
568 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
569 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
570 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
573 * Pairwise key table valid bitmap registers.
574 * SEC_CSR2: pairwise key table valid bitmap 0.
575 * SEC_CSR3: pairwise key table valid bitmap 1.
577 #define SEC_CSR2 0x30a8
578 #define SEC_CSR3 0x30ac
581 * SEC_CSR4: Pairwise key table lookup control.
583 #define SEC_CSR4 0x30b0
586 * SEC_CSR5: shared key table security mode register.
588 #define SEC_CSR5 0x30b4
589 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
590 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
591 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
592 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
593 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
594 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
595 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
596 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
599 * STA control registers.
603 * STA_CSR0: RX PLCP error count & RX FCS error count.
605 #define STA_CSR0 0x30c0
606 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
607 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
610 * STA_CSR1: RX False CCA count & RX LONG frame count.
612 #define STA_CSR1 0x30c4
613 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
614 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
617 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
619 #define STA_CSR2 0x30c8
620 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
621 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
624 * STA_CSR3: TX Beacon count.
626 #define STA_CSR3 0x30cc
627 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
630 * STA_CSR4: TX Result status register.
631 * VALID: 1:This register contains a valid TX result.
633 #define STA_CSR4 0x30d0
634 #define STA_CSR4_VALID FIELD32(0x00000001)
635 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
636 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
637 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
638 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
639 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
642 * QOS control registers.
646 * QOS_CSR0: TXOP holder MAC address register.
648 #define QOS_CSR0 0x30e0
649 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
650 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
651 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
652 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
655 * QOS_CSR1: TXOP holder MAC address register.
657 #define QOS_CSR1 0x30e4
658 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
659 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
662 * QOS_CSR2: TXOP holder timeout register.
664 #define QOS_CSR2 0x30e8
667 * RX QOS-CFPOLL MAC address register.
668 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
669 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
671 #define QOS_CSR3 0x30ec
672 #define QOS_CSR4 0x30f0
675 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
677 #define QOS_CSR5 0x30f4
680 * Host DMA registers.
684 * AC0_BASE_CSR: AC_BK base address.
686 #define AC0_BASE_CSR 0x3400
687 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
690 * AC1_BASE_CSR: AC_BE base address.
692 #define AC1_BASE_CSR 0x3404
693 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
696 * AC2_BASE_CSR: AC_VI base address.
698 #define AC2_BASE_CSR 0x3408
699 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
702 * AC3_BASE_CSR: AC_VO base address.
704 #define AC3_BASE_CSR 0x340c
705 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
708 * MGMT_BASE_CSR: MGMT ring base address.
710 #define MGMT_BASE_CSR 0x3410
711 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
714 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
716 #define TX_RING_CSR0 0x3418
717 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
718 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
719 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
720 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
723 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
724 * TXD_SIZE: In unit of 32-bit.
726 #define TX_RING_CSR1 0x341c
727 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
728 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
729 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
732 * AIFSN_CSR: AIFSN for each EDCA AC.
738 #define AIFSN_CSR 0x3420
739 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
740 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
741 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
742 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
745 * CWMIN_CSR: CWmin for each EDCA AC.
751 #define CWMIN_CSR 0x3424
752 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
753 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
754 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
755 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
758 * CWMAX_CSR: CWmax for each EDCA AC.
764 #define CWMAX_CSR 0x3428
765 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
766 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
767 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
768 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
773 #define TX_DMA_DST_CSR 0x342c
776 * TX_CNTL_CSR: KICK/Abort TX.
777 * KICK_TX_AC0: For AC_BK.
778 * KICK_TX_AC1: For AC_BE.
779 * KICK_TX_AC2: For AC_VI.
780 * KICK_TX_AC3: For AC_VO.
781 * ABORT_TX_AC0: For AC_BK.
782 * ABORT_TX_AC1: For AC_BE.
783 * ABORT_TX_AC2: For AC_VI.
784 * ABORT_TX_AC3: For AC_VO.
786 #define TX_CNTL_CSR 0x3430
787 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
788 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
789 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
790 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
791 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
792 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
793 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
794 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
795 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
796 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
801 #define LOAD_TX_RING_CSR 0x3434
804 * Several read-only registers, for debugging.
806 #define AC0_TXPTR_CSR 0x3438
807 #define AC1_TXPTR_CSR 0x343c
808 #define AC2_TXPTR_CSR 0x3440
809 #define AC3_TXPTR_CSR 0x3444
810 #define MGMT_TXPTR_CSR 0x3448
815 #define RX_BASE_CSR 0x3450
816 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
820 * RXD_SIZE: In unit of 32-bit.
822 #define RX_RING_CSR 0x3454
823 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
824 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
825 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
830 #define RX_CNTL_CSR 0x3458
833 * RXPTR_CSR: Read-only, for debugging.
835 #define RXPTR_CSR 0x345c
840 #define PCI_CFG_CSR 0x3460
845 #define BUF_FORMAT_CSR 0x3464
848 * INT_SOURCE_CSR: Interrupt source register.
849 * Write one to clear corresponding bit.
851 #define INT_SOURCE_CSR 0x3468
852 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
853 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
854 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
855 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
856 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
857 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
858 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
859 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
860 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
861 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
864 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
865 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
867 #define INT_MASK_CSR 0x346c
868 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
869 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
870 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
871 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
872 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
873 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
874 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
875 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
876 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
877 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
878 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
879 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
882 * E2PROM_CSR: EEPROM control register.
883 * RELOAD: Write 1 to reload eeprom content.
884 * TYPE_93C46: 1: 93c46, 0:93c66.
885 * LOAD_STATUS: 1:loading, 0:done.
887 #define E2PROM_CSR 0x3470
888 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
889 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
890 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
891 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
892 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
893 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
894 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
897 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
898 * AC0_TX_OP: For AC_BK, in unit of 32us.
899 * AC1_TX_OP: For AC_BE, in unit of 32us.
901 #define AC_TXOP_CSR0 0x3474
902 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
903 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
906 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
907 * AC2_TX_OP: For AC_VI, in unit of 32us.
908 * AC3_TX_OP: For AC_VO, in unit of 32us.
910 #define AC_TXOP_CSR1 0x3478
911 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
912 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
917 #define DMA_STATUS_CSR 0x3480
922 #define TEST_MODE_CSR 0x3484
927 #define UART0_TX_CSR 0x3488
932 #define UART0_RX_CSR 0x348c
937 #define UART0_FRAME_CSR 0x3490
942 #define UART0_BUFFER_CSR 0x3494
947 #define IO_CNTL_CSR 0x3498
950 * UART_INT_SOURCE_CSR
952 #define UART_INT_SOURCE_CSR 0x34a8
957 #define UART_INT_MASK_CSR 0x34ac
962 #define PBF_QUEUE_CSR 0x34b0
965 * Firmware DMA registers.
966 * Firmware DMA registers are dedicated for MCU usage
967 * and should not be touched by host driver.
968 * Therefore we skip the definition of these registers.
970 #define FW_TX_BASE_CSR 0x34c0
971 #define FW_TX_START_CSR 0x34c4
972 #define FW_TX_LAST_CSR 0x34c8
973 #define FW_MODE_CNTL_CSR 0x34cc
974 #define FW_TXPTR_CSR 0x34d0
977 * 8051 firmware image.
979 #define FIRMWARE_RT2561 "rt2561.bin"
980 #define FIRMWARE_RT2561s "rt2561s.bin"
981 #define FIRMWARE_RT2661 "rt2661.bin"
982 #define FIRMWARE_IMAGE_BASE 0x4000
987 #define RF3_TXPOWER FIELD32(0x00003e00)
988 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
992 * The wordsize of the EEPROM is 16 bits.
998 #define EEPROM_MAC_ADDR_0 0x0002
999 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1000 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1001 #define EEPROM_MAC_ADDR1 0x0004
1002 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1003 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1004 #define EEPROM_MAC_ADDR_2 0x0006
1005 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1006 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1010 * ANTENNA_NUM: Number of antenna's.
1011 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1012 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1013 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1014 * DYN_TXAGC: Dynamic TX AGC control.
1015 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1016 * RF_TYPE: Rf_type of this adapter.
1018 #define EEPROM_ANTENNA 0x0010
1019 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1020 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1021 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1022 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1023 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1024 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1025 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1028 * EEPROM NIC config.
1029 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1030 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1031 * CARDBUS_ACCEL: 0:enable, 1:disable.
1032 * EXTERNAL_LNA_A: External LNA enable for 5G.
1034 #define EEPROM_NIC 0x0011
1035 #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1036 #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1037 #define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
1038 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1039 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1040 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1044 * GEO_A: Default geographical setting for 5GHz band
1045 * GEO: Default geographical setting.
1047 #define EEPROM_GEOGRAPHY 0x0012
1048 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1049 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1054 #define EEPROM_BBP_START 0x0013
1055 #define EEPROM_BBP_SIZE 16
1056 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1057 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1060 * EEPROM TXPOWER 802.11G
1062 #define EEPROM_TXPOWER_G_START 0x0023
1063 #define EEPROM_TXPOWER_G_SIZE 7
1064 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1065 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1070 #define EEPROM_FREQ 0x002f
1071 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1072 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1073 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
1077 * POLARITY_RDY_G: Polarity RDY_G setting.
1078 * POLARITY_RDY_A: Polarity RDY_A setting.
1079 * POLARITY_ACT: Polarity ACT setting.
1080 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1081 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1082 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1083 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1084 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1085 * LED_MODE: Led mode.
1087 #define EEPROM_LED 0x0030
1088 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1089 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1090 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1091 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1092 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1093 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1094 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1095 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1096 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1099 * EEPROM TXPOWER 802.11A
1101 #define EEPROM_TXPOWER_A_START 0x0031
1102 #define EEPROM_TXPOWER_A_SIZE 12
1103 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1104 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1107 * EEPROM RSSI offset 802.11BG
1109 #define EEPROM_RSSI_OFFSET_BG 0x004d
1110 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1111 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1114 * EEPROM RSSI offset 802.11A
1116 #define EEPROM_RSSI_OFFSET_A 0x004e
1117 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1118 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1122 * The wordsize of the BBP is 8 bits.
1128 #define BBP_R2_BG_MODE FIELD8(0x20)
1133 #define BBP_R3_SMART_MODE FIELD8(0x01)
1136 * BBP_R4: RX antenna control
1137 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1139 #define BBP_R4_RX_ANTENNA FIELD8(0x03)
1140 #define BBP_R4_RX_FRAME_END FIELD8(0x10)
1141 #define BBP_R4_RX_BG_MODE FIELD8(0x20)
1146 #define BBP_R77_PAIR FIELD8(0x03)
1149 * MCU mailbox commands.
1151 #define MCU_SLEEP 0x30
1152 #define MCU_WAKEUP 0x31
1153 #define MCU_LED 0x50
1154 #define MCU_LED_STRENGTH 0x52
1157 * DMA descriptor defines.
1159 #define TXD_DESC_SIZE ( 16 * sizeof(struct data_desc) )
1160 #define RXD_DESC_SIZE ( 16 * sizeof(struct data_desc) )
1163 * TX descriptor format for TX, PRIO and Beacon Ring.
1168 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1169 * KEY_TABLE: Use per-client pairwise KEY table.
1171 * Key index (0~31) to the pairwise KEY table.
1172 * 0~3 to shared KEY table 0 (BSS0).
1173 * 4~7 to shared KEY table 1 (BSS1).
1174 * 8~11 to shared KEY table 2 (BSS2).
1175 * 12~15 to shared KEY table 3 (BSS3).
1176 * BURST: Next frame belongs to same "burst" event.
1178 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1179 #define TXD_W0_VALID FIELD32(0x00000002)
1180 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1181 #define TXD_W0_ACK FIELD32(0x00000008)
1182 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1183 #define TXD_W0_OFDM FIELD32(0x00000020)
1184 #define TXD_W0_IFS FIELD32(0x00000040)
1185 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1186 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1187 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1188 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1189 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1190 #define TXD_W0_BURST FIELD32(0x10000000)
1191 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1195 * HOST_Q_ID: EDCA/HCCA queue ID.
1196 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1197 * BUFFER_COUNT: Number of buffers in this TXD.
1199 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1200 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1201 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1202 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1203 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1204 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1205 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1206 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1209 * Word2: PLCP information
1211 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1212 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1213 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1214 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1219 #define TXD_W3_IV FIELD32(0xffffffff)
1224 #define TXD_W4_EIV FIELD32(0xffffffff)
1228 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1229 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1230 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1231 * WAITING_DMA_DONE_INT: TXD been filled with data
1232 * and waiting for TxDoneISR housekeeping.
1234 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1235 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1236 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1237 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1238 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1241 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1242 * through TXFIFO. MAC block use this TXINFO to control the transmission
1243 * behavior of this frame.
1244 * The following fields are not used by MAC block.
1245 * They are used by DMA block and HOST driver only.
1246 * Once a frame has been DMA to ASIC, all the following fields are useless
1251 * Word6-10: Buffer physical address
1253 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1254 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1255 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1256 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1257 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1260 * Word11-13: Buffer length
1262 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1263 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1264 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1265 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1266 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1271 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1276 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1279 * RX descriptor format for RX Ring.
1284 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1285 * KEY_INDEX: Decryption key actually used.
1287 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1288 #define RXD_W0_DROP FIELD32(0x00000002)
1289 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1290 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1291 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1292 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1293 #define RXD_W0_CRC FIELD32(0x00000040)
1294 #define RXD_W0_OFDM FIELD32(0x00000080)
1295 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1296 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1297 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1298 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1302 * SIGNAL: RX raw data rate reported by BBP.
1304 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1305 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1306 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1307 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1311 * IV: Received IV of originally encrypted.
1313 #define RXD_W2_IV FIELD32(0xffffffff)
1317 * EIV: Received EIV of originally encrypted.
1319 #define RXD_W3_EIV FIELD32(0xffffffff)
1324 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1327 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1328 * and passed to the HOST driver.
1329 * The following fields are for DMA block and HOST usage only.
1330 * Can't be touched by ASIC MAC block.
1336 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1339 * Word6-15: Reserved
1341 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1342 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1343 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1344 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1345 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1346 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1347 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1348 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1349 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1350 #define RXD_W15_RESERVED FIELD32(0xffffffff)
1353 * Macro's for converting txpower from EEPROM to dscape value
1354 * and from dscape value to register value.
1356 #define MIN_TXPOWER 0
1357 #define MAX_TXPOWER 31
1358 #define DEFAULT_TXPOWER 24
1360 #define TXPOWER_FROM_DEV(__txpower) \
1362 ((__txpower) > MAX_TXPOWER) ? \
1363 DEFAULT_TXPOWER : (__txpower); \
1366 #define TXPOWER_TO_DEV(__txpower) \
1368 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1369 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1373 #endif /* RT61PCI_H */
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