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[target/generic]: preliminary 2.6.38 support
[openwrt.git] / target / linux / brcm63xx / patches-2.6.35 / 240-spi.patch
1 --- a/arch/mips/bcm63xx/cpu.c
2 +++ b/arch/mips/bcm63xx/cpu.c
3 @@ -56,6 +56,7 @@ static const unsigned long bcm96338_regs
4
5 static const int bcm96338_irqs[] = {
6 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
8 [IRQ_UART0] = BCM_6338_UART0_IRQ,
9 [IRQ_DSL] = BCM_6338_DSL_IRQ,
10 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11 @@ -130,6 +131,7 @@ static const unsigned long bcm96348_regs
12
13 static const int bcm96348_irqs[] = {
14 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
16 [IRQ_UART0] = BCM_6348_UART0_IRQ,
17 [IRQ_DSL] = BCM_6348_DSL_IRQ,
18 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19 @@ -173,6 +175,7 @@ static const unsigned long bcm96358_regs
20
21 static const int bcm96358_irqs[] = {
22 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
24 [IRQ_UART0] = BCM_6358_UART0_IRQ,
25 [IRQ_UART1] = BCM_6358_UART1_IRQ,
26 [IRQ_DSL] = BCM_6358_DSL_IRQ,
27 --- /dev/null
28 +++ b/arch/mips/bcm63xx/dev-spi.c
29 @@ -0,0 +1,127 @@
30 +/*
31 + * This file is subject to the terms and conditions of the GNU General Public
32 + * License. See the file "COPYING" in the main directory of this archive
33 + * for more details.
34 + *
35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
36 + */
37 +
38 +#include <linux/init.h>
39 +#include <linux/kernel.h>
40 +#include <linux/platform_device.h>
41 +
42 +#include <bcm63xx_cpu.h>
43 +#include <bcm63xx_dev_spi.h>
44 +#include <bcm63xx_regs.h>
45 +
46 +#ifdef BCMCPU_RUNTIME_DETECT
47 +/*
48 + * register offsets
49 + */
50 +static const unsigned long bcm96338_regs_spi[] = {
51 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
52 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
53 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
54 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
55 + [SPI_ST] = SPI_BCM_6338_SPI_ST,
56 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
57 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
58 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
59 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
60 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
61 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
62 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
63 +};
64 +
65 +static const unsigned long bcm96348_regs_spi[] = {
66 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
67 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
68 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
69 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
70 + [SPI_ST] = SPI_BCM_6348_SPI_ST,
71 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
72 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
73 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
74 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
75 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
76 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
77 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
78 +};
79 +
80 +static const unsigned long bcm96358_regs_spi[] = {
81 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
82 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
83 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
84 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
85 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
86 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
87 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
88 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
89 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
90 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
91 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
92 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
93 +};
94 +
95 +const unsigned long *bcm63xx_regs_spi;
96 +EXPORT_SYMBOL(bcm63xx_regs_spi);
97 +
98 +static __init void bcm63xx_spi_regs_init(void)
99 +{
100 + if (BCMCPU_IS_6338())
101 + bcm63xx_regs_spi = bcm96338_regs_spi;
102 + if (BCMCPU_IS_6348())
103 + bcm63xx_regs_spi = bcm96348_regs_spi;
104 + if (BCMCPU_IS_6358())
105 + bcm63xx_regs_spi = bcm96358_regs_spi;
106 +}
107 +#else
108 +static __init void bcm63xx_spi_regs_init(void) { }
109 +#endif
110 +
111 +static struct resource spi_resources[] = {
112 + {
113 + .start = -1, /* filled at runtime */
114 + .end = -1, /* filled at runtime */
115 + .flags = IORESOURCE_MEM,
116 + },
117 + {
118 + .start = -1, /* filled at runtime */
119 + .flags = IORESOURCE_IRQ,
120 + },
121 +};
122 +
123 +static struct bcm63xx_spi_pdata spi_pdata = {
124 + .bus_num = 0,
125 + .num_chipselect = 8,
126 + .speed_hz = 50000000, /* Fclk */
127 +};
128 +
129 +static struct platform_device bcm63xx_spi_device = {
130 + .name = "bcm63xx-spi",
131 + .id = 0,
132 + .num_resources = ARRAY_SIZE(spi_resources),
133 + .resource = spi_resources,
134 + .dev = {
135 + .platform_data = &spi_pdata,
136 + },
137 +};
138 +
139 +int __init bcm63xx_spi_register(void)
140 +{
141 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
142 + spi_resources[0].end = spi_resources[0].start;
143 + spi_resources[0].end += RSET_SPI_SIZE - 1;
144 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
145 +
146 + /* Fill in platform data */
147 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
148 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
149 +
150 + if (BCMCPU_IS_6358())
151 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
152 +
153 + bcm63xx_spi_regs_init();
154 +
155 + return platform_device_register(&bcm63xx_spi_device);
156 +}
157 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
158 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
159 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
160 #define RSET_WDT_SIZE 12
161 #define RSET_ENET_SIZE 2048
162 #define RSET_ENETDMA_SIZE 2048
163 +#define RSET_SPI_SIZE 256
164 #define RSET_UART_SIZE 24
165 #define RSET_UDC_SIZE 256
166 #define RSET_OHCI_SIZE 256
167 @@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
168 #define BCM_6358_UART0_BASE (0xfffe0100)
169 #define BCM_6358_UART1_BASE (0xfffe0120)
170 #define BCM_6358_GPIO_BASE (0xfffe0080)
171 -#define BCM_6358_SPI_BASE (0xdeadbeef)
172 +#define BCM_6358_SPI_BASE (0xfffe0800)
173 #define BCM_6358_UDC0_BASE (0xfffe0400)
174 #define BCM_6358_OHCI0_BASE (0xfffe1400)
175 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
176 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
177 */
178 enum bcm63xx_irq {
179 IRQ_TIMER = 0,
180 + IRQ_SPI,
181 IRQ_UART0,
182 IRQ_UART1,
183 IRQ_DSL,
184 @@ -507,6 +509,7 @@ enum bcm63xx_irq {
185 * 6348 irqs
186 */
187 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
188 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
189 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
190 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
191 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
192 @@ -531,6 +534,7 @@ enum bcm63xx_irq {
193 * 6358 irqs
194 */
195 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
196 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
197 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
198 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
199 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
200 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
201 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
202 @@ -769,4 +769,116 @@
203 #define DMIPSPLLCFG_N2_SHIFT 29
204 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
205
206 +/*************************************************************************
207 + * _REG relative to RSET_SPI
208 + *************************************************************************/
209 +
210 +/* BCM 6338 SPI core */
211 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
212 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
213 +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
214 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
215 +#define SPI_BCM_6338_SPI_ST 0x05
216 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
217 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
218 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
219 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
220 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
221 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
222 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
223 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
224 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
225 +
226 +/* BCM 6348 SPI core */
227 +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
228 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01
229 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
230 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
231 +#define SPI_BCM_6348_SPI_CLK_CFG 0x05
232 +#define SPI_BCM_6348_SPI_ST 0x06
233 +#define SPI_BCM_6348_SPI_INT_MASK 0x07
234 +#define SPI_BCM_6348_SPI_RX_TAIL 0x08
235 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
236 +#define SPI_BCM_6348_SPI_MSG_DATA 0x40
237 +#define SPI_BCM_6348_SPI_MSG_CTL 0x42
238 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
239 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
240 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
241 +
242 +/* BCM 6358 SPI core */
243 +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
244 +
245 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
246 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
247 +
248 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
249 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
250 +
251 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
252 +
253 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
254 +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
255 +
256 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
257 +
258 +#define SPI_BCM_6358_SPI_STATUS 0x705
259 +
260 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
261 +
262 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
263 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
264 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
265 +
266 +/* Shared SPI definitions */
267 +
268 +/* Message configuration */
269 +#define SPI_FD_RW 0x00
270 +#define SPI_HD_W 0x01
271 +#define SPI_HD_R 0x02
272 +#define SPI_BYTE_CNT_SHIFT 0
273 +#define SPI_MSG_TYPE_SHIFT 14
274 +
275 +/* Command */
276 +#define SPI_CMD_NOOP 0x01
277 +#define SPI_CMD_SOFT_RESET 0x02
278 +#define SPI_CMD_HARD_RESET 0x04
279 +#define SPI_CMD_START_IMMEDIATE 0x08
280 +#define SPI_CMD_COMMAND_SHIFT 0
281 +#define SPI_CMD_COMMAND_MASK 0x000f
282 +#define SPI_CMD_DEVICE_ID_SHIFT 4
283 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
284 +#define SPI_CMD_ONE_BYTE_SHIFT 11
285 +#define SPI_CMD_ONE_WIRE_SHIFT 12
286 +#define SPI_DEV_ID_0 0
287 +#define SPI_DEV_ID_1 1
288 +#define SPI_DEV_ID_2 2
289 +#define SPI_DEV_ID_3 3
290 +
291 +/* Interrupt mask */
292 +#define SPI_INTR_CMD_DONE 0x01
293 +#define SPI_INTR_RX_OVERFLOW 0x02
294 +#define SPI_INTR_TX_UNDERFLOW 0x04
295 +#define SPI_INTR_TX_OVERFLOW 0x08
296 +#define SPI_INTR_RX_UNDERFLOW 0x10
297 +#define SPI_INTR_CLEAR_ALL 0x1f
298 +
299 +/* Status */
300 +#define SPI_RX_EMPTY 0x02
301 +#define SPI_CMD_BUSY 0x04
302 +#define SPI_SERIAL_BUSY 0x08
303 +
304 +/* Clock configuration */
305 +#define SPI_CLK_20MHZ 0x00
306 +#define SPI_CLK_0_391MHZ 0x01
307 +#define SPI_CLK_0_781MHZ 0x02 /* default */
308 +#define SPI_CLK_1_563MHZ 0x03
309 +#define SPI_CLK_3_125MHZ 0x04
310 +#define SPI_CLK_6_250MHZ 0x05
311 +#define SPI_CLK_12_50MHZ 0x06
312 +#define SPI_CLK_25MHZ 0x07
313 +#define SPI_CLK_MASK 0x07
314 +#define SPI_SSOFFTIME_MASK 0x38
315 +#define SPI_SSOFFTIME_SHIFT 3
316 +#define SPI_BYTE_SWAP 0x80
317 +
318 #endif /* BCM63XX_REGS_H_ */
319 --- /dev/null
320 +++ b/drivers/spi/bcm63xx_spi.c
321 @@ -0,0 +1,494 @@
322 +/*
323 + * Broadcom BCM63xx SPI controller support
324 + *
325 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
326 + *
327 + * This program is free software; you can redistribute it and/or
328 + * modify it under the terms of the GNU General Public License
329 + * as published by the Free Software Foundation; either version 2
330 + * of the License, or (at your option) any later version.
331 + *
332 + * This program is distributed in the hope that it will be useful,
333 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
334 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
335 + * GNU General Public License for more details.
336 + *
337 + * You should have received a copy of the GNU General Public License
338 + * along with this program; if not, write to the
339 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
340 + */
341 +
342 +#include <linux/kernel.h>
343 +#include <linux/init.h>
344 +#include <linux/clk.h>
345 +#include <linux/module.h>
346 +#include <linux/platform_device.h>
347 +#include <linux/delay.h>
348 +#include <linux/interrupt.h>
349 +#include <linux/spi/spi.h>
350 +#include <linux/completion.h>
351 +#include <linux/err.h>
352 +
353 +#include <bcm63xx_dev_spi.h>
354 +
355 +#define PFX KBUILD_MODNAME
356 +#define DRV_VER "0.1.2"
357 +
358 +struct bcm63xx_spi {
359 + spinlock_t lock;
360 + int stopping;
361 + struct completion done;
362 +
363 + void __iomem *regs;
364 + int irq;
365 +
366 + /* Platform data */
367 + u32 speed_hz;
368 + unsigned fifo_size;
369 +
370 + /* Data buffers */
371 + const unsigned char *tx_ptr;
372 + unsigned char *rx_ptr;
373 +
374 + /* data iomem */
375 + u8 __iomem *tx_io;
376 + const u8 __iomem *rx_io;
377 +
378 + int remaining_bytes;
379 +
380 + struct clk *clk;
381 + struct platform_device *pdev;
382 +};
383 +
384 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
385 + unsigned int offset)
386 +{
387 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
388 +}
389 +
390 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
391 + unsigned int offset)
392 +{
393 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
394 +}
395 +
396 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
397 + u8 value, unsigned int offset)
398 +{
399 + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
400 +}
401 +
402 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
403 + u16 value, unsigned int offset)
404 +{
405 + bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
406 +}
407 +
408 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
409 + struct spi_transfer *t)
410 +{
411 + u8 bits_per_word;
412 + u8 clk_cfg;
413 + u32 hz;
414 + unsigned int div;
415 +
416 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
417 +
418 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
419 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
420 + if (bits_per_word != 8) {
421 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
422 + __func__, bits_per_word);
423 + return -EINVAL;
424 + }
425 +
426 + if (spi->chip_select > spi->master->num_chipselect) {
427 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
428 + __func__, spi->chip_select);
429 + return -EINVAL;
430 + }
431 +
432 + /* Check clock setting */
433 + div = (bs->speed_hz / hz);
434 + switch (div) {
435 + case 2:
436 + clk_cfg = SPI_CLK_25MHZ;
437 + break;
438 + case 4:
439 + clk_cfg = SPI_CLK_12_50MHZ;
440 + break;
441 + case 8:
442 + clk_cfg = SPI_CLK_6_250MHZ;
443 + break;
444 + case 16:
445 + clk_cfg = SPI_CLK_3_125MHZ;
446 + break;
447 + case 32:
448 + clk_cfg = SPI_CLK_1_563MHZ;
449 + break;
450 + case 64:
451 + clk_cfg = SPI_CLK_0_781MHZ;
452 + break;
453 + case 128:
454 + default:
455 + /* Set to slowest mode for compatibility */
456 + clk_cfg = SPI_CLK_0_391MHZ;
457 + break;
458 + }
459 +
460 + bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
461 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
462 + div, hz, clk_cfg);
463 +
464 + return 0;
465 +}
466 +
467 +/* the spi->mode bits understood by this driver: */
468 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
469 +
470 +static int bcm63xx_spi_setup(struct spi_device *spi)
471 +{
472 + struct bcm63xx_spi *bs;
473 + int ret;
474 +
475 + bs = spi_master_get_devdata(spi->master);
476 +
477 + if (bs->stopping)
478 + return -ESHUTDOWN;
479 +
480 + if (!spi->bits_per_word)
481 + spi->bits_per_word = 8;
482 +
483 + if (spi->mode & ~MODEBITS) {
484 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
485 + __func__, spi->mode & ~MODEBITS);
486 + return -EINVAL;
487 + }
488 +
489 + ret = bcm63xx_spi_setup_transfer(spi, NULL);
490 + if (ret < 0) {
491 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
492 + spi->mode & ~MODEBITS);
493 + return ret;
494 + }
495 +
496 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
497 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
498 +
499 + return 0;
500 +}
501 +
502 +/* Fill the TX FIFO with as many bytes as possible */
503 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
504 +{
505 + u8 size;
506 +
507 + /* Fill the Tx FIFO with as many bytes as possible */
508 + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
509 + bs->fifo_size;
510 + memcpy_toio(bs->tx_io, bs->tx_ptr, size);
511 + bs->remaining_bytes -= size;
512 +}
513 +
514 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
515 +{
516 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
517 + u16 msg_ctl;
518 + u16 cmd;
519 +
520 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
521 + t->tx_buf, t->rx_buf, t->len);
522 +
523 + /* Transmitter is inhibited */
524 + bs->tx_ptr = t->tx_buf;
525 + bs->rx_ptr = t->rx_buf;
526 + init_completion(&bs->done);
527 +
528 + if (t->tx_buf) {
529 + bs->remaining_bytes = t->len;
530 + bcm63xx_spi_fill_tx_fifo(bs);
531 + }
532 +
533 + /* Enable the command done interrupt which
534 + * we use to determine completion of a command */
535 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
536 +
537 + /* Fill in the Message control register */
538 + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
539 +
540 + if (t->rx_buf && t->tx_buf)
541 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
542 + else if (t->rx_buf)
543 + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
544 + else if (t->tx_buf)
545 + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
546 +
547 + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
548 +
549 + /* Issue the transfer */
550 + cmd = SPI_CMD_START_IMMEDIATE;
551 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
552 + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
553 + bcm_spi_writew(bs, cmd, SPI_CMD);
554 + wait_for_completion(&bs->done);
555 +
556 + /* Disable the CMD_DONE interrupt */
557 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
558 +
559 + return t->len - bs->remaining_bytes;
560 +}
561 +
562 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
563 +{
564 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
565 + struct spi_transfer *t;
566 + int ret = 0;
567 +
568 + if (unlikely(list_empty(&m->transfers)))
569 + return -EINVAL;
570 +
571 + if (bs->stopping)
572 + return -ESHUTDOWN;
573 +
574 + list_for_each_entry(t, &m->transfers, transfer_list) {
575 + ret += bcm63xx_txrx_bufs(spi, t);
576 + }
577 +
578 + m->complete(m->context);
579 +
580 + return ret;
581 +}
582 +
583 +/* This driver supports single master mode only. Hence
584 + * CMD_DONE is the only interrupt we care about
585 + */
586 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
587 +{
588 + struct spi_master *master = (struct spi_master *)dev_id;
589 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
590 + u8 intr;
591 + u16 cmd;
592 +
593 + /* Read interupts and clear them immediately */
594 + intr = bcm_spi_readb(bs, SPI_INT_STATUS);
595 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
596 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
597 +
598 + /* A tansfer completed */
599 + if (intr & SPI_INTR_CMD_DONE) {
600 + u8 rx_tail;
601 +
602 + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
603 +
604 + /* Read out all the data */
605 + if (rx_tail)
606 + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
607 +
608 + /* See if there is more data to send */
609 + if (bs->remaining_bytes > 0) {
610 + bcm63xx_spi_fill_tx_fifo(bs);
611 +
612 + /* Start the transfer */
613 + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
614 + SPI_MSG_CTL);
615 + cmd = bcm_spi_readw(bs, SPI_CMD);
616 + cmd |= SPI_CMD_START_IMMEDIATE;
617 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
618 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
619 + bcm_spi_writew(bs, cmd, SPI_CMD);
620 + } else {
621 + complete(&bs->done);
622 + }
623 + }
624 +
625 + return IRQ_HANDLED;
626 +}
627 +
628 +
629 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
630 +{
631 + struct resource *r;
632 + struct device *dev = &pdev->dev;
633 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
634 + int irq;
635 + struct spi_master *master;
636 + struct clk *clk;
637 + struct bcm63xx_spi *bs;
638 + int ret;
639 +
640 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641 + if (!r) {
642 + dev_err(dev, "no iomem\n");
643 + ret = -ENXIO;
644 + goto out;
645 + }
646 +
647 + irq = platform_get_irq(pdev, 0);
648 + if (irq < 0) {
649 + dev_err(dev, "no irq\n");
650 + ret = -ENXIO;
651 + goto out;
652 + }
653 +
654 + clk = clk_get(dev, "spi");
655 + if (IS_ERR(clk)) {
656 + dev_err(dev, "no clock for device\n");
657 + ret = -ENODEV;
658 + goto out;
659 + }
660 +
661 + master = spi_alloc_master(dev, sizeof(*bs));
662 + if (!master) {
663 + dev_err(dev, "out of memory\n");
664 + ret = -ENOMEM;
665 + goto out_free;
666 + }
667 +
668 + bs = spi_master_get_devdata(master);
669 + init_completion(&bs->done);
670 +
671 + platform_set_drvdata(pdev, master);
672 + bs->pdev = pdev;
673 +
674 + if (!request_mem_region(r->start, r->end - r->start, PFX)) {
675 + dev_err(dev, "iomem request failed\n");
676 + ret = -ENXIO;
677 + goto out_put_master;
678 + }
679 +
680 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
681 + if (!bs->regs) {
682 + dev_err(dev, "unable to ioremap regs\n");
683 + ret = -ENOMEM;
684 + goto out_put_master;
685 + }
686 + bs->irq = irq;
687 + bs->clk = clk;
688 + bs->fifo_size = pdata->fifo_size;
689 +
690 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
691 + if (ret) {
692 + dev_err(dev, "unable to request irq\n");
693 + goto out_unmap;
694 + }
695 +
696 + master->bus_num = pdata->bus_num;
697 + master->num_chipselect = pdata->num_chipselect;
698 + master->setup = bcm63xx_spi_setup;
699 + master->transfer = bcm63xx_transfer;
700 + bs->speed_hz = pdata->speed_hz;
701 + bs->stopping = 0;
702 + bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
703 + bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
704 + spin_lock_init(&bs->lock);
705 +
706 + /* Initialize hardware */
707 + clk_enable(bs->clk);
708 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
709 +
710 + /* register and we are done */
711 + ret = spi_register_master(master);
712 + if (ret) {
713 + dev_err(dev, "spi register failed\n");
714 + goto out_reset_hw;
715 + }
716 +
717 + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
718 + r->start, irq, bs->fifo_size, DRV_VER);
719 +
720 + return 0;
721 +
722 +out_reset_hw:
723 + clk_disable(clk);
724 + free_irq(irq, master);
725 +out_unmap:
726 + iounmap(bs->regs);
727 +out_put_master:
728 + spi_master_put(master);
729 +out_free:
730 + clk_put(clk);
731 +out:
732 + return ret;
733 +}
734 +
735 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
736 +{
737 + struct spi_master *master = platform_get_drvdata(pdev);
738 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
739 + struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
740 +
741 + /* reset spi block */
742 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
743 + spin_lock(&bs->lock);
744 + bs->stopping = 1;
745 +
746 + /* HW shutdown */
747 + clk_disable(bs->clk);
748 + clk_put(bs->clk);
749 +
750 + spin_unlock(&bs->lock);
751 +
752 + free_irq(bs->irq, master);
753 + iounmap(bs->regs);
754 + release_mem_region(r->start, r->end - r->start);
755 + platform_set_drvdata(pdev, 0);
756 + spi_unregister_master(master);
757 +
758 + return 0;
759 +}
760 +
761 +#ifdef CONFIG_PM
762 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
763 +{
764 + struct spi_master *master = platform_get_drvdata(pdev);
765 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
766 +
767 + clk_disable(bs->clk);
768 +
769 + return 0;
770 +}
771 +
772 +static int bcm63xx_spi_resume(struct platform_device *pdev)
773 +{
774 + struct spi_master *master = platform_get_drvdata(pdev);
775 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
776 +
777 + clk_enable(bs->clk);
778 +
779 + return 0;
780 +}
781 +#else
782 +#define bcm63xx_spi_suspend NULL
783 +#define bcm63xx_spi_resume NULL
784 +#endif
785 +
786 +static struct platform_driver bcm63xx_spi_driver = {
787 + .driver = {
788 + .name = "bcm63xx-spi",
789 + .owner = THIS_MODULE,
790 + },
791 + .probe = bcm63xx_spi_probe,
792 + .remove = __exit_p(bcm63xx_spi_remove),
793 + .suspend = bcm63xx_spi_suspend,
794 + .resume = bcm63xx_spi_resume,
795 +};
796 +
797 +
798 +static int __init bcm63xx_spi_init(void)
799 +{
800 + return platform_driver_register(&bcm63xx_spi_driver);
801 +}
802 +
803 +static void __exit bcm63xx_spi_exit(void)
804 +{
805 + platform_driver_unregister(&bcm63xx_spi_driver);
806 +}
807 +
808 +module_init(bcm63xx_spi_init);
809 +module_exit(bcm63xx_spi_exit);
810 +
811 +MODULE_ALIAS("platform:bcm63xx_spi");
812 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
813 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
814 +MODULE_LICENSE("GPL");
815 +MODULE_VERSION(DRV_VER);
816 --- a/drivers/spi/Kconfig
817 +++ b/drivers/spi/Kconfig
818 @@ -60,6 +60,12 @@ config SPI_ATMEL
819 This selects a driver for the Atmel SPI Controller, present on
820 many AT32 (AVR32) and AT91 (ARM) chips.
821
822 +config SPI_BCM63XX
823 + tristate "Broadcom BCM63xx SPI controller"
824 + depends on BCM63XX
825 + help
826 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
827 +
828 config SPI_BFIN
829 tristate "SPI controller driver for ADI Blackfin5xx"
830 depends on BLACKFIN
831 --- a/drivers/spi/Makefile
832 +++ b/drivers/spi/Makefile
833 @@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
834 obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
835 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
836 obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
837 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
838
839 # special build for s3c24xx spi driver with fiq support
840 spi_s3c24xx_hw-y := spi_s3c24xx.o
841 --- /dev/null
842 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
843 @@ -0,0 +1,126 @@
844 +#ifndef BCM63XX_DEV_SPI_H
845 +#define BCM63XX_DEV_SPI_H
846 +
847 +#include <linux/types.h>
848 +#include <bcm63xx_io.h>
849 +#include <bcm63xx_regs.h>
850 +
851 +int __init bcm63xx_spi_register(void);
852 +
853 +struct bcm63xx_spi_pdata {
854 + unsigned int fifo_size;
855 + int bus_num;
856 + int num_chipselect;
857 + u32 speed_hz;
858 +};
859 +
860 +enum bcm63xx_regs_spi {
861 + SPI_CMD,
862 + SPI_INT_STATUS,
863 + SPI_INT_MASK_ST,
864 + SPI_INT_MASK,
865 + SPI_ST,
866 + SPI_CLK_CFG,
867 + SPI_FILL_BYTE,
868 + SPI_MSG_TAIL,
869 + SPI_RX_TAIL,
870 + SPI_MSG_CTL,
871 + SPI_MSG_DATA,
872 + SPI_RX_DATA,
873 +};
874 +
875 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
876 +{
877 +#ifdef BCMCPU_RUNTIME_DETECT
878 + extern const unsigned long *bcm63xx_regs_spi;
879 + return bcm63xx_regs_spi[reg];
880 +#else
881 +#ifdef CONFIG_BCM63XX_CPU_6338
882 +switch (reg) {
883 + case SPI_CMD:
884 + return SPI_BCM_6338_SPI_CMD;
885 + case SPI_INT_STATUS:
886 + return SPI_BCM_6338_SPI_INT_STATUS;
887 + case SPI_INT_MASK_ST:
888 + return SPI_BCM_6338_SPI_MASK_INT_ST;
889 + case SPI_INT_MASK:
890 + return SPI_BCM_6338_SPI_INT_MASK;
891 + case SPI_ST:
892 + return SPI_BCM_6338_SPI_ST;
893 + case SPI_CLK_CFG:
894 + return SPI_BCM_6338_SPI_CLK_CFG;
895 + case SPI_FILL_BYTE:
896 + return SPI_BCM_6338_SPI_FILL_BYTE;
897 + case SPI_MSG_TAIL:
898 + return SPI_BCM_6338_SPI_MSG_TAIL;
899 + case SPI_RX_TAIL:
900 + return SPI_BCM_6338_SPI_RX_TAIL;
901 + case SPI_MSG_CTL:
902 + return SPI_BCM_6338_SPI_MSG_CTL;
903 + case SPI_MSG_DATA:
904 + return SPI_BCM_6338_SPI_MSG_DATA;
905 + case SPI_RX_DATA:
906 + return SPI_BCM_6338_SPI_RX_DATA;
907 +}
908 +#endif
909 +#ifdef CONFIG_BCM63XX_CPU_6348
910 +switch (reg) {
911 + case SPI_CMD:
912 + return SPI_BCM_6348_SPI_CMD;
913 + case SPI_INT_MASK_ST:
914 + return SPI_BCM_6348_SPI_MASK_INT_ST;
915 + case SPI_INT_MASK:
916 + return SPI_BCM_6348_SPI_INT_MASK;
917 + case SPI_INT_STATUS:
918 + return SPI_BCM_6348_SPI_INT_STATUS;
919 + case SPI_ST:
920 + return SPI_BCM_6348_SPI_ST;
921 + case SPI_CLK_CFG:
922 + return SPI_BCM_6348_SPI_CLK_CFG;
923 + case SPI_FILL_BYTE:
924 + return SPI_BCM_6348_SPI_FILL_BYTE;
925 + case SPI_MSG_TAIL:
926 + return SPI_BCM_6348_SPI_MSG_TAIL;
927 + case SPI_RX_TAIL:
928 + return SPI_BCM_6348_SPI_RX_TAIL;
929 + case SPI_MSG_CTL:
930 + return SPI_BCM_6348_SPI_MSG_CTL;
931 + case SPI_MSG_DATA:
932 + return SPI_BCM_6348_SPI_MSG_DATA;
933 + case SPI_RX_DATA:
934 + return SPI_BCM_6348_SPI_RX_DATA;
935 +}
936 +#endif
937 +#ifdef CONFIG_BCM63XX_CPU_6358
938 +switch (reg) {
939 + case SPI_CMD:
940 + return SPI_BCM_6358_SPI_CMD;
941 + case SPI_INT_STATUS:
942 + return SPI_BCM_6358_SPI_INT_STATUS;
943 + case SPI_INT_MASK_ST:
944 + return SPI_BCM_6358_SPI_MASK_INT_ST;
945 + case SPI_INT_MASK:
946 + return SPI_BCM_6358_SPI_INT_MASK;
947 + case SPI_ST:
948 + return SPI_BCM_6358_SPI_STATUS;
949 + case SPI_CLK_CFG:
950 + return SPI_BCM_6358_SPI_CLK_CFG;
951 + case SPI_FILL_BYTE:
952 + return SPI_BCM_6358_SPI_FILL_BYTE;
953 + case SPI_MSG_TAIL:
954 + return SPI_BCM_6358_SPI_MSG_TAIL;
955 + case SPI_RX_TAIL:
956 + return SPI_BCM_6358_SPI_RX_TAIL;
957 + case SPI_MSG_CTL:
958 + return SPI_BCM_6358_MSG_CTL;
959 + case SPI_MSG_DATA:
960 + return SPI_BCM_6358_SPI_MSG_DATA;
961 + case SPI_RX_DATA:
962 + return SPI_BCM_6358_SPI_RX_DATA;
963 +}
964 +#endif
965 +#endif
966 + return 0;
967 +}
968 +
969 +#endif /* BCM63XX_DEV_SPI_H */
970 --- a/arch/mips/bcm63xx/Makefile
971 +++ b/arch/mips/bcm63xx/Makefile
972 @@ -1,6 +1,6 @@
973 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
974 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
975 - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
976 + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
977 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
978
979 obj-y += boards/
980 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
981 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
982 @@ -33,6 +33,7 @@
983 #include <bcm63xx_dev_usb_ohci.h>
984 #include <bcm63xx_dev_usb_ehci.h>
985 #include <bcm63xx_dev_usb_udc.h>
986 +#include <bcm63xx_dev_spi.h>
987 #include <board_bcm963xx.h>
988
989 #define PFX "board_bcm963xx: "
990 @@ -1587,6 +1588,9 @@ int __init board_register_devices(void)
991 if (board.num_spis)
992 spi_register_board_info(board.spis, board.num_spis);
993
994 + if (!BCMCPU_IS_6345())
995 + bcm63xx_spi_register();
996 +
997 /* read base address of boot chip select (0) */
998 if (BCMCPU_IS_6345())
999 val = 0x1fc00000;
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