[kernel] add a chip_fixup function to the plat_nand driver on 2.6.23 as well (closes...
[openwrt.git] / target / linux / brcm47xx / patches-2.6.23 / 622-ssb-cardbus-fixes.patch
1 Index: linux-2.6.23.17/drivers/ssb/driver_pcicore.c
2 ===================================================================
3 --- linux-2.6.23.17.orig/drivers/ssb/driver_pcicore.c
4 +++ linux-2.6.23.17/drivers/ssb/driver_pcicore.c
5 @@ -11,6 +11,7 @@
6 #include <linux/ssb/ssb.h>
7 #include <linux/pci.h>
8 #include <linux/delay.h>
9 +#include <linux/ssb/ssb_embedded.h>
10
11 #include "ssb_private.h"
12
13 @@ -27,6 +28,18 @@ void pcicore_write32(struct ssb_pcicore
14 ssb_write32(pc->dev, offset, value);
15 }
16
17 +static inline
18 +u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
19 +{
20 + return ssb_read16(pc->dev, offset);
21 +}
22 +
23 +static inline
24 +void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
25 +{
26 + ssb_write16(pc->dev, offset, value);
27 +}
28 +
29 /**************************************************
30 * Code for hostmode operation.
31 **************************************************/
32 @@ -123,8 +136,10 @@ static u32 get_cfgspace_addr(struct ssb_
33 u32 addr = 0;
34 u32 tmp;
35
36 - if (unlikely(pc->cardbusmode && dev > 1))
37 + /* We do only have one cardbus device behind the bridge. */
38 + if (pc->cardbusmode && (dev >= 1))
39 goto out;
40 +
41 if (bus == 0) {
42 /* Type 0 transaction */
43 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
44 @@ -324,7 +339,16 @@ static void ssb_pcicore_init_hostmode(st
45 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
46 udelay(1); /* Assertion time demanded by the PCI standard */
47
48 - /*TODO cardbus mode */
49 + if (pc->dev->bus->has_cardbus_slot) {
50 + ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
51 + pc->cardbusmode = 1;
52 + /* GPIO 1 resets the bridge */
53 + ssb_gpio_out(pc->dev->bus, 1, 1);
54 + ssb_gpio_outen(pc->dev->bus, 1, 1);
55 + pcicore_write16(pc, SSB_PCICORE_SPROM(0),
56 + pcicore_read16(pc, SSB_PCICORE_SPROM(0))
57 + | 0x0400);
58 + }
59
60 /* 64MB I/O window */
61 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
62 Index: linux-2.6.23.17/drivers/ssb/main.c
63 ===================================================================
64 --- linux-2.6.23.17.orig/drivers/ssb/main.c
65 +++ linux-2.6.23.17/drivers/ssb/main.c
66 @@ -559,6 +559,7 @@ static int ssb_fetch_invariants(struct s
67 goto out;
68 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
69 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
70 + bus->has_cardbus_slot = iv.has_cardbus_slot;
71 out:
72 return err;
73 }
74 Index: linux-2.6.23.17/include/linux/ssb/ssb.h
75 ===================================================================
76 --- linux-2.6.23.17.orig/include/linux/ssb/ssb.h
77 +++ linux-2.6.23.17/include/linux/ssb/ssb.h
78 @@ -282,6 +282,8 @@ struct ssb_bus {
79 struct ssb_boardinfo boardinfo;
80 /* Contents of the SPROM. */
81 struct ssb_sprom sprom;
82 + /* If the board has a cardbus slot, this is set to true. */
83 + bool has_cardbus_slot;
84
85 #ifdef CONFIG_SSB_EMBEDDED
86 /* Lock for GPIO register access. */
87 @@ -299,8 +301,13 @@ struct ssb_bus {
88
89 /* The initialization-invariants. */
90 struct ssb_init_invariants {
91 + /* Versioning information about the PCB. */
92 struct ssb_boardinfo boardinfo;
93 + /* The SPROM information. That's either stored in an
94 + * EEPROM or NVRAM on the board. */
95 struct ssb_sprom sprom;
96 + /* If the board has a cardbus slot, this is set to true. */
97 + bool has_cardbus_slot;
98 };
99 /* Type of function to fetch the invariants. */
100 typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
101 Index: linux-2.6.23.17/include/linux/ssb/ssb_driver_pci.h
102 ===================================================================
103 --- linux-2.6.23.17.orig/include/linux/ssb/ssb_driver_pci.h
104 +++ linux-2.6.23.17/include/linux/ssb/ssb_driver_pci.h
105 @@ -51,6 +51,11 @@
106 #define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
107 #define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
108 #define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
109 +#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
110 +#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
111 +#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
112 +#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
113 +#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
114
115 /* SBtoPCIx */
116 #define SSB_PCICORE_SBTOPCI_MEM 0x00000000
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