target/linux/lantiq/patches-2.6.32/0008-MIPS-Lantiq-Add-more-gpio-drivers.patch

   1 From f9391211e47cdcc31f341d710efef4b3b46c333d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 30 Mar 2011 09:27:56 +0200
   4 Subject: [PATCH 08/13] MIPS: Lantiq: Add more gpio drivers
   5
   6 The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only.
   7
   8 [ralf@linux-mips.org: Fixed ltq_stp_probe section() attributes.]
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
  12 Cc: linux-mips@linux-mips.org
  13 Patchwork: https://patchwork.linux-mips.org/patch/2258/
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  arch/mips/lantiq/xway/Makefile   |    2 +-
  17  arch/mips/lantiq/xway/gpio_ebu.c |  126 ++++++++++++++++++++++++++++++
  18  arch/mips/lantiq/xway/gpio_stp.c |  157 ++++++++++++++++++++++++++++++++++++++
  19  3 files changed, 284 insertions(+), 1 deletions(-)
  20  create mode 100644 arch/mips/lantiq/xway/gpio_ebu.c
  21  create mode 100644 arch/mips/lantiq/xway/gpio_stp.c
  22
  23 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
  24 index b1d3640..6b5e07e 100644
  25 --- a/arch/mips/lantiq/xway/Makefile
  26 +++ b/arch/mips/lantiq/xway/Makefile
  27 @@ -1,4 +1,4 @@
  28 -obj-y := pmu.o ebu.o reset.o gpio.o devices.o
  29 +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o
  30
  31  obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
  32  obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
  33 diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
  34 new file mode 100644
  35 index 0000000..a479355
  36 --- /dev/null
  37 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
  38 @@ -0,0 +1,126 @@
  39 +/*
  40 + *  This program is free software; you can redistribute it and/or modify it
  41 + *  under the terms of the GNU General Public License version 2 as published
  42 + *  by the Free Software Foundation.
  43 + *
  44 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  45 + */
  46 +
  47 +#include <linux/init.h>
  48 +#include <linux/module.h>
  49 +#include <linux/types.h>
  50 +#include <linux/platform_device.h>
  51 +#include <linux/mutex.h>
  52 +#include <linux/gpio.h>
  53 +#include <linux/io.h>
  54 +
  55 +#include <lantiq_soc.h>
  56 +
  57 +/*
  58 + * By attaching hardware latches to the EBU it is possible to create output
  59 + * only gpios. This driver configures a special memory address, which when
  60 + * written to outputs 16 bit to the latches.
  61 + */
  62 +
  63 +#define LTQ_EBU_BUSCON 0x1e7ff         /* 16 bit access, slowest timing */
  64 +#define LTQ_EBU_WP     0x80000000      /* write protect bit */
  65 +
  66 +/* we keep a shadow value of the last value written to the ebu */
  67 +static int ltq_ebu_gpio_shadow = 0x0;
  68 +static void __iomem *ltq_ebu_gpio_membase;
  69 +
  70 +static void ltq_ebu_apply(void)
  71 +{
  72 +       unsigned long flags;
  73 +
  74 +       spin_lock_irqsave(&ebu_lock, flags);
  75 +       ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
  76 +       *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow;
  77 +       ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
  78 +       spin_unlock_irqrestore(&ebu_lock, flags);
  79 +}
  80 +
  81 +static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
  82 +{
  83 +       if (value)
  84 +               ltq_ebu_gpio_shadow |= (1 << offset);
  85 +       else
  86 +               ltq_ebu_gpio_shadow &= ~(1 << offset);
  87 +       ltq_ebu_apply();
  88 +}
  89 +
  90 +static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset,
  91 +       int value)
  92 +{
  93 +       ltq_ebu_set(chip, offset, value);
  94 +
  95 +       return 0;
  96 +}
  97 +
  98 +static struct gpio_chip ltq_ebu_chip = {
  99 +       .label = "ltq_ebu",
 100 +       .direction_output = ltq_ebu_direction_output,
 101 +       .set = ltq_ebu_set,
 102 +       .base = 72,
 103 +       .ngpio = 16,
 104 +       .can_sleep = 1,
 105 +       .owner = THIS_MODULE,
 106 +};
 107 +
 108 +static int ltq_ebu_probe(struct platform_device *pdev)
 109 +{
 110 +       int ret = 0;
 111 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 112 +
 113 +       if (!res) {
 114 +               dev_err(&pdev->dev, "failed to get memory resource\n");
 115 +               return -ENOENT;
 116 +       }
 117 +
 118 +       res = devm_request_mem_region(&pdev->dev, res->start,
 119 +               resource_size(res), dev_name(&pdev->dev));
 120 +       if (!res) {
 121 +               dev_err(&pdev->dev, "failed to request memory resource\n");
 122 +               return -EBUSY;
 123 +       }
 124 +
 125 +       ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start,
 126 +               resource_size(res));
 127 +       if (!ltq_ebu_gpio_membase) {
 128 +               dev_err(&pdev->dev, "Failed to ioremap mem region\n");
 129 +               return -ENOMEM;
 130 +       }
 131 +
 132 +       /* grab the default shadow value passed form the platform code */
 133 +       ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data;
 134 +
 135 +       /* tell the ebu controller which memory address we will be using */
 136 +       ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1);
 137 +
 138 +       /* write protect the region */
 139 +       ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
 140 +
 141 +       ret = gpiochip_add(&ltq_ebu_chip);
 142 +       if (!ret)
 143 +               ltq_ebu_apply();
 144 +       return ret;
 145 +}
 146 +
 147 +static struct platform_driver ltq_ebu_driver = {
 148 +       .probe = ltq_ebu_probe,
 149 +       .driver = {
 150 +               .name = "ltq_ebu",
 151 +               .owner = THIS_MODULE,
 152 +       },
 153 +};
 154 +
 155 +static int __init ltq_ebu_init(void)
 156 +{
 157 +       int ret = platform_driver_register(&ltq_ebu_driver);
 158 +
 159 +       if (ret)
 160 +               pr_info("ltq_ebu : Error registering platfom driver!");
 161 +       return ret;
 162 +}
 163 +
 164 +postcore_initcall(ltq_ebu_init);
 165 diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
 166 new file mode 100644
 167 index 0000000..67d59d6
 168 --- /dev/null
 169 +++ b/arch/mips/lantiq/xway/gpio_stp.c
 170 @@ -0,0 +1,157 @@
 171 +/*
 172 + *  This program is free software; you can redistribute it and/or modify it
 173 + *  under the terms of the GNU General Public License version 2 as published
 174 + *  by the Free Software Foundation.
 175 + *
 176 + *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
 177 + *
 178 + */
 179 +
 180 +#include <linux/slab.h>
 181 +#include <linux/init.h>
 182 +#include <linux/module.h>
 183 +#include <linux/types.h>
 184 +#include <linux/platform_device.h>
 185 +#include <linux/mutex.h>
 186 +#include <linux/io.h>
 187 +#include <linux/gpio.h>
 188 +
 189 +#include <lantiq_soc.h>
 190 +
 191 +#define LTQ_STP_CON0           0x00
 192 +#define LTQ_STP_CON1           0x04
 193 +#define LTQ_STP_CPU0           0x08
 194 +#define LTQ_STP_CPU1           0x0C
 195 +#define LTQ_STP_AR             0x10
 196 +
 197 +#define LTQ_STP_CON_SWU                (1 << 31)
 198 +#define LTQ_STP_2HZ            0
 199 +#define LTQ_STP_4HZ            (1 << 23)
 200 +#define LTQ_STP_8HZ            (2 << 23)
 201 +#define LTQ_STP_10HZ           (3 << 23)
 202 +#define LTQ_STP_SPEED_MASK     (0xf << 23)
 203 +#define LTQ_STP_UPD_FPI                (1 << 31)
 204 +#define LTQ_STP_UPD_MASK       (3 << 30)
 205 +#define LTQ_STP_ADSL_SRC       (3 << 24)
 206 +
 207 +#define LTQ_STP_GROUP0         (1 << 0)
 208 +
 209 +#define LTQ_STP_RISING         0
 210 +#define LTQ_STP_FALLING                (1 << 26)
 211 +#define LTQ_STP_EDGE_MASK      (1 << 26)
 212 +
 213 +#define ltq_stp_r32(reg)       __raw_readl(ltq_stp_membase + reg)
 214 +#define ltq_stp_w32(val, reg)  __raw_writel(val, ltq_stp_membase + reg)
 215 +#define ltq_stp_w32_mask(clear, set, reg) \
 216 +               ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \
 217 +               ltq_stp_membase + (reg))
 218 +
 219 +static int ltq_stp_shadow = 0xffff;
 220 +static void __iomem *ltq_stp_membase;
 221 +
 222 +static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
 223 +{
 224 +       if (value)
 225 +               ltq_stp_shadow |= (1 << offset);
 226 +       else
 227 +               ltq_stp_shadow &= ~(1 << offset);
 228 +       ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
 229 +}
 230 +
 231 +static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
 232 +       int value)
 233 +{
 234 +       ltq_stp_set(chip, offset, value);
 235 +
 236 +       return 0;
 237 +}
 238 +
 239 +static struct gpio_chip ltq_stp_chip = {
 240 +       .label = "ltq_stp",
 241 +       .direction_output = ltq_stp_direction_output,
 242 +       .set = ltq_stp_set,
 243 +       .base = 48,
 244 +       .ngpio = 24,
 245 +       .can_sleep = 1,
 246 +       .owner = THIS_MODULE,
 247 +};
 248 +
 249 +static int ltq_stp_hw_init(void)
 250 +{
 251 +       /* the 3 pins used to control the external stp */
 252 +       ltq_gpio_request(4, 1, 0, 1, "stp-st");
 253 +       ltq_gpio_request(5, 1, 0, 1, "stp-d");
 254 +       ltq_gpio_request(6, 1, 0, 1, "stp-sh");
 255 +
 256 +       /* sane defaults */
 257 +       ltq_stp_w32(0, LTQ_STP_AR);
 258 +       ltq_stp_w32(0, LTQ_STP_CPU0);
 259 +       ltq_stp_w32(0, LTQ_STP_CPU1);
 260 +       ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
 261 +       ltq_stp_w32(0, LTQ_STP_CON1);
 262 +
 263 +       /* rising or falling edge */
 264 +       ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
 265 +
 266 +       /* per default stp 15-0 are set */
 267 +       ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
 268 +
 269 +       /* stp are update periodically by the FPI bus */
 270 +       ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
 271 +
 272 +       /* set stp update speed */
 273 +       ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
 274 +
 275 +       /* tell the hardware that pin (led) 0 and 1 are controlled
 276 +        *  by the dsl arc
 277 +        */
 278 +       ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
 279 +
 280 +       ltq_pmu_enable(PMU_LED);
 281 +       return 0;
 282 +}
 283 +
 284 +static int __devinit ltq_stp_probe(struct platform_device *pdev)
 285 +{
 286 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 287 +       int ret = 0;
 288 +
 289 +       if (!res)
 290 +               return -ENOENT;
 291 +       res = devm_request_mem_region(&pdev->dev, res->start,
 292 +               resource_size(res), dev_name(&pdev->dev));
 293 +       if (!res) {
 294 +               dev_err(&pdev->dev, "failed to request STP memory\n");
 295 +               return -EBUSY;
 296 +       }
 297 +       ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start,
 298 +               resource_size(res));
 299 +       if (!ltq_stp_membase) {
 300 +               dev_err(&pdev->dev, "failed to remap STP memory\n");
 301 +               return -ENOMEM;
 302 +       }
 303 +       ret = gpiochip_add(&ltq_stp_chip);
 304 +       if (!ret)
 305 +               ret = ltq_stp_hw_init();
 306 +
 307 +       return ret;
 308 +}
 309 +
 310 +static struct platform_driver ltq_stp_driver = {
 311 +       .probe = ltq_stp_probe,
 312 +       .driver = {
 313 +               .name = "ltq_stp",
 314 +               .owner = THIS_MODULE,
 315 +       },
 316 +};
 317 +
 318 +int __init ltq_stp_init(void)
 319 +{
 320 +       int ret = platform_driver_register(&ltq_stp_driver);
 321 +
 322 +       if (ret)
 323 +               pr_info("ltq_stp: error registering platfom driver");
 324 +       return ret;
 325 +}
 326 +
 327 +postcore_initcall(ltq_stp_init);
 328 --
 329 1.7.2.3
 330