target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

   1 /*
   2  * Ralink RT305x SoC specific setup
   3  *
   4  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  * Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17
  18 #include <asm/mach-ralink/common.h>
  19 #include <asm/mach-ralink/ramips_gpio.h>
  20 #include <asm/mach-ralink/rt305x.h>
  21 #include <asm/mach-ralink/rt305x_regs.h>
  22
  23 void __iomem * rt305x_sysc_base;
  24 void __iomem * rt305x_memc_base;
  25
  26 void __init ramips_soc_prom_init(void)
  27 {
  28         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  29         u32 n0;
  30         u32 n1;
  31         u32 id;
  32
  33         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  34         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  35         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  36
  37         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  38                 "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u",
  39                 (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
  40                 (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
  41                 (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
  42                 (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
  43                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  44                 (id & CHIP_ID_REV_MASK));
  45 }
  46
  47 static struct ramips_gpio_chip rt305x_gpio_chips[] = {
  48         {
  49                 .chip = {
  50                         .label  = "RT305X-GPIO0",
  51                         .base   = 0,
  52                         .ngpio  = 24,
  53                 },
  54                 .regs = {
  55                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  56                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  57                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  58                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  59                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  60                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  61                         [RAMIPS_GPIO_REG_POL]   = 0x28,
  62                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
  63                         [RAMIPS_GPIO_REG_RESET] = 0x30,
  64                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
  65                 },
  66                 .map_base = RT305X_PIO_BASE,
  67                 .map_size = RT305X_PIO_SIZE,
  68         },
  69         {
  70                 .chip = {
  71                         .label  = "RT305X-GPIO1",
  72                         .base   = 24,
  73                         .ngpio  = 16,
  74                 },
  75                 .regs = {
  76                         [RAMIPS_GPIO_REG_INT]   = 0x38,
  77                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
  78                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
  79                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
  80                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
  81                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
  82                         [RAMIPS_GPIO_REG_POL]   = 0x50,
  83                         [RAMIPS_GPIO_REG_SET]   = 0x54,
  84                         [RAMIPS_GPIO_REG_RESET] = 0x58,
  85                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
  86                 },
  87                 .map_base = RT305X_PIO_BASE,
  88                 .map_size = RT305X_PIO_SIZE,
  89         },
  90         {
  91                 .chip = {
  92                         .label  = "RT305X-GPIO2",
  93                         .base   = 40,
  94                         .ngpio  = 12,
  95                 },
  96                 .regs = {
  97                         [RAMIPS_GPIO_REG_INT]   = 0x60,
  98                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
  99                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
 100                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
 101                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 102                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 103                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 104                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 105                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 106                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 107                 },
 108                 .map_base = RT305X_PIO_BASE,
 109                 .map_size = RT305X_PIO_SIZE,
 110         },
 111 };
 112
 113 static struct ramips_gpio_data rt305x_gpio_data = {
 114         .chips = rt305x_gpio_chips,
 115         .num_chips = ARRAY_SIZE(rt305x_gpio_chips),
 116 };
 117
 118 static void rt305x_gpio_reserve(int first, int last)
 119 {
 120         for (; first <= last; first++)
 121                 gpio_request(first, "reserved");
 122 }
 123
 124 void __init rt305x_gpio_init(u32 mode)
 125 {
 126         u32 t;
 127
 128         rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 129
 130         ramips_gpio_init(&rt305x_gpio_data);
 131         if ((mode & RT305X_GPIO_MODE_I2C) == 0)
 132                 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
 133
 134         if ((mode & RT305X_GPIO_MODE_SPI) == 0)
 135                 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
 136
 137         t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
 138         t &= RT305X_GPIO_MODE_UART0_MASK;
 139         switch (t) {
 140         case RT305X_GPIO_MODE_UARTF:
 141         case RT305X_GPIO_MODE_PCM_UARTF:
 142         case RT305X_GPIO_MODE_PCM_I2S:
 143         case RT305X_GPIO_MODE_I2S_UARTF:
 144                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
 145                 break;
 146         case RT305X_GPIO_MODE_PCM_GPIO:
 147                 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
 148                 break;
 149         case RT305X_GPIO_MODE_GPIO_UARTF:
 150         case RT305X_GPIO_MODE_GPIO_I2S:
 151                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
 152                 break;
 153         }
 154
 155         if ((mode & RT305X_GPIO_MODE_UART1) == 0)
 156                 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
 157                                     RT305X_GPIO_UART1_RXD);
 158
 159         if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
 160                 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
 161
 162         if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
 163                 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
 164                                     RT305X_GPIO_MDIO_MDIO);
 165
 166         if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
 167                 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
 168                                     RT305X_GPIO_SDRAM_MD31);
 169
 170         if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
 171                 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
 172                                     RT305X_GPIO_GE0_RXCLK);
 173 }