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[package] mac80211: update ath9k patches
[openwrt.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From dda25991ee4dc0a2ebe2e3b50857971fe1d878c4 Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Sat, 10 Jan 2009 11:03:23 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark and Felix.
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
12 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
13 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
14 ---
15 drivers/net/wireless/rt2x00/Kconfig | 15 +
16 drivers/net/wireless/rt2x00/Makefile | 1 +
17 drivers/net/wireless/rt2x00/rt2800pci.c | 2707 +++++++++++++++++++++++++++++++
18 drivers/net/wireless/rt2x00/rt2800pci.h | 1879 +++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2x00.h | 4 +
20 5 files changed, 4606 insertions(+), 0 deletions(-)
21 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
23 --- a/drivers/net/wireless/rt2x00/Makefile
24 +++ b/drivers/net/wireless/rt2x00/Makefile
25 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
26 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
27 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
28 obj-$(CONFIG_RT61PCI) += rt61pci.o
29 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
30 obj-$(CONFIG_RT2500USB) += rt2500usb.o
31 obj-$(CONFIG_RT73USB) += rt73usb.o
32 --- /dev/null
33 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
34 @@ -0,0 +1,2707 @@
35 +/*
36 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
37 + <http://rt2x00.serialmonkey.com>
38 +
39 + This program is free software; you can redistribute it and/or modify
40 + it under the terms of the GNU General Public License as published by
41 + the Free Software Foundation; either version 2 of the License, or
42 + (at your option) any later version.
43 +
44 + This program is distributed in the hope that it will be useful,
45 + but WITHOUT ANY WARRANTY; without even the implied warranty of
46 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47 + GNU General Public License for more details.
48 +
49 + You should have received a copy of the GNU General Public License
50 + along with this program; if not, write to the
51 + Free Software Foundation, Inc.,
52 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
53 + */
54 +
55 +/*
56 + Module: rt2800pci
57 + Abstract: rt2800pci device specific routines.
58 + Supported chipsets: RT2800E & RT2800ED.
59 + */
60 +
61 +#include <linux/crc-ccitt.h>
62 +#include <linux/delay.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/init.h>
65 +#include <linux/kernel.h>
66 +#include <linux/module.h>
67 +#include <linux/pci.h>
68 +#include <linux/eeprom_93cx6.h>
69 +
70 +#include "rt2x00.h"
71 +#include "rt2x00pci.h"
72 +#include "rt2800pci.h"
73 +
74 +/*
75 + * Allow hardware encryption to be disabled.
76 + */
77 +static int modparam_nohwcrypt = 0;
78 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
79 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
80 +
81 +/*
82 + * Register access.
83 + * BBP and RF register require indirect register access,
84 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
85 + * These indirect registers work with busy bits,
86 + * and we will try maximal REGISTER_BUSY_COUNT times to access
87 + * the register while taking a REGISTER_BUSY_DELAY us delay
88 + * between each attampt. When the busy bit is still set at that time,
89 + * the access attempt is considered to have failed,
90 + * and we will print an error.
91 + */
92 +#define WAIT_FOR_BBP(__dev, __reg) \
93 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
94 +#define WAIT_FOR_RF(__dev, __reg) \
95 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
96 +#define WAIT_FOR_MCU(__dev, __reg) \
97 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
98 + H2M_MAILBOX_CSR_OWNER, (__reg))
99 +
100 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
101 + const unsigned int word, const u8 value)
102 +{
103 + u32 reg;
104 +
105 + mutex_lock(&rt2x00dev->csr_mutex);
106 +
107 + /*
108 + * Wait until the BBP becomes available, afterwards we
109 + * can safely write the new data into the register.
110 + */
111 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
112 + reg = 0;
113 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
114 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
116 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
117 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
118 +
119 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
120 + }
121 +
122 + mutex_unlock(&rt2x00dev->csr_mutex);
123 +}
124 +
125 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
126 + const unsigned int word, u8 *value)
127 +{
128 + u32 reg;
129 +
130 + mutex_lock(&rt2x00dev->csr_mutex);
131 +
132 + /*
133 + * Wait until the BBP becomes available, afterwards we
134 + * can safely write the read request into the register.
135 + * After the data has been written, we wait until hardware
136 + * returns the correct value, if at any time the register
137 + * doesn't become available in time, reg will be 0xffffffff
138 + * which means we return 0xff to the caller.
139 + */
140 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
141 + reg = 0;
142 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
143 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
144 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
145 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
146 +
147 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
148 +
149 + WAIT_FOR_BBP(rt2x00dev, &reg);
150 + }
151 +
152 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
153 +
154 + mutex_unlock(&rt2x00dev->csr_mutex);
155 +}
156 +
157 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
158 + const unsigned int word, const u32 value)
159 +{
160 + u32 reg;
161 +
162 + if (!word)
163 + return;
164 +
165 + mutex_lock(&rt2x00dev->csr_mutex);
166 +
167 + /*
168 + * Wait until the RF becomes available, afterwards we
169 + * can safely write the new data into the register.
170 + */
171 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
172 + reg = 0;
173 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
174 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
175 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
176 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
177 +
178 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
179 + rt2x00_rf_write(rt2x00dev, word, value);
180 + }
181 +
182 + mutex_unlock(&rt2x00dev->csr_mutex);
183 +}
184 +
185 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
186 + const u8 command, const u8 token,
187 + const u8 arg0, const u8 arg1)
188 +{
189 + u32 reg;
190 +
191 + mutex_lock(&rt2x00dev->csr_mutex);
192 +
193 + /*
194 + * Wait until the MCU becomes available, afterwards we
195 + * can safely write the new data into the register.
196 + */
197 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
198 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
199 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
200 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
201 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
202 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
203 +
204 + reg = 0;
205 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
206 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
207 + }
208 +
209 + mutex_unlock(&rt2x00dev->csr_mutex);
210 +}
211 +
212 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
213 +{
214 + struct rt2x00_dev *rt2x00dev = eeprom->data;
215 + u32 reg;
216 +
217 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
218 +
219 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
220 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
221 + eeprom->reg_data_clock =
222 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
223 + eeprom->reg_chip_select =
224 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
225 +}
226 +
227 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
228 +{
229 + struct rt2x00_dev *rt2x00dev = eeprom->data;
230 + u32 reg = 0;
231 +
232 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
233 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
234 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
235 + !!eeprom->reg_data_clock);
236 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
237 + !!eeprom->reg_chip_select);
238 +
239 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
240 +}
241 +
242 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
243 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
244 + .owner = THIS_MODULE,
245 + .csr = {
246 + .read = rt2x00pci_register_read,
247 + .write = rt2x00pci_register_write,
248 + .flags = RT2X00DEBUGFS_OFFSET,
249 + .word_base = CSR_REG_BASE,
250 + .word_size = sizeof(u32),
251 + .word_count = CSR_REG_SIZE / sizeof(u32),
252 + },
253 + .eeprom = {
254 + .read = rt2x00_eeprom_read,
255 + .write = rt2x00_eeprom_write,
256 + .word_base = EEPROM_BASE,
257 + .word_size = sizeof(u16),
258 + .word_count = EEPROM_SIZE / sizeof(u16),
259 + },
260 + .bbp = {
261 + .read = rt2800pci_bbp_read,
262 + .write = rt2800pci_bbp_write,
263 + .word_base = BBP_BASE,
264 + .word_size = sizeof(u8),
265 + .word_count = BBP_SIZE / sizeof(u8),
266 + },
267 + .rf = {
268 + .read = rt2x00_rf_read,
269 + .write = rt2800pci_rf_write,
270 + .word_base = RF_BASE,
271 + .word_size = sizeof(u32),
272 + .word_count = RF_SIZE / sizeof(u32),
273 + },
274 +};
275 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
276 +
277 +#ifdef CONFIG_RT2X00_LIB_RFKILL
278 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
279 +{
280 + u32 reg;
281 +
282 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
283 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
284 +}
285 +#else
286 +#define rt2800pci_rfkill_poll NULL
287 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
288 +
289 +#ifdef CONFIG_RT2X00_LIB_LEDS
290 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
291 + enum led_brightness brightness)
292 +{
293 + struct rt2x00_led *led =
294 + container_of(led_cdev, struct rt2x00_led, led_dev);
295 + unsigned int enabled = brightness != LED_OFF;
296 + unsigned int bg_mode =
297 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
298 + unsigned int polarity =
299 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
300 + EEPROM_FREQ_LED_POLARITY);
301 + unsigned int ledmode =
302 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
303 + EEPROM_FREQ_LED_MODE);
304 +
305 + if (led->type == LED_TYPE_RADIO) {
306 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
307 + enabled ? 0x20 : 0);
308 + } else if (led->type == LED_TYPE_ASSOC) {
309 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
310 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
311 + } else if (led->type == LED_TYPE_QUALITY) {
312 + /*
313 + * The brightness is divided into 6 levels (0 - 5),
314 + * The specs tell us the following levels:
315 + * 0, 1 ,3, 7, 15, 31
316 + * to determine the level in a simple way we can simply
317 + * work with bitshifting:
318 + * (1 << level) - 1
319 + */
320 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
321 + (1 << brightness / (LED_FULL / 6)) - 1,
322 + polarity);
323 + }
324 +}
325 +
326 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
327 + unsigned long *delay_on,
328 + unsigned long *delay_off)
329 +{
330 + struct rt2x00_led *led =
331 + container_of(led_cdev, struct rt2x00_led, led_dev);
332 + u32 reg;
333 +
334 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
335 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
336 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
337 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
338 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
339 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
340 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
341 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
342 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
343 +
344 + return 0;
345 +}
346 +
347 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
348 + struct rt2x00_led *led,
349 + enum led_type type)
350 +{
351 + led->rt2x00dev = rt2x00dev;
352 + led->type = type;
353 + led->led_dev.brightness_set = rt2800pci_brightness_set;
354 + led->led_dev.blink_set = rt2800pci_blink_set;
355 + led->flags = LED_INITIALIZED;
356 +}
357 +#endif /* CONFIG_RT2X00_LIB_LEDS */
358 +
359 +/*
360 + * Configuration handlers.
361 + */
362 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
363 + struct rt2x00lib_crypto *crypto,
364 + struct ieee80211_key_conf *key)
365 +{
366 + u32 offset;
367 + u32 reg;
368 +
369 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
370 +
371 + reg = 0;
372 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
373 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
374 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
375 + crypto->cipher);
376 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
377 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
378 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
379 + rt2x00pci_register_write(rt2x00dev, offset, reg);
380 +}
381 +
382 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
383 + struct rt2x00lib_crypto *crypto,
384 + struct ieee80211_key_conf *key)
385 +{
386 + struct hw_key_entry key_entry;
387 + struct rt2x00_field32 field;
388 + u32 offset;
389 + u32 mask;
390 + u32 reg;
391 +
392 + if (crypto->cmd == SET_KEY) {
393 + memcpy(key_entry.key, crypto->key,
394 + sizeof(key_entry.key));
395 + memcpy(key_entry.tx_mic, crypto->tx_mic,
396 + sizeof(key_entry.tx_mic));
397 + memcpy(key_entry.rx_mic, crypto->rx_mic,
398 + sizeof(key_entry.rx_mic));
399 +
400 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
401 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
402 + &key_entry, sizeof(key_entry));
403 +
404 + /*
405 + * The driver does not support the IV/EIV generation
406 + * in hardware. However it doesn't support the IV/EIV
407 + * inside the ieee80211 frame either, but requires it
408 + * to be provided seperately for the descriptor.
409 + * rt2x00lib will cut the IV/EIV data out of all frames
410 + * given to us by mac80211, but we must tell mac80211
411 + * to generate the IV/EIV data.
412 + */
413 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
414 + }
415 +
416 + /*
417 + * The cipher types are stored over multiple registers
418 + * starting with SHARED_KEY_MODE_BASE each word will have
419 + * 32 bits and contains the cipher types for 2 modes each.
420 + * Using the correct defines correctly will cause overhead,
421 + * so just calculate the correct offset.
422 + */
423 + mask = key->hw_key_idx % 8;
424 + field.bit_offset = (3 * mask);
425 + field.bit_mask = 0x7 << field.bit_offset;
426 +
427 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
428 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
429 + rt2x00_set_field32(&reg, field,
430 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
431 + rt2x00pci_register_write(rt2x00dev, offset, reg);
432 +
433 + /*
434 + * Update WCID information
435 + */
436 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
437 +
438 + return 0;
439 +}
440 +
441 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
442 + struct rt2x00lib_crypto *crypto,
443 + struct ieee80211_key_conf *key)
444 +{
445 + struct hw_key_entry key_entry;
446 + u32 offset;
447 +
448 + /*
449 + * 1 pairwise key is possible per AID, this means that the AID
450 + * equals our hw_key_idx.
451 + */
452 + key->hw_key_idx = crypto->aid;
453 +
454 + if (crypto->cmd == SET_KEY) {
455 + memcpy(key_entry.key, crypto->key,
456 + sizeof(key_entry.key));
457 + memcpy(key_entry.tx_mic, crypto->tx_mic,
458 + sizeof(key_entry.tx_mic));
459 + memcpy(key_entry.rx_mic, crypto->rx_mic,
460 + sizeof(key_entry.rx_mic));
461 +
462 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
463 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
464 + &key_entry, sizeof(key_entry));
465 +
466 + /*
467 + * The driver does not support the IV/EIV generation
468 + * in hardware. However it doesn't support the IV/EIV
469 + * inside the ieee80211 frame either, but requires it
470 + * to be provided seperately for the descriptor.
471 + * rt2x00lib will cut the IV/EIV data out of all frames
472 + * given to us by mac80211, but we must tell mac80211
473 + * to generate the IV/EIV data.
474 + */
475 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
476 + }
477 +
478 + /*
479 + * Update WCID information
480 + */
481 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
482 +
483 + return 0;
484 +}
485 +
486 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
487 + const unsigned int filter_flags)
488 +{
489 + u32 reg;
490 +
491 + /*
492 + * Start configuration steps.
493 + * Note that the version error will always be dropped
494 + * and broadcast frames will always be accepted since
495 + * there is no filter for it at this time.
496 + */
497 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
498 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
499 + !(filter_flags & FIF_FCSFAIL));
500 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
501 + !(filter_flags & FIF_PLCPFAIL));
502 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
503 + !(filter_flags & FIF_PROMISC_IN_BSS));
504 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
505 + !(filter_flags & FIF_OTHER_BSS));
506 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
507 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
508 + !(filter_flags & FIF_ALLMULTI));
509 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
510 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
511 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
512 + !(filter_flags & FIF_CONTROL));
513 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
514 + !(filter_flags & FIF_CONTROL));
515 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
516 + !(filter_flags & FIF_CONTROL));
517 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
518 + !(filter_flags & FIF_CONTROL));
519 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
520 + !(filter_flags & FIF_CONTROL));
521 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
522 + !(filter_flags & FIF_CONTROL));
523 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
524 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
525 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
526 + !(filter_flags & FIF_CONTROL));
527 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
528 +}
529 +
530 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
531 + struct rt2x00_intf *intf,
532 + struct rt2x00intf_conf *conf,
533 + const unsigned int flags)
534 +{
535 + unsigned int beacon_base;
536 + u32 reg;
537 +
538 + if (flags & CONFIG_UPDATE_TYPE) {
539 + /*
540 + * Clear current synchronisation setup.
541 + * For the Beacon base registers we only need to clear
542 + * the first byte since that byte contains the VALID and OWNER
543 + * bits which (when set to 0) will invalidate the entire beacon.
544 + */
545 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
546 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
547 +
548 + /*
549 + * Enable synchronisation.
550 + */
551 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
552 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
553 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
554 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
555 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
556 + }
557 +
558 + if (flags & CONFIG_UPDATE_MAC) {
559 + reg = le32_to_cpu(conf->mac[1]);
560 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
561 + conf->mac[1] = cpu_to_le32(reg);
562 +
563 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
564 + conf->mac, sizeof(conf->mac));
565 + }
566 +
567 + if (flags & CONFIG_UPDATE_BSSID) {
568 + reg = le32_to_cpu(conf->bssid[1]);
569 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
570 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
571 + conf->bssid[1] = cpu_to_le32(reg);
572 +
573 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
574 + conf->bssid, sizeof(conf->bssid));
575 + }
576 +}
577 +
578 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
579 + struct rt2x00lib_erp *erp)
580 +{
581 + u32 reg;
582 +
583 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
584 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
585 + erp->ack_timeout);
586 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
587 +
588 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
589 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
590 + !!erp->short_preamble);
591 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
592 + !!erp->short_preamble);
593 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
594 +
595 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
596 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
597 + erp->cts_protection ? 2 : 0);
598 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
599 +
600 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
601 + erp->basic_rates);
602 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
603 + erp->basic_rates >> 32);
604 +
605 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
606 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
607 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
608 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
609 +
610 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
611 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
612 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
613 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
614 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
615 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
616 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
617 +}
618 +
619 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
620 + struct antenna_setup *ant)
621 +{
622 + u16 eeprom;
623 + u8 r1;
624 + u8 r3;
625 +
626 + /*
627 + * FIXME: Use requested antenna configuration.
628 + */
629 +
630 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
631 +
632 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
633 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
634 +
635 + /*
636 + * Configure the TX antenna.
637 + */
638 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
639 + case 1:
640 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
641 + break;
642 + case 2:
643 + case 3:
644 + /* Do nothing */
645 + break;
646 + }
647 +
648 + /*
649 + * Configure the RX antenna.
650 + */
651 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
652 + case 1:
653 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
654 + break;
655 + case 2:
656 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
657 + break;
658 + case 3:
659 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
660 + break;
661 + }
662 +
663 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
664 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
665 +}
666 +
667 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
668 + struct rt2x00lib_conf *libconf)
669 +{
670 + u16 eeprom;
671 + short lna_gain;
672 +
673 + if (libconf->rf.channel <= 14) {
674 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
676 + } else if (libconf->rf.channel <= 64) {
677 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
678 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
679 + } else if (libconf->rf.channel <= 128) {
680 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
681 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
682 + } else {
683 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
684 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
685 + }
686 +
687 + rt2x00dev->lna_gain = lna_gain;
688 +}
689 +
690 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
691 + struct rf_channel *rf,
692 + struct channel_info *info)
693 +{
694 + u32 reg;
695 + unsigned int tx_pin;
696 + u16 eeprom;
697 +
698 + tx_pin = 0;
699 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
700 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
701 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
702 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
703 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
704 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
705 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
706 +
707 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
708 +
709 + /*
710 + * Determine antenna settings from EEPROM
711 + */
712 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
713 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
714 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
715 + /* Turn off unused PA or LNA when only 1T or 1R */
716 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
717 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
718 + }
719 +
720 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
721 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
722 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
723 + /* Turn off unused PA or LNA when only 1T or 1R */
724 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
725 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
726 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
727 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
728 +
729 + if (rf->channel > 14) {
730 + /*
731 + * When TX power is below 0, we should increase it by 7 to
732 + * make it a positive value (Minumum value is -7).
733 + * However this means that values between 0 and 7 have
734 + * double meaning, and we should set a 7DBm boost flag.
735 + */
736 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
737 + (info->tx_power1 >= 0));
738 +
739 + if (info->tx_power1 < 0)
740 + info->tx_power1 += 7;
741 +
742 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
743 + TXPOWER_A_TO_DEV(info->tx_power1));
744 +
745 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
746 + (info->tx_power2 >= 0));
747 +
748 + if (info->tx_power2 < 0)
749 + info->tx_power2 += 7;
750 +
751 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
752 + TXPOWER_A_TO_DEV(info->tx_power2));
753 +
754 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
755 + } else {
756 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
757 + TXPOWER_G_TO_DEV(info->tx_power1));
758 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
759 + TXPOWER_G_TO_DEV(info->tx_power2));
760 +
761 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
762 + }
763 +
764 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
765 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
766 +
767 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
768 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
769 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
770 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
771 +
772 + udelay(200);
773 +
774 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
775 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
776 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
777 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
778 +
779 + udelay(200);
780 +
781 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
782 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
783 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
784 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
785 +
786 + /*
787 + * Change BBP settings
788 + */
789 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
790 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
791 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
792 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
793 +
794 + if (rf->channel <= 14) {
795 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
796 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
797 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
798 + } else {
799 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
800 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
801 + }
802 +
803 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
804 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
805 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
806 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
807 + } else {
808 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
809 +
810 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
811 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
812 + else
813 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
814 +
815 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
816 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
817 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
818 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
819 + }
820 +
821 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
822 +
823 + msleep(1);
824 +}
825 +
826 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
827 + const int txpower)
828 +{
829 + u32 reg;
830 + u32 value = TXPOWER_G_TO_DEV(txpower);
831 + u8 r1;
832 +
833 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
834 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
835 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
836 +
837 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
840 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
841 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
842 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
843 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
845 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
846 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
847 +
848 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
851 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
852 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
853 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
854 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
856 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
857 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
858 +
859 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
860 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
861 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
862 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
863 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
864 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
865 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
866 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
867 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
868 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
869 +
870 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
871 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
872 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
873 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
874 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
875 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
876 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
877 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
878 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
879 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
880 +
881 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
882 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
883 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
884 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
885 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
886 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
887 +}
888 +
889 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
890 + struct rt2x00lib_conf *libconf)
891 +{
892 + u32 reg;
893 +
894 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
895 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
896 + libconf->conf->short_frame_max_tx_count);
897 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
898 + libconf->conf->long_frame_max_tx_count);
899 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
900 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
901 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
902 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
903 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
904 +}
905 +
906 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
907 + struct rt2x00lib_conf *libconf)
908 +{
909 + u32 reg;
910 +
911 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
912 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
913 + libconf->conf->beacon_int * 16);
914 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
915 +}
916 +
917 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
918 + struct rt2x00lib_conf *libconf,
919 + const unsigned int flags)
920 +{
921 + /* Always recalculate LNA gain before changing configuration */
922 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
923 +
924 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
925 + rt2800pci_config_channel(rt2x00dev, &libconf->rf,
926 + &libconf->channel);
927 + if (flags & IEEE80211_CONF_CHANGE_POWER)
928 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
929 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
930 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
931 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
932 + rt2800pci_config_duration(rt2x00dev, libconf);
933 +}
934 +
935 +/*
936 + * Link tuning
937 + */
938 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
939 + struct link_qual *qual)
940 +{
941 + u32 reg;
942 +
943 + /*
944 + * Update FCS error count from register.
945 + */
946 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
947 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
948 +
949 + /*
950 + * Update False CCA count from register.
951 + */
952 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
953 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
954 +}
955 +
956 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
957 +{
958 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
959 + return 0x2e + rt2x00dev->lna_gain;
960 +
961 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
962 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
963 + else
964 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
965 +}
966 +
967 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
968 + struct link_qual *qual, u8 vgc_level)
969 +{
970 + if (qual->vgc_level != vgc_level) {
971 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
972 + qual->vgc_level = vgc_level;
973 + qual->vgc_level_reg = vgc_level;
974 + }
975 +}
976 +
977 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
978 + struct link_qual *qual)
979 +{
980 + rt2800pci_set_vgc(rt2x00dev, qual,
981 + rt2800pci_get_default_vgc(rt2x00dev));
982 +}
983 +
984 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
985 + struct link_qual *qual, const u32 count)
986 +{
987 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
988 + return;
989 +
990 + /*
991 + * When RSSI is better then -80 increase VGC level with 0x10
992 + */
993 + rt2800pci_set_vgc(rt2x00dev, qual,
994 + rt2800pci_get_default_vgc(rt2x00dev) +
995 + ((qual->rssi > -80) * 0x10));
996 +}
997 +
998 +/*
999 + * Firmware functions
1000 + */
1001 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1002 +{
1003 + return FIRMWARE_RT2860;
1004 +}
1005 +
1006 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1007 +{
1008 + u16 crc;
1009 +
1010 + /*
1011 + * Use the crc ccitt algorithm.
1012 + * This will return the same value as the legacy driver which
1013 + * used bit ordering reversion on the both the firmware bytes
1014 + * before input input as well as on the final output.
1015 + * Obviously using crc ccitt directly is much more efficient.
1016 + * The last 2 bytes in the firmware array are the crc checksum itself,
1017 + * this means that we should never pass those 2 bytes to the crc
1018 + * algorithm.
1019 + */
1020 + crc = crc_ccitt(~0, data, len - 2);
1021 +
1022 + /*
1023 + * There is a small difference between the crc-itu-t + bitrev and
1024 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1025 + * will be swapped, use swab16 to convert the crc to the correct
1026 + * value.
1027 + */
1028 + return swab16(crc);
1029 +}
1030 +
1031 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1032 + const void *data, const size_t len)
1033 +{
1034 + unsigned int i;
1035 + u32 reg;
1036 +
1037 + /*
1038 + * Wait for stable hardware.
1039 + */
1040 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1041 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1042 + if (reg && reg != ~0)
1043 + break;
1044 + msleep(1);
1045 + }
1046 +
1047 + if (i == REGISTER_BUSY_COUNT) {
1048 + ERROR(rt2x00dev, "Unstable hardware.\n");
1049 + return -EBUSY;
1050 + }
1051 +
1052 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1053 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1054 +
1055 + /*
1056 + * Disable DMA, will be reenabled later when enabling
1057 + * the radio.
1058 + */
1059 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1060 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1061 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1062 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1063 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1064 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1065 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1066 +
1067 + /*
1068 + * enable Host program ram write selection
1069 + */
1070 + reg = 0;
1071 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1072 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1073 +
1074 + /*
1075 + * Write firmware to device.
1076 + */
1077 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1078 + data, len);
1079 +
1080 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1081 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1082 +
1083 + /*
1084 + * Wait for device to stabilize.
1085 + */
1086 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1087 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1088 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1089 + break;
1090 + msleep(1);
1091 + }
1092 +
1093 + if (i == REGISTER_BUSY_COUNT) {
1094 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1095 + return -EBUSY;
1096 + }
1097 +
1098 + /*
1099 + * Disable interrupts
1100 + */
1101 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1102 +
1103 + /*
1104 + * Initialize BBP R/W access agent
1105 + */
1106 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1107 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1108 +
1109 + return 0;
1110 +}
1111 +
1112 +/*
1113 + * Initialization functions.
1114 + */
1115 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1116 +{
1117 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1118 + u32 word;
1119 +
1120 + if (entry->queue->qid == QID_RX) {
1121 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1122 +
1123 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1124 + } else {
1125 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1126 +
1127 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1128 + }
1129 +}
1130 +
1131 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1132 +{
1133 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1134 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1135 + u32 word;
1136 +
1137 + if (entry->queue->qid == QID_RX) {
1138 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1139 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1140 + rt2x00_desc_write(entry_priv->desc, 0, word);
1141 +
1142 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1143 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1144 + rt2x00_desc_write(entry_priv->desc, 1, word);
1145 + } else {
1146 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1147 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1148 + rt2x00_desc_write(entry_priv->desc, 1, word);
1149 + }
1150 +}
1151 +
1152 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1153 +{
1154 + struct queue_entry_priv_pci *entry_priv;
1155 + u32 reg;
1156 +
1157 + /*
1158 + * Initialize registers.
1159 + */
1160 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1161 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1162 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1163 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1164 +
1165 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1166 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1167 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1168 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1169 +
1170 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1171 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1172 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1173 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1174 +
1175 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1176 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1177 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1178 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1179 +
1180 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1181 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1182 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1183 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1184 +
1185 + /*
1186 + * Enable global DMA configuration
1187 + */
1188 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1189 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1190 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1191 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1192 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1193 +
1194 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1195 +
1196 + return 0;
1197 +}
1198 +
1199 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1200 +{
1201 + u32 reg;
1202 + unsigned int i;
1203 +
1204 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1205 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1206 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1207 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1208 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1209 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1210 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1211 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1212 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1213 +
1214 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1215 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1216 +
1217 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1218 +
1219 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1220 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1221 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1222 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1223 +
1224 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1225 +
1226 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1227 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1228 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1229 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1230 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1231 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1232 +
1233 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1234 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1235 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1236 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1237 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1238 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1239 +
1240 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1241 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1242 +
1243 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1244 +
1245 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1246 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1247 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1248 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1249 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1250 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1251 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1252 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1253 +
1254 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1255 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1256 +
1257 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1258 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1259 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1260 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1261 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1262 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1263 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1264 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1265 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1266 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1267 +
1268 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1269 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1270 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1271 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1272 +
1273 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1274 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1275 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1276 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1277 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1278 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1279 +
1280 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1281 +
1282 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1283 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1284 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1285 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1286 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1287 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1288 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1289 +
1290 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1291 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1292 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1293 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1294 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1295 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1296 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1297 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1298 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1299 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1300 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1301 +
1302 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1303 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1304 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1305 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1306 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1307 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1308 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1309 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1310 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1311 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1312 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1313 +
1314 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1315 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1316 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1317 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1318 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1319 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1320 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1321 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1322 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1323 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1324 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1325 +
1326 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1327 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1328 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1329 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1330 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1331 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1332 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1333 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1334 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1335 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1336 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1337 +
1338 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1339 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1340 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1341 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1342 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1343 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1344 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1345 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1346 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1347 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1348 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1349 +
1350 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1351 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1352 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1353 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1354 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1355 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1356 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1357 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1358 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1359 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1360 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1361 +
1362 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1363 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1364 +
1365 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1366 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1367 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1368 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1369 +
1370 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1371 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1372 +
1373 + /*
1374 + * ASIC will keep garbage value after boot, clear encryption keys.
1375 + */
1376 + for (i = 0; i < 254; i++) {
1377 + u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1378 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1379 + wcid, sizeof(wcid));
1380 + }
1381 +
1382 + for (i = 0; i < 4; i++)
1383 + rt2x00pci_register_write(rt2x00dev,
1384 + SHARED_KEY_MODE_ENTRY(i), 0);
1385 +
1386 + for (i = 0; i < 256; i++)
1387 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1388 +
1389 + /*
1390 + * Clear all beacons
1391 + * For the Beacon base registers we only need to clear
1392 + * the first byte since that byte contains the VALID and OWNER
1393 + * bits which (when set to 0) will invalidate the entire beacon.
1394 + */
1395 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1396 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1397 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1398 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1399 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1400 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1401 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1402 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1403 +
1404 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1405 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1406 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1407 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1408 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1409 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1410 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1411 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1412 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1413 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1414 +
1415 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1416 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1417 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1418 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1419 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1420 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1421 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1422 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1423 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1424 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1425 +
1426 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1427 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1428 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1429 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1430 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1431 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1432 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1433 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1434 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1435 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1436 +
1437 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1438 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1439 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1440 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1441 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1442 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1443 +
1444 + /*
1445 + * We must clear the error counters.
1446 + * These registers are cleared on read,
1447 + * so we may pass a useless variable to store the value.
1448 + */
1449 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1450 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1451 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1452 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1453 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1454 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1455 +
1456 + return 0;
1457 +}
1458 +
1459 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1460 +{
1461 + unsigned int i;
1462 + u32 reg;
1463 +
1464 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1465 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1466 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1467 + return 0;
1468 +
1469 + udelay(REGISTER_BUSY_DELAY);
1470 + }
1471 +
1472 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1473 + return -EACCES;
1474 +}
1475 +
1476 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1477 +{
1478 + unsigned int i;
1479 + u8 value;
1480 +
1481 + /*
1482 + * BBP was enabled after firmware was loaded,
1483 + * but we need to reactivate it now.
1484 + */
1485 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0x00000000);
1486 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0x00000000);
1487 + msleep(1);
1488 +
1489 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1490 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1491 + if ((value != 0xff) && (value != 0x00))
1492 + return 0;
1493 + udelay(REGISTER_BUSY_DELAY);
1494 + }
1495 +
1496 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1497 + return -EACCES;
1498 +}
1499 +
1500 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1501 +{
1502 + unsigned int i;
1503 + u16 eeprom;
1504 + u8 reg_id;
1505 + u8 value;
1506 +
1507 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1508 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1509 + return -EACCES;
1510 +
1511 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1512 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1513 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1514 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1515 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1516 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1517 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1518 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1519 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1520 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1521 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1522 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1523 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1524 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1525 +
1526 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1527 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1528 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1529 + }
1530 +
1531 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1532 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1533 +
1534 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1535 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1536 +
1537 + if (eeprom != 0xffff && eeprom != 0x0000) {
1538 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1539 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1540 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1541 + }
1542 + }
1543 +
1544 + return 0;
1545 +}
1546 +
1547 +/*
1548 + * Device state switch handlers.
1549 + */
1550 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1551 + enum dev_state state)
1552 +{
1553 + u32 reg;
1554 +
1555 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1556 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1557 + (state == STATE_RADIO_RX_ON) ||
1558 + (state == STATE_RADIO_RX_ON_LINK));
1559 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1560 +}
1561 +
1562 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1563 + enum dev_state state)
1564 +{
1565 + int mask = (state == STATE_RADIO_IRQ_ON);
1566 + u32 reg;
1567 +
1568 + /*
1569 + * When interrupts are being enabled, the interrupt registers
1570 + * should clear the register to assure a clean state.
1571 + */
1572 + if (state == STATE_RADIO_IRQ_ON) {
1573 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1574 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1575 + }
1576 +
1577 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1578 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1579 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1580 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1581 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1582 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1583 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1584 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1585 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1586 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1587 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1588 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1589 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1590 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1591 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1592 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1593 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1594 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1595 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1596 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1597 +}
1598 +
1599 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1600 +{
1601 + unsigned int i;
1602 + u32 reg;
1603 +
1604 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1605 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1606 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1607 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1608 + return 0;
1609 +
1610 + msleep(1);
1611 + }
1612 +
1613 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1614 + return -EACCES;
1615 +}
1616 +
1617 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1618 +{
1619 + u32 reg;
1620 + u16 word;
1621 +
1622 + /*
1623 + * Initialize all registers.
1624 + */
1625 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1626 + rt2800pci_init_queues(rt2x00dev) ||
1627 + rt2800pci_init_registers(rt2x00dev) ||
1628 + rt2800pci_init_bbp(rt2x00dev)))
1629 + return -EIO;
1630 +
1631 + /*
1632 + * Send signal to firmware during boot time.
1633 + */
1634 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1635 +
1636 + /* Wait for DMA, ignore error */
1637 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1638 +
1639 + /*
1640 + * Enable RX.
1641 + */
1642 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1643 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1644 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1645 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1646 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1647 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1648 +
1649 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1650 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1651 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1652 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1653 +
1654 + /*
1655 + * Initialize LED control
1656 + */
1657 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1658 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1659 + word & 0xff, (word >> 8) & 0xff);
1660 +
1661 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1662 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1663 + word & 0xff, (word >> 8) & 0xff);
1664 +
1665 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1666 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1667 + word & 0xff, (word >> 8) & 0xff);
1668 +
1669 + return 0;
1670 +}
1671 +
1672 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1673 +{
1674 + u32 reg;
1675 +
1676 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1677 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1678 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1679 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1680 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1681 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1682 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1683 +
1684 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1685 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1686 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1687 +
1688 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1689 +
1690 + /* Wait for DMA, ignore error */
1691 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1692 +}
1693 +
1694 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1695 + enum dev_state state)
1696 +{
1697 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1698 +
1699 + if (state == STATE_AWAKE)
1700 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1701 + else
1702 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1703 +
1704 + return 0;
1705 +}
1706 +
1707 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1708 + enum dev_state state)
1709 +{
1710 + int retval = 0;
1711 +
1712 + switch (state) {
1713 + case STATE_RADIO_ON:
1714 + /*
1715 + * Before the radio can be enabled, the device first has
1716 + * to be woken up. After that it needs a bit of time
1717 + * to be fully awake and the radio can be enabled.
1718 + */
1719 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1720 + msleep(1);
1721 + retval = rt2800pci_enable_radio(rt2x00dev);
1722 + break;
1723 + case STATE_RADIO_OFF:
1724 + /*
1725 + * After the radio has been disablee, the device should
1726 + * be put to sleep for powersaving.
1727 + */
1728 + rt2800pci_disable_radio(rt2x00dev);
1729 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1730 + break;
1731 + case STATE_RADIO_RX_ON:
1732 + case STATE_RADIO_RX_ON_LINK:
1733 + case STATE_RADIO_RX_OFF:
1734 + case STATE_RADIO_RX_OFF_LINK:
1735 + rt2800pci_toggle_rx(rt2x00dev, state);
1736 + break;
1737 + case STATE_RADIO_IRQ_ON:
1738 + case STATE_RADIO_IRQ_OFF:
1739 + rt2800pci_toggle_irq(rt2x00dev, state);
1740 + break;
1741 + case STATE_DEEP_SLEEP:
1742 + case STATE_SLEEP:
1743 + case STATE_STANDBY:
1744 + case STATE_AWAKE:
1745 + retval = rt2800pci_set_state(rt2x00dev, state);
1746 + break;
1747 + default:
1748 + retval = -ENOTSUPP;
1749 + break;
1750 + }
1751 +
1752 + if (unlikely(retval))
1753 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1754 + state, retval);
1755 +
1756 + return retval;
1757 +}
1758 +
1759 +/*
1760 + * TX descriptor initialization
1761 + */
1762 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1763 + struct sk_buff *skb,
1764 + struct txentry_desc *txdesc)
1765 +{
1766 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1767 + __le32 *txd = skbdesc->desc;
1768 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1769 + u32 word;
1770 +
1771 + /*
1772 + * Initialize TX Info descriptor
1773 + */
1774 + rt2x00_desc_read(txwi, 0, &word);
1775 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1776 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1777 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1778 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1779 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1780 + rt2x00_set_field32(&word, TXWI_W0_TS,
1781 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1782 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1783 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1784 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1785 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1786 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1787 + rt2x00_set_field32(&word, TXWI_W0_BW,
1788 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1789 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1790 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1791 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1792 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1793 + rt2x00_desc_write(txwi, 0, word);
1794 +
1795 + rt2x00_desc_read(txwi, 1, &word);
1796 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1797 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1798 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1799 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1800 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1801 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1802 + skbdesc->entry->entry_idx);
1803 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1804 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1805 + skbdesc->entry->queue->qid);
1806 + rt2x00_desc_write(txwi, 1, word);
1807 +
1808 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1809 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1810 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1811 + }
1812 +
1813 + /*
1814 + * Initialize TX descriptor
1815 + */
1816 + rt2x00_desc_read(txd, 0, &word);
1817 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1818 + rt2x00_desc_write(txd, 0, word);
1819 +
1820 + rt2x00_desc_read(txd, 1, &word);
1821 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1822 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1823 + rt2x00_set_field32(&word, TXD_W1_BURST,
1824 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1825 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1826 + rt2x00dev->hw->extra_tx_headroom);
1827 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1828 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1829 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1830 + rt2x00_desc_write(txd, 1, word);
1831 +
1832 + rt2x00_desc_read(txd, 2, &word);
1833 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1834 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1835 + rt2x00_desc_write(txd, 2, word);
1836 +
1837 + rt2x00_desc_read(txd, 3, &word);
1838 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1839 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1840 + rt2x00_desc_write(txd, 3, word);
1841 +}
1842 +
1843 +/*
1844 + * TX data initialization
1845 + */
1846 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1847 +{
1848 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1849 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1850 + unsigned int beacon_base;
1851 + u32 reg;
1852 +
1853 + /*
1854 + * Disable beaconing while we are reloading the beacon data,
1855 + * otherwise we might be sending out invalid data.
1856 + */
1857 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1858 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1859 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1860 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1861 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1862 +
1863 + /*
1864 + * Write entire beacon with descriptor to register.
1865 + */
1866 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1867 + rt2x00pci_register_multiwrite(rt2x00dev,
1868 + beacon_base,
1869 + skbdesc->desc, skbdesc->desc_len);
1870 + rt2x00pci_register_multiwrite(rt2x00dev,
1871 + beacon_base + skbdesc->desc_len,
1872 + entry->skb->data, entry->skb->len);
1873 +
1874 + /*
1875 + * Clean up beacon skb.
1876 + */
1877 + dev_kfree_skb_any(entry->skb);
1878 + entry->skb = NULL;
1879 +}
1880 +
1881 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1882 + const enum data_queue_qid queue_idx)
1883 +{
1884 + struct data_queue *queue;
1885 + unsigned int idx, qidx = 0;
1886 + u32 reg;
1887 +
1888 + if (queue_idx == QID_BEACON) {
1889 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1890 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1891 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1892 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1893 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1894 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1895 + }
1896 + return;
1897 + }
1898 +
1899 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1900 + return;
1901 +
1902 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1903 + idx = queue->index[Q_INDEX];
1904 +
1905 + if (queue_idx == QID_MGMT)
1906 + qidx = 5;
1907 + else
1908 + qidx = queue_idx;
1909 +
1910 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1911 +}
1912 +
1913 +/*
1914 + * RX control handlers
1915 + */
1916 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1917 + struct rxdone_entry_desc *rxdesc)
1918 +{
1919 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1920 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1921 + __le32 *rxd = entry_priv->desc;
1922 + __le32 *rxwi = (__le32 *)entry->skb->data;
1923 + u32 rxd3;
1924 + u32 rxwi0;
1925 + u32 rxwi1;
1926 + u32 rxwi2;
1927 + u32 rxwi3;
1928 +
1929 + rt2x00_desc_read(rxd, 3, &rxd3);
1930 + rt2x00_desc_read(rxwi, 0, &rxwi0);
1931 + rt2x00_desc_read(rxwi, 1, &rxwi1);
1932 + rt2x00_desc_read(rxwi, 2, &rxwi2);
1933 + rt2x00_desc_read(rxwi, 3, &rxwi3);
1934 +
1935 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1936 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1937 +
1938 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1939 + /*
1940 + * Unfortunately we don't know the cipher type used during
1941 + * decryption. This prevents us from correct providing
1942 + * correct statistics through debugfs.
1943 + */
1944 + rxdesc->cipher = CIPHER_NONE;
1945 + rxdesc->cipher_status =
1946 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1947 + }
1948 +
1949 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
1950 + /*
1951 + * Hardware has stripped IV/EIV data from 802.11 frame during
1952 + * decryption. Unfortunately the descriptor doesn't contain
1953 + * any fields with the EIV/IV data either, so they can't
1954 + * be restored by rt2x00lib.
1955 + */
1956 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1957 +
1958 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1959 + rxdesc->flags |= RX_FLAG_DECRYPTED;
1960 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1961 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1962 + }
1963 +
1964 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
1965 + rxdesc->dev_flags |= RXDONE_MY_BSS;
1966 +
1967 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
1968 + rxdesc->flags |= RX_FLAG_SHORT_GI;
1969 +
1970 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
1971 + rxdesc->flags |= RX_FLAG_40MHZ;
1972 +
1973 + /*
1974 + * Detect RX rate, always use MCS as signal type.
1975 + */
1976 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
1977 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
1978 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1979 +
1980 + /*
1981 + * Mask of 0x8 bit to remove the short preamble flag.
1982 + */
1983 + if (rxdesc->dev_flags == RATE_MODE_CCK)
1984 + rxdesc->signal &= ~0x8;
1985 +
1986 + rxdesc->rssi =
1987 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1988 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1989 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1990 +
1991 + rxdesc->noise =
1992 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1993 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1994 +
1995 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1996 +
1997 + /*
1998 + * Remove TXWI descriptor from start of buffer.
1999 + */
2000 + skb_pull(entry->skb, TXWI_DESC_SIZE);
2001 + skb_trim(entry->skb, rxdesc->size);
2002 +}
2003 +
2004 +/*
2005 + * Interrupt functions.
2006 + */
2007 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2008 +{
2009 + struct data_queue *queue;
2010 + struct queue_entry *entry;
2011 + struct queue_entry *entry_done;
2012 + struct queue_entry_priv_pci *entry_priv;
2013 + struct txdone_entry_desc txdesc;
2014 + u32 word;
2015 + u32 reg;
2016 + u32 old_reg;
2017 + int type;
2018 + int index;
2019 +
2020 + /*
2021 + * During each loop we will compare the freshly read
2022 + * TX_STA_FIFO register value with the value read from
2023 + * the previous loop. If the 2 values are equal then
2024 + * we should stop processing because the chance it
2025 + * quite big that the device has been unplugged and
2026 + * we risk going into an endless loop.
2027 + */
2028 + old_reg = 0;
2029 +
2030 + while (1) {
2031 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2032 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2033 + break;
2034 +
2035 + if (old_reg == reg)
2036 + break;
2037 + old_reg = reg;
2038 +
2039 + /*
2040 + * Skip this entry when it contains an invalid
2041 + * queue identication number.
2042 + */
2043 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2044 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2045 + if (unlikely(!queue))
2046 + continue;
2047 +
2048 + /*
2049 + * Skip this entry when it contains an invalid
2050 + * index number.
2051 + */
2052 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2053 + if (unlikely(index >= queue->limit))
2054 + continue;
2055 +
2056 + entry = &queue->entries[index];
2057 + entry_priv = entry->priv_data;
2058 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2059 +
2060 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2061 + while (entry != entry_done) {
2062 + /*
2063 + * Catch up.
2064 + * Just report any entries we missed as failed.
2065 + */
2066 + WARNING(rt2x00dev,
2067 + "TX status report missed for entry %d\n",
2068 + entry_done->entry_idx);
2069 +
2070 + txdesc.flags = 0;
2071 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2072 + txdesc.retry = 0;
2073 +
2074 + rt2x00lib_txdone(entry_done, &txdesc);
2075 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2076 + }
2077 +
2078 + /*
2079 + * Obtain the status about this packet.
2080 + */
2081 + txdesc.flags = 0;
2082 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2083 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2084 + else
2085 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2086 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2087 +
2088 + rt2x00lib_txdone(entry, &txdesc);
2089 + }
2090 +}
2091 +
2092 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2093 +{
2094 + struct rt2x00_dev *rt2x00dev = dev_instance;
2095 + u32 reg;
2096 +
2097 + /* Read status and ACK all interrupts */
2098 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2099 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2100 +
2101 + if (!reg)
2102 + return IRQ_NONE;
2103 +
2104 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2105 + return IRQ_HANDLED;
2106 +
2107 + /*
2108 + * 1 - Rx ring done interrupt.
2109 + */
2110 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2111 + rt2x00pci_rxdone(rt2x00dev);
2112 +
2113 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2114 + rt2800pci_txdone(rt2x00dev);
2115 +
2116 + return IRQ_HANDLED;
2117 +}
2118 +
2119 +/*
2120 + * Device probe functions.
2121 + */
2122 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2123 +{
2124 + struct eeprom_93cx6 eeprom;
2125 + u32 reg;
2126 + u16 word;
2127 + u8 *mac;
2128 + u8 default_lna_gain;
2129 +
2130 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2131 +
2132 + eeprom.data = rt2x00dev;
2133 + eeprom.register_read = rt2800pci_eepromregister_read;
2134 + eeprom.register_write = rt2800pci_eepromregister_write;
2135 + eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2136 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2137 + eeprom.reg_data_in = 0;
2138 + eeprom.reg_data_out = 0;
2139 + eeprom.reg_data_clock = 0;
2140 + eeprom.reg_chip_select = 0;
2141 +
2142 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2143 + EEPROM_SIZE / sizeof(u16));
2144 +
2145 + /*
2146 + * Start validation of the data that has been read.
2147 + */
2148 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2149 + if (!is_valid_ether_addr(mac)) {
2150 + DECLARE_MAC_BUF(macbuf);
2151 +
2152 + random_ether_addr(mac);
2153 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2154 + }
2155 +
2156 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2157 + if (word == 0xffff) {
2158 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2159 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2160 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2161 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2162 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2163 + }
2164 +
2165 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2166 + if (word != 0) {
2167 + /* NIC configuration must always be 0. */
2168 + word = 0;
2169 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2170 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2171 + }
2172 +
2173 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2174 + if ((word & 0x00ff) == 0x00ff) {
2175 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2176 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2177 + LED_MODE_TXRX_ACTIVITY);
2178 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2179 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2180 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2181 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2182 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2183 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2184 + }
2185 +
2186 + /*
2187 + * During the LNA validation we are going to use
2188 + * lna0 as correct value. Note that EEPROM_LNA
2189 + * is never validated.
2190 + */
2191 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2192 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2193 +
2194 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2195 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2196 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2197 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2198 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2199 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2200 +
2201 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2202 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2203 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2204 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2205 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2206 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2207 + default_lna_gain);
2208 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2209 +
2210 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2211 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2212 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2213 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2214 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2215 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2216 +
2217 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2218 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2219 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2220 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2221 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2222 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2223 + default_lna_gain);
2224 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2225 +
2226 + return 0;
2227 +}
2228 +
2229 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2230 +{
2231 + u32 reg;
2232 + u16 value;
2233 + u16 eeprom;
2234 + u16 device;
2235 +
2236 + /*
2237 + * Read EEPROM word for configuration.
2238 + */
2239 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2240 +
2241 + /*
2242 + * Identify RF chipset.
2243 + * To determine the RT chip we have to read the
2244 + * PCI header of the device.
2245 + */
2246 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2247 + PCI_CONFIG_HEADER_DEVICE, &device);
2248 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2249 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2250 + reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2251 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2252 +
2253 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2254 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2255 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2256 + !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2257 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2258 + return -ENODEV;
2259 + }
2260 +
2261 + /*
2262 + * Read frequency offset and RF programming sequence.
2263 + */
2264 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2265 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2266 +
2267 + /*
2268 + * Read external LNA informations.
2269 + */
2270 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2271 +
2272 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2273 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2274 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2275 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2276 +
2277 + /*
2278 + * Detect if this device has an hardware controlled radio.
2279 + */
2280 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2281 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2282 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2283 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2284 +
2285 + /*
2286 + * Store led settings, for correct led behaviour.
2287 + */
2288 +#ifdef CONFIG_RT2X00_LIB_LEDS
2289 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2290 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2291 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2292 +
2293 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2294 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2295 +
2296 + return 0;
2297 +}
2298 +
2299 +/*
2300 + * RF value list for rt2860
2301 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2302 + */
2303 +static const struct rf_channel rf_vals[] = {
2304 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2305 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2306 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2307 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2308 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2309 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2310 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2311 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2312 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2313 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2314 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2315 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2316 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2317 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2318 +
2319 + /* 802.11 UNI / HyperLan 2 */
2320 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2321 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2322 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2323 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2324 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2325 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2326 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2327 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2328 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2329 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2330 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2331 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2332 +
2333 + /* 802.11 HyperLan 2 */
2334 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2335 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2336 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2337 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2338 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2339 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2340 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2341 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2342 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2343 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2344 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2345 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2346 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2347 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2348 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2349 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2350 +
2351 + /* 802.11 UNII */
2352 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2353 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2354 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2355 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2356 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2357 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2358 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2359 +
2360 + /* 802.11 Japan */
2361 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2362 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2363 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2364 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2365 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2366 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2367 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2368 +};
2369 +
2370 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2371 +{
2372 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2373 + struct channel_info *info;
2374 + char *tx_power1;
2375 + char *tx_power2;
2376 + unsigned int i;
2377 +
2378 + /*
2379 + * Initialize all hw fields.
2380 + */
2381 + rt2x00dev->hw->flags =
2382 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2383 + IEEE80211_HW_SIGNAL_DBM;
2384 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2385 +
2386 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2387 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2388 + rt2x00_eeprom_addr(rt2x00dev,
2389 + EEPROM_MAC_ADDR_0));
2390 +
2391 + /*
2392 + * Initialize hw_mode information.
2393 + */
2394 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2395 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2396 +
2397 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2398 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2399 + spec->num_channels = 14;
2400 + spec->channels = rf_vals;
2401 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2402 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2403 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2404 + spec->num_channels = ARRAY_SIZE(rf_vals);
2405 + spec->channels = rf_vals;
2406 + }
2407 +
2408 + /*
2409 + * Initialize HT information.
2410 + */
2411 + spec->ht.ht_supported = true;
2412 + spec->ht.cap =
2413 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2414 + IEEE80211_HT_CAP_GRN_FLD |
2415 + IEEE80211_HT_CAP_SGI_20 |
2416 + IEEE80211_HT_CAP_SGI_40 |
2417 + IEEE80211_HT_CAP_TX_STBC |
2418 + IEEE80211_HT_CAP_RX_STBC |
2419 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2420 + spec->ht.ampdu_factor = 3;
2421 + spec->ht.ampdu_density = 4;
2422 + spec->ht.mcs.rx_mask[0] = 0xff;
2423 + spec->ht.mcs.rx_mask[1] = 0xff;
2424 + spec->ht.mcs.tx_params =
2425 + IEEE80211_HT_MCS_TX_DEFINED;
2426 +
2427 + /*
2428 + * Create channel information array
2429 + */
2430 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2431 + if (!info)
2432 + return -ENOMEM;
2433 +
2434 + spec->channels_info = info;
2435 +
2436 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2437 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2438 +
2439 + for (i = 0; i < 14; i++) {
2440 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2441 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2442 + }
2443 +
2444 + if (spec->num_channels > 14) {
2445 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2446 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2447 +
2448 + for (i = 14; i < spec->num_channels; i++) {
2449 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2450 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2451 + }
2452 + }
2453 +
2454 + return 0;
2455 +}
2456 +
2457 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2458 +{
2459 + int retval;
2460 +
2461 + /*
2462 + * Allocate eeprom data.
2463 + */
2464 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2465 + if (retval)
2466 + return retval;
2467 +
2468 + retval = rt2800pci_init_eeprom(rt2x00dev);
2469 + if (retval)
2470 + return retval;
2471 +
2472 + /*
2473 + * Initialize hw specifications.
2474 + */
2475 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2476 + if (retval)
2477 + return retval;
2478 +
2479 + /*
2480 + * This device requires firmware.
2481 + */
2482 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2483 + if (!modparam_nohwcrypt)
2484 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2485 +
2486 + /*
2487 + * Set the rssi offset.
2488 + */
2489 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2490 +
2491 + return 0;
2492 +}
2493 +
2494 +/*
2495 + * IEEE80211 stack callback functions.
2496 + */
2497 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2498 +{
2499 + struct rt2x00_dev *rt2x00dev = hw->priv;
2500 + u32 reg;
2501 +
2502 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2503 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2504 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2505 +
2506 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2507 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2508 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2509 +
2510 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2511 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2512 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2513 +
2514 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2515 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2516 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2517 +
2518 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2519 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2520 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2521 +
2522 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2523 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2524 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2525 +
2526 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2527 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2528 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2529 +
2530 + return 0;
2531 +}
2532 +
2533 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2534 + const struct ieee80211_tx_queue_params *params)
2535 +{
2536 + struct rt2x00_dev *rt2x00dev = hw->priv;
2537 + struct data_queue *queue;
2538 + struct rt2x00_field32 field;
2539 + int retval;
2540 + u32 reg;
2541 + u32 offset;
2542 +
2543 + /*
2544 + * First pass the configuration through rt2x00lib, that will
2545 + * update the queue settings and validate the input. After that
2546 + * we are free to update the registers based on the value
2547 + * in the queue parameter.
2548 + */
2549 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2550 + if (retval)
2551 + return retval;
2552 +
2553 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2554 +
2555 + /* Update WMM TXOP register */
2556 + if (queue_idx < 2) {
2557 + field.bit_offset = queue_idx * 16;
2558 + field.bit_mask = 0xffff << field.bit_offset;
2559 +
2560 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2561 + rt2x00_set_field32(&reg, field, queue->txop);
2562 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2563 + } else if (queue_idx < 4) {
2564 + field.bit_offset = (queue_idx - 2) * 16;
2565 + field.bit_mask = 0xffff << field.bit_offset;
2566 +
2567 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2568 + rt2x00_set_field32(&reg, field, queue->txop);
2569 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2570 + }
2571 +
2572 + /* Update WMM registers */
2573 + field.bit_offset = queue_idx * 4;
2574 + field.bit_mask = 0xf << field.bit_offset;
2575 +
2576 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2577 + rt2x00_set_field32(&reg, field, queue->aifs);
2578 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2579 +
2580 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2581 + rt2x00_set_field32(&reg, field, queue->cw_min);
2582 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2583 +
2584 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2585 + rt2x00_set_field32(&reg, field, queue->cw_max);
2586 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2587 +
2588 + /* Update EDCA registers */
2589 + if (queue_idx < 4) {
2590 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2591 +
2592 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2593 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2594 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2595 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2596 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2597 + }
2598 +
2599 + return 0;
2600 +}
2601 +
2602 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2603 +{
2604 + struct rt2x00_dev *rt2x00dev = hw->priv;
2605 + u64 tsf;
2606 + u32 reg;
2607 +
2608 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2609 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2610 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2611 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2612 +
2613 + return tsf;
2614 +}
2615 +
2616 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2617 + .tx = rt2x00mac_tx,
2618 + .start = rt2x00mac_start,
2619 + .stop = rt2x00mac_stop,
2620 + .add_interface = rt2x00mac_add_interface,
2621 + .remove_interface = rt2x00mac_remove_interface,
2622 + .config = rt2x00mac_config,
2623 + .config_interface = rt2x00mac_config_interface,
2624 + .configure_filter = rt2x00mac_configure_filter,
2625 + .set_key = rt2x00mac_set_key,
2626 + .get_stats = rt2x00mac_get_stats,
2627 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2628 + .bss_info_changed = rt2x00mac_bss_info_changed,
2629 + .conf_tx = rt2800pci_conf_tx,
2630 + .get_tx_stats = rt2x00mac_get_tx_stats,
2631 + .get_tsf = rt2800pci_get_tsf,
2632 +};
2633 +
2634 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2635 + .irq_handler = rt2800pci_interrupt,
2636 + .probe_hw = rt2800pci_probe_hw,
2637 + .get_firmware_name = rt2800pci_get_firmware_name,
2638 + .get_firmware_crc = rt2800pci_get_firmware_crc,
2639 + .load_firmware = rt2800pci_load_firmware,
2640 + .initialize = rt2x00pci_initialize,
2641 + .uninitialize = rt2x00pci_uninitialize,
2642 + .get_entry_state = rt2800pci_get_entry_state,
2643 + .clear_entry = rt2800pci_clear_entry,
2644 + .set_device_state = rt2800pci_set_device_state,
2645 + .rfkill_poll = rt2800pci_rfkill_poll,
2646 + .link_stats = rt2800pci_link_stats,
2647 + .reset_tuner = rt2800pci_reset_tuner,
2648 + .link_tuner = rt2800pci_link_tuner,
2649 + .write_tx_desc = rt2800pci_write_tx_desc,
2650 + .write_tx_data = rt2x00pci_write_tx_data,
2651 + .write_beacon = rt2800pci_write_beacon,
2652 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2653 + .fill_rxdone = rt2800pci_fill_rxdone,
2654 + .config_shared_key = rt2800pci_config_shared_key,
2655 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2656 + .config_filter = rt2800pci_config_filter,
2657 + .config_intf = rt2800pci_config_intf,
2658 + .config_erp = rt2800pci_config_erp,
2659 + .config_ant = rt2800pci_config_ant,
2660 + .config = rt2800pci_config,
2661 +};
2662 +
2663 +static const struct data_queue_desc rt2800pci_queue_rx = {
2664 + .entry_num = RX_ENTRIES,
2665 + .data_size = DATA_FRAME_SIZE,
2666 + .desc_size = RXD_DESC_SIZE,
2667 + .priv_size = sizeof(struct queue_entry_priv_pci),
2668 +};
2669 +
2670 +static const struct data_queue_desc rt2800pci_queue_tx = {
2671 + .entry_num = TX_ENTRIES,
2672 + .data_size = DATA_FRAME_SIZE,
2673 + .desc_size = TXD_DESC_SIZE,
2674 + .priv_size = sizeof(struct queue_entry_priv_pci),
2675 +};
2676 +
2677 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2678 + .entry_num = 8 * BEACON_ENTRIES,
2679 + .data_size = 0, /* No DMA required for beacons */
2680 + .desc_size = TXWI_DESC_SIZE,
2681 + .priv_size = sizeof(struct queue_entry_priv_pci),
2682 +};
2683 +
2684 +static const struct rt2x00_ops rt2800pci_ops = {
2685 + .name = KBUILD_MODNAME,
2686 + .max_sta_intf = 1,
2687 + .max_ap_intf = 8,
2688 + .eeprom_size = EEPROM_SIZE,
2689 + .rf_size = RF_SIZE,
2690 + .tx_queues = NUM_TX_QUEUES,
2691 + .rx = &rt2800pci_queue_rx,
2692 + .tx = &rt2800pci_queue_tx,
2693 + .bcn = &rt2800pci_queue_bcn,
2694 + .lib = &rt2800pci_rt2x00_ops,
2695 + .hw = &rt2800pci_mac80211_ops,
2696 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2697 + .debugfs = &rt2800pci_rt2x00debug,
2698 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2699 +};
2700 +
2701 +/*
2702 + * RT2800pci module information.
2703 + */
2704 +static struct pci_device_id rt2800pci_device_table[] = {
2705 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2706 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2707 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2708 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2709 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2710 + { 0, }
2711 +};
2712 +
2713 +MODULE_AUTHOR(DRV_PROJECT);
2714 +MODULE_VERSION(DRV_VERSION);
2715 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2716 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2717 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2718 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2719 +MODULE_LICENSE("GPL");
2720 +
2721 +static struct pci_driver rt2800pci_driver = {
2722 + .name = KBUILD_MODNAME,
2723 + .id_table = rt2800pci_device_table,
2724 + .probe = rt2x00pci_probe,
2725 + .remove = __devexit_p(rt2x00pci_remove),
2726 + .suspend = rt2x00pci_suspend,
2727 + .resume = rt2x00pci_resume,
2728 +};
2729 +
2730 +static int __init rt2800pci_init(void)
2731 +{
2732 + return pci_register_driver(&rt2800pci_driver);
2733 +}
2734 +
2735 +static void __exit rt2800pci_exit(void)
2736 +{
2737 + pci_unregister_driver(&rt2800pci_driver);
2738 +}
2739 +
2740 +module_init(rt2800pci_init);
2741 +module_exit(rt2800pci_exit);
2742 --- /dev/null
2743 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2744 @@ -0,0 +1,1879 @@
2745 +/*
2746 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2747 + <http://rt2x00.serialmonkey.com>
2748 +
2749 + This program is free software; you can redistribute it and/or modify
2750 + it under the terms of the GNU General Public License as published by
2751 + the Free Software Foundation; either version 2 of the License, or
2752 + (at your option) any later version.
2753 +
2754 + This program is distributed in the hope that it will be useful,
2755 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2756 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2757 + GNU General Public License for more details.
2758 +
2759 + You should have received a copy of the GNU General Public License
2760 + along with this program; if not, write to the
2761 + Free Software Foundation, Inc.,
2762 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2763 + */
2764 +
2765 +/*
2766 + Module: rt2800pci
2767 + Abstract: Data structures and registers for the rt2800pci module.
2768 + Supported chipsets: RT2800E & RT2800ED.
2769 + */
2770 +
2771 +#ifndef RT2800PCI_H
2772 +#define RT2800PCI_H
2773 +
2774 +/*
2775 + * RF chip defines.
2776 + *
2777 + * RF2820 2.4G 2T3R
2778 + * RF2850 2.4G/5G 2T3R
2779 + * RF2720 2.4G 1T2R
2780 + * RF2750 2.4G/5G 1T2R
2781 + * RF3020 2.4G 1T1R
2782 + * RF2020 2.4G B/G
2783 + */
2784 +#define RF2820 0x0001
2785 +#define RF2850 0x0002
2786 +#define RF2720 0x0003
2787 +#define RF2750 0x0004
2788 +#define RF3020 0x0005
2789 +#define RF2020 0x0006
2790 +
2791 +/*
2792 + * RT2860 version
2793 + */
2794 +#define RT2860_VERSION_C 0x0100
2795 +#define RT2860_VERSION_D 0x0101
2796 +#define RT2860_VERSION_E 0x0200
2797 +
2798 +/*
2799 + * Signal information.
2800 + * Defaul offset is required for RSSI <-> dBm conversion.
2801 + */
2802 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2803 +
2804 +/*
2805 + * Register layout information.
2806 + */
2807 +#define CSR_REG_BASE 0x1000
2808 +#define CSR_REG_SIZE 0x0800
2809 +#define EEPROM_BASE 0x0000
2810 +#define EEPROM_SIZE 0x0110
2811 +#define BBP_BASE 0x0000
2812 +#define BBP_SIZE 0x0080
2813 +#define RF_BASE 0x0000
2814 +#define RF_SIZE 0x0014
2815 +
2816 +/*
2817 + * Number of TX queues.
2818 + */
2819 +#define NUM_TX_QUEUES 4
2820 +
2821 +/*
2822 + * PCI registers.
2823 + */
2824 +
2825 +/*
2826 + * PCI Configuration Header
2827 + */
2828 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2829 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2830 +
2831 +/*
2832 + * E2PROM_CSR: EEPROM control register.
2833 + * RELOAD: Write 1 to reload eeprom content.
2834 + * TYPE_93C46: 1: 93c46, 0:93c66.
2835 + * LOAD_STATUS: 1:loading, 0:done.
2836 + */
2837 +#define E2PROM_CSR 0x0004
2838 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
2839 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
2840 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
2841 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
2842 +#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
2843 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2844 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
2845 +
2846 +/*
2847 + * HOST-MCU shared memory
2848 + */
2849 +#define HOST_CMD_CSR 0x0404
2850 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2851 +
2852 +/*
2853 + * INT_SOURCE_CSR: Interrupt source register.
2854 + * Write one to clear corresponding bit.
2855 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2856 + */
2857 +#define INT_SOURCE_CSR 0x0200
2858 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2859 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2860 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2861 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2862 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2863 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2864 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2865 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2866 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2867 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2868 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2869 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2870 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2871 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2872 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2873 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2874 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2875 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2876 +
2877 +/*
2878 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2879 + */
2880 +#define INT_MASK_CSR 0x0204
2881 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2882 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2883 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2884 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2885 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2886 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2887 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2888 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2889 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2890 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2891 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
2892 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
2893 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
2894 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2895 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2896 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
2897 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
2898 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
2899 +
2900 +/*
2901 + * WPDMA_GLO_CFG
2902 + */
2903 +#define WPDMA_GLO_CFG 0x0208
2904 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2905 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2906 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2907 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2908 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2909 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2910 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2911 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2912 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2913 +
2914 +/*
2915 + * WPDMA_RST_IDX
2916 + */
2917 +#define WPDMA_RST_IDX 0x020c
2918 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2919 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2920 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2921 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2922 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2923 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2924 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2925 +
2926 +/*
2927 + * DELAY_INT_CFG
2928 + */
2929 +#define DELAY_INT_CFG 0x0210
2930 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2931 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2932 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2933 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2934 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2935 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2936 +
2937 +/*
2938 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2939 + * AIFSN0: AC_BE
2940 + * AIFSN1: AC_BK
2941 + * AIFSN1: AC_VI
2942 + * AIFSN1: AC_VO
2943 + */
2944 +#define WMM_AIFSN_CFG 0x0214
2945 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
2946 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
2947 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
2948 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
2949 +
2950 +/*
2951 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2952 + * CWMIN0: AC_BE
2953 + * CWMIN1: AC_BK
2954 + * CWMIN1: AC_VI
2955 + * CWMIN1: AC_VO
2956 + */
2957 +#define WMM_CWMIN_CFG 0x0218
2958 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
2959 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
2960 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
2961 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
2962 +
2963 +/*
2964 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2965 + * CWMAX0: AC_BE
2966 + * CWMAX1: AC_BK
2967 + * CWMAX1: AC_VI
2968 + * CWMAX1: AC_VO
2969 + */
2970 +#define WMM_CWMAX_CFG 0x021c
2971 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
2972 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
2973 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
2974 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
2975 +
2976 +/*
2977 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2978 + * AC0TXOP: AC_BK in unit of 32us
2979 + * AC1TXOP: AC_BE in unit of 32us
2980 + */
2981 +#define WMM_TXOP0_CFG 0x0220
2982 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
2983 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
2984 +
2985 +/*
2986 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2987 + * AC2TXOP: AC_VI in unit of 32us
2988 + * AC3TXOP: AC_VO in unit of 32us
2989 + */
2990 +#define WMM_TXOP1_CFG 0x0224
2991 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
2992 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
2993 +
2994 +/*
2995 + * RINGREG_DIFF
2996 + */
2997 +#define RINGREG_DIFF 0x0010
2998 +
2999 +/*
3000 + * GPIO_CTRL_CFG:
3001 + */
3002 +#define GPIO_CTRL_CFG 0x0228
3003 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3004 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3005 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3006 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3007 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3008 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3009 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3010 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3011 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3012 +
3013 +/*
3014 + * MCU_CMD_CFG
3015 + */
3016 +#define MCU_CMD_CFG 0x022c
3017 +
3018 +/*
3019 + * AC_BK register offsets
3020 + */
3021 +#define TX_BASE_PTR0 0x0230
3022 +#define TX_MAX_CNT0 0x0234
3023 +#define TX_CTX_IDX0 0x0238
3024 +#define TX_DTX_IDX0 0x023c
3025 +
3026 +/*
3027 + * AC_BE register offsets
3028 + */
3029 +#define TX_BASE_PTR1 0x0240
3030 +#define TX_MAX_CNT1 0x0244
3031 +#define TX_CTX_IDX1 0x0248
3032 +#define TX_DTX_IDX1 0x024c
3033 +
3034 +/*
3035 + * AC_VI register offsets
3036 + */
3037 +#define TX_BASE_PTR2 0x0250
3038 +#define TX_MAX_CNT2 0x0254
3039 +#define TX_CTX_IDX2 0x0258
3040 +#define TX_DTX_IDX2 0x025c
3041 +
3042 +/*
3043 + * AC_VO register offsets
3044 + */
3045 +#define TX_BASE_PTR3 0x0260
3046 +#define TX_MAX_CNT3 0x0264
3047 +#define TX_CTX_IDX3 0x0268
3048 +#define TX_DTX_IDX3 0x026c
3049 +
3050 +/*
3051 + * HCCA register offsets
3052 + */
3053 +#define TX_BASE_PTR4 0x0270
3054 +#define TX_MAX_CNT4 0x0274
3055 +#define TX_CTX_IDX4 0x0278
3056 +#define TX_DTX_IDX4 0x027c
3057 +
3058 +/*
3059 + * MGMT register offsets
3060 + */
3061 +#define TX_BASE_PTR5 0x0280
3062 +#define TX_MAX_CNT5 0x0284
3063 +#define TX_CTX_IDX5 0x0288
3064 +#define TX_DTX_IDX5 0x028c
3065 +
3066 +/*
3067 + * Queue register offset macros
3068 + */
3069 +#define TX_QUEUE_REG_OFFSET 0x10
3070 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3071 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3072 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3073 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3074 +
3075 +/*
3076 + * RX register offsets
3077 + */
3078 +#define RX_BASE_PTR 0x0290
3079 +#define RX_MAX_CNT 0x0294
3080 +#define RX_CRX_IDX 0x0298
3081 +#define RX_DRX_IDX 0x029c
3082 +
3083 +/*
3084 + * PBF_SYS_CTRL
3085 + * HOST_RAM_WRITE: enable Host program ram write selection
3086 + */
3087 +#define PBF_SYS_CTRL 0x0400
3088 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3089 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3090 +
3091 +/*
3092 + * PBF registers
3093 + * Most are for debug. Driver doesn't touch PBF register.
3094 + */
3095 +#define PBF_CFG 0x0408
3096 +#define PBF_MAX_PCNT 0x040c
3097 +#define PBF_CTRL 0x0410
3098 +#define PBF_INT_STA 0x0414
3099 +#define PBF_INT_ENA 0x0418
3100 +
3101 +/*
3102 + * BCN_OFFSET0:
3103 + */
3104 +#define BCN_OFFSET0 0x042c
3105 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3106 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3107 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3108 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3109 +
3110 +/*
3111 + * BCN_OFFSET1:
3112 + */
3113 +#define BCN_OFFSET1 0x0430
3114 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3115 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3116 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3117 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3118 +
3119 +/*
3120 + * PBF registers
3121 + * Most are for debug. Driver doesn't touch PBF register.
3122 + */
3123 +#define TXRXQ_PCNT 0x0438
3124 +#define PBF_DBG 0x043c
3125 +
3126 +/*
3127 + * MAC Control/Status Registers(CSR).
3128 + * Some values are set in TU, whereas 1 TU == 1024 us.
3129 + */
3130 +
3131 +/*
3132 + * MAC_CSR0: ASIC revision number.
3133 + * ASIC_REV: 0
3134 + * ASIC_VER: 2860
3135 + */
3136 +#define MAC_CSR0 0x1000
3137 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3138 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3139 +
3140 +/*
3141 + * MAC_SYS_CTRL:
3142 + */
3143 +#define MAC_SYS_CTRL 0x1004
3144 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3145 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3146 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3147 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3148 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3149 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3150 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3151 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3152 +
3153 +/*
3154 + * MAC_ADDR_DW0: STA MAC register 0
3155 + */
3156 +#define MAC_ADDR_DW0 0x1008
3157 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3158 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3159 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3160 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3161 +
3162 +/*
3163 + * MAC_ADDR_DW1: STA MAC register 1
3164 + * UNICAST_TO_ME_MASK:
3165 + * Used to mask off bits from byte 5 of the MAC address
3166 + * to determine the UNICAST_TO_ME bit for RX frames.
3167 + * The full mask is complemented by BSS_ID_MASK:
3168 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3169 + */
3170 +#define MAC_ADDR_DW1 0x100c
3171 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3172 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3173 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3174 +
3175 +/*
3176 + * MAC_BSSID_DW0: BSSID register 0
3177 + */
3178 +#define MAC_BSSID_DW0 0x1010
3179 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3180 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3181 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3182 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3183 +
3184 +/*
3185 + * MAC_BSSID_DW1: BSSID register 1
3186 + * BSS_ID_MASK:
3187 + * 0: 1-BSSID mode (BSS index = 0)
3188 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3189 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3190 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3191 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3192 + * BSSID. This will make sure that those bits will be ignored
3193 + * when determining the MY_BSS of RX frames.
3194 + */
3195 +#define MAC_BSSID_DW1 0x1014
3196 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3197 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3198 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3199 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3200 +
3201 +/*
3202 + * MAX_LEN_CFG: Maximum frame length register.
3203 + * MAX_MPDU: rt2860b max 16k bytes
3204 + * MAX_PSDU: Maximum PSDU length
3205 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3206 + */
3207 +#define MAX_LEN_CFG 0x1018
3208 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3209 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3210 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3211 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3212 +
3213 +/*
3214 + * BBP_CSR_CFG: BBP serial control register
3215 + * VALUE: Register value to program into BBP
3216 + * REG_NUM: Selected BBP register
3217 + * READ_CONTROL: 0 write BBP, 1 read BBP
3218 + * BUSY: ASIC is busy executing BBP commands
3219 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3220 + * BBP_RW_MODE: 0 serial, 1 paralell
3221 + */
3222 +#define BBP_CSR_CFG 0x101c
3223 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3224 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3225 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3226 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3227 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3228 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3229 +
3230 +/*
3231 + * RF_CSR_CFG0: RF control register
3232 + * REGID_AND_VALUE: Register value to program into RF
3233 + * BITWIDTH: Selected RF register
3234 + * STANDBYMODE: 0 high when standby, 1 low when standby
3235 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3236 + * BUSY: ASIC is busy executing RF commands
3237 + */
3238 +#define RF_CSR_CFG0 0x1020
3239 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3240 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3241 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3242 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3243 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3244 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3245 +
3246 +/*
3247 + * RF_CSR_CFG1: RF control register
3248 + * REGID_AND_VALUE: Register value to program into RF
3249 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3250 + * 0: 3 system clock cycle (37.5usec)
3251 + * 1: 5 system clock cycle (62.5usec)
3252 + */
3253 +#define RF_CSR_CFG1 0x1024
3254 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3255 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3256 +
3257 +/*
3258 + * RF_CSR_CFG2: RF control register
3259 + * VALUE: Register value to program into RF
3260 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3261 + * 0: 3 system clock cycle (37.5usec)
3262 + * 1: 5 system clock cycle (62.5usec)
3263 + */
3264 +#define RF_CSR_CFG2 0x1028
3265 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3266 +
3267 +/*
3268 + * LED_CFG: LED control
3269 + * color LED's:
3270 + * 0: off
3271 + * 1: blinking upon TX2
3272 + * 2: periodic slow blinking
3273 + * 3: always on
3274 + * LED polarity:
3275 + * 0: active low
3276 + * 1: active high
3277 + */
3278 +#define LED_CFG 0x102c
3279 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3280 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3281 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3282 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3283 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3284 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3285 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3286 +
3287 +/*
3288 + * XIFS_TIME_CFG: MAC timing
3289 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3290 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3291 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3292 + * when MAC doesn't reference BBP signal BBRXEND
3293 + * EIFS: unit 1us
3294 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3295 + *
3296 + */
3297 +#define XIFS_TIME_CFG 0x1100
3298 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3299 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3300 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3301 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3302 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3303 +
3304 +/*
3305 + * BKOFF_SLOT_CFG:
3306 + */
3307 +#define BKOFF_SLOT_CFG 0x1104
3308 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3309 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3310 +
3311 +/*
3312 + * NAV_TIME_CFG:
3313 + */
3314 +#define NAV_TIME_CFG 0x1108
3315 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3316 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3317 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3318 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3319 +
3320 +/*
3321 + * CH_TIME_CFG: count as channel busy
3322 + */
3323 +#define CH_TIME_CFG 0x110c
3324 +
3325 +/*
3326 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3327 + */
3328 +#define PBF_LIFE_TIMER 0x1110
3329 +
3330 +/*
3331 + * BCN_TIME_CFG:
3332 + * BEACON_INTERVAL: in unit of 1/16 TU
3333 + * TSF_TICKING: Enable TSF auto counting
3334 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3335 + * BEACON_GEN: Enable beacon generator
3336 + */
3337 +#define BCN_TIME_CFG 0x1114
3338 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3339 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3340 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3341 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3342 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3343 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3344 +
3345 +/*
3346 + * TBTT_SYNC_CFG:
3347 + */
3348 +#define TBTT_SYNC_CFG 0x1118
3349 +
3350 +/*
3351 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3352 + */
3353 +#define TSF_TIMER_DW0 0x111c
3354 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3355 +
3356 +/*
3357 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3358 + */
3359 +#define TSF_TIMER_DW1 0x1120
3360 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3361 +
3362 +/*
3363 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3364 + */
3365 +#define TBTT_TIMER 0x1124
3366 +
3367 +/*
3368 + * INT_TIMER_CFG:
3369 + */
3370 +#define INT_TIMER_CFG 0x1128
3371 +
3372 +/*
3373 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3374 + */
3375 +#define INT_TIMER_EN 0x112c
3376 +
3377 +/*
3378 + * CH_IDLE_STA: channel idle time
3379 + */
3380 +#define CH_IDLE_STA 0x1130
3381 +
3382 +/*
3383 + * CH_BUSY_STA: channel busy time
3384 + */
3385 +#define CH_BUSY_STA 0x1134
3386 +
3387 +/*
3388 + * MAC_STATUS_CFG:
3389 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3390 + * if 1 or higher one of the 2 registers is busy.
3391 + */
3392 +#define MAC_STATUS_CFG 0x1200
3393 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3394 +
3395 +/*
3396 + * PWR_PIN_CFG:
3397 + */
3398 +#define PWR_PIN_CFG 0x1204
3399 +
3400 +/*
3401 + * AUTOWAKEUP_CFG: Manual power control / status register
3402 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3403 + * AUTOWAKE: 0:sleep, 1:awake
3404 + */
3405 +#define AUTOWAKEUP_CFG 0x1208
3406 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3407 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3408 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3409 +
3410 +/*
3411 + * EDCA_AC0_CFG:
3412 + */
3413 +#define EDCA_AC0_CFG 0x1300
3414 +#define EDCA_AC0_CFG_AC_TX_OP FIELD32(0x000000ff)
3415 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3416 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3417 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3418 +
3419 +/*
3420 + * EDCA_AC1_CFG:
3421 + */
3422 +#define EDCA_AC1_CFG 0x1304
3423 +#define EDCA_AC1_CFG_AC_TX_OP FIELD32(0x000000ff)
3424 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3425 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3426 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3427 +
3428 +/*
3429 + * EDCA_AC2_CFG:
3430 + */
3431 +#define EDCA_AC2_CFG 0x1308
3432 +#define EDCA_AC2_CFG_AC_TX_OP FIELD32(0x000000ff)
3433 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3434 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3435 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3436 +
3437 +/*
3438 + * EDCA_AC3_CFG:
3439 + */
3440 +#define EDCA_AC3_CFG 0x130c
3441 +#define EDCA_AC3_CFG_AC_TX_OP FIELD32(0x000000ff)
3442 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3443 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3444 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3445 +
3446 +/*
3447 + * EDCA_TID_AC_MAP:
3448 + */
3449 +#define EDCA_TID_AC_MAP 0x1310
3450 +
3451 +/*
3452 + * TX_PWR_CFG_0:
3453 + */
3454 +#define TX_PWR_CFG_0 0x1314
3455 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3456 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3457 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3458 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3459 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3460 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3461 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3462 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3463 +
3464 +/*
3465 + * TX_PWR_CFG_1:
3466 + */
3467 +#define TX_PWR_CFG_1 0x1318
3468 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3469 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3470 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3471 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3472 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3473 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3474 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3475 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3476 +
3477 +/*
3478 + * TX_PWR_CFG_2:
3479 + */
3480 +#define TX_PWR_CFG_2 0x131c
3481 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3482 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3483 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3484 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3485 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3486 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3487 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3488 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3489 +
3490 +/*
3491 + * TX_PWR_CFG_3:
3492 + */
3493 +#define TX_PWR_CFG_3 0x1320
3494 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3495 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3496 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3497 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3498 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3499 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3500 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3501 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3502 +
3503 +/*
3504 + * TX_PWR_CFG_4:
3505 + */
3506 +#define TX_PWR_CFG_4 0x1324
3507 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3508 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3509 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3510 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3511 +
3512 +/*
3513 + * TX_PIN_CFG:
3514 + */
3515 +#define TX_PIN_CFG 0x1328
3516 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3517 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3518 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3519 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3520 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3521 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3522 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3523 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3524 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3525 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3526 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3527 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3528 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3529 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3530 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3531 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3532 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3533 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3534 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3535 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3536 +
3537 +/*
3538 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3539 + */
3540 +#define TX_BAND_CFG 0x132c
3541 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3542 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3543 +
3544 +/*
3545 + * TX_SW_CFG0:
3546 + */
3547 +#define TX_SW_CFG0 0x1330
3548 +
3549 +/*
3550 + * TX_SW_CFG1:
3551 + */
3552 +#define TX_SW_CFG1 0x1334
3553 +
3554 +/*
3555 + * TX_SW_CFG2:
3556 + */
3557 +#define TX_SW_CFG2 0x1338
3558 +
3559 +/*
3560 + * TXOP_THRES_CFG:
3561 + */
3562 +#define TXOP_THRES_CFG 0x133c
3563 +
3564 +/*
3565 + * TXOP_CTRL_CFG:
3566 + */
3567 +#define TXOP_CTRL_CFG 0x1340
3568 +
3569 +/*
3570 + * TX_RTS_CFG:
3571 + * RTS_THRES: unit:byte
3572 + * RTS_FBK_EN: enable rts rate fallback
3573 + */
3574 +#define TX_RTS_CFG 0x1344
3575 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3576 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3577 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3578 +
3579 +/*
3580 + * TX_TIMEOUT_CFG:
3581 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3582 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3583 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3584 + * it is recommended that:
3585 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3586 + */
3587 +#define TX_TIMEOUT_CFG 0x1348
3588 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3589 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3590 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3591 +
3592 +/*
3593 + * TX_RTY_CFG:
3594 + * SHORT_RTY_LIMIT: short retry limit
3595 + * LONG_RTY_LIMIT: long retry limit
3596 + * LONG_RTY_THRE: Long retry threshoold
3597 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3598 + * 0:expired by retry limit, 1: expired by mpdu life timer
3599 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3600 + * 0:expired by retry limit, 1: expired by mpdu life timer
3601 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3602 + */
3603 +#define TX_RTY_CFG 0x134c
3604 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3605 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3606 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3607 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3608 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3609 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3610 +
3611 +/*
3612 + * TX_LINK_CFG:
3613 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3614 + * MFB_ENABLE: TX apply remote MFB 1:enable
3615 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3616 + * 0: not apply remote remote unsolicit (MFS=7)
3617 + * TX_MRQ_EN: MCS request TX enable
3618 + * TX_RDG_EN: RDG TX enable
3619 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3620 + * REMOTE_MFB: remote MCS feedback
3621 + * REMOTE_MFS: remote MCS feedback sequence number
3622 + */
3623 +#define TX_LINK_CFG 0x1350
3624 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3625 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3626 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3627 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3628 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3629 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3630 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3631 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3632 +
3633 +/*
3634 + * HT_FBK_CFG0:
3635 + */
3636 +#define HT_FBK_CFG0 0x1354
3637 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3638 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3639 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3640 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3641 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3642 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3643 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3644 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3645 +
3646 +/*
3647 + * HT_FBK_CFG1:
3648 + */
3649 +#define HT_FBK_CFG1 0x1358
3650 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3651 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3652 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3653 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3654 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3655 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3656 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3657 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3658 +
3659 +/*
3660 + * LG_FBK_CFG0:
3661 + */
3662 +#define LG_FBK_CFG0 0x135c
3663 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3664 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3665 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3666 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3667 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3668 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3669 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3670 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3671 +
3672 +/*
3673 + * LG_FBK_CFG1:
3674 + */
3675 +#define LG_FBK_CFG1 0x1360
3676 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3677 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3678 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3679 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3680 +
3681 +/*
3682 + * CCK_PROT_CFG: CCK Protection
3683 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3684 + * PROTECT_CTRL: Protection control frame type for CCK TX
3685 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3686 + * PROTECT_NAV: TXOP protection type for CCK TX
3687 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3688 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3689 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3690 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3691 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3692 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3693 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3694 + * RTS_TH_EN: RTS threshold enable on CCK TX
3695 + */
3696 +#define CCK_PROT_CFG 0x1364
3697 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3698 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3699 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3700 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3701 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3702 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3703 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3704 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3705 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3706 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3707 +
3708 +/*
3709 + * OFDM_PROT_CFG: OFDM Protection
3710 + */
3711 +#define OFDM_PROT_CFG 0x1368
3712 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3713 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3714 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3715 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3716 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3717 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3718 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3719 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3720 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3721 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3722 +
3723 +/*
3724 + * MM20_PROT_CFG: MM20 Protection
3725 + */
3726 +#define MM20_PROT_CFG 0x136c
3727 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3728 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3729 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3730 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3731 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3732 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3733 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3734 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3735 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3736 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3737 +
3738 +/*
3739 + * MM40_PROT_CFG: MM40 Protection
3740 + */
3741 +#define MM40_PROT_CFG 0x1370
3742 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3743 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3744 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3745 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3746 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3747 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3748 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3749 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3750 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3751 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3752 +
3753 +/*
3754 + * GF20_PROT_CFG: GF20 Protection
3755 + */
3756 +#define GF20_PROT_CFG 0x1374
3757 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3758 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3759 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3760 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3761 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3762 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3763 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3764 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3765 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3766 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3767 +
3768 +/*
3769 + * GF40_PROT_CFG: GF40 Protection
3770 + */
3771 +#define GF40_PROT_CFG 0x1378
3772 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3773 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3774 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3775 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3776 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3777 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3778 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3779 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3780 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3781 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3782 +
3783 +/*
3784 + * EXP_CTS_TIME:
3785 + */
3786 +#define EXP_CTS_TIME 0x137c
3787 +
3788 +/*
3789 + * EXP_ACK_TIME:
3790 + */
3791 +#define EXP_ACK_TIME 0x1380
3792 +
3793 +/*
3794 + * RX_FILTER_CFG: RX configuration register.
3795 + */
3796 +#define RX_FILTER_CFG 0x1400
3797 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3798 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3799 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3800 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3801 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3802 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3803 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3804 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3805 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3806 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3807 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3808 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3809 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3810 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3811 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3812 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3813 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3814 +
3815 +/*
3816 + * AUTO_RSP_CFG:
3817 + * AUTORESPONDER: 0: disable, 1: enable
3818 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3819 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3820 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3821 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3822 + * DUAL_CTS_EN: Power bit value in control frame
3823 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3824 + */
3825 +#define AUTO_RSP_CFG 0x1404
3826 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3827 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3828 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3829 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3830 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3831 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3832 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3833 +
3834 +/*
3835 + * LEGACY_BASIC_RATE:
3836 + */
3837 +#define LEGACY_BASIC_RATE 0x1408
3838 +
3839 +/*
3840 + * HT_BASIC_RATE:
3841 + */
3842 +#define HT_BASIC_RATE 0x140c
3843 +
3844 +/*
3845 + * HT_CTRL_CFG:
3846 + */
3847 +#define HT_CTRL_CFG 0x1410
3848 +
3849 +/*
3850 + * SIFS_COST_CFG:
3851 + */
3852 +#define SIFS_COST_CFG 0x1414
3853 +
3854 +/*
3855 + * RX_PARSER_CFG:
3856 + * Set NAV for all received frames
3857 + */
3858 +#define RX_PARSER_CFG 0x1418
3859 +
3860 +/*
3861 + * TX_SEC_CNT0:
3862 + */
3863 +#define TX_SEC_CNT0 0x1500
3864 +
3865 +/*
3866 + * RX_SEC_CNT0:
3867 + */
3868 +#define RX_SEC_CNT0 0x1504
3869 +
3870 +/*
3871 + * CCMP_FC_MUTE:
3872 + */
3873 +#define CCMP_FC_MUTE 0x1508
3874 +
3875 +/*
3876 + * TXOP_HLDR_ADDR0:
3877 + */
3878 +#define TXOP_HLDR_ADDR0 0x1600
3879 +
3880 +/*
3881 + * TXOP_HLDR_ADDR1:
3882 + */
3883 +#define TXOP_HLDR_ADDR1 0x1604
3884 +
3885 +/*
3886 + * TXOP_HLDR_ET:
3887 + */
3888 +#define TXOP_HLDR_ET 0x1608
3889 +
3890 +/*
3891 + * QOS_CFPOLL_RA_DW0:
3892 + */
3893 +#define QOS_CFPOLL_RA_DW0 0x160c
3894 +
3895 +/*
3896 + * QOS_CFPOLL_RA_DW1:
3897 + */
3898 +#define QOS_CFPOLL_RA_DW1 0x1610
3899 +
3900 +/*
3901 + * QOS_CFPOLL_QC:
3902 + */
3903 +#define QOS_CFPOLL_QC 0x1614
3904 +
3905 +/*
3906 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3907 + */
3908 +#define RX_STA_CNT0 0x1700
3909 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
3910 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
3911 +
3912 +/*
3913 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3914 + */
3915 +#define RX_STA_CNT1 0x1704
3916 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
3917 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
3918 +
3919 +/*
3920 + * RX_STA_CNT2:
3921 + */
3922 +#define RX_STA_CNT2 0x1708
3923 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
3924 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
3925 +
3926 +/*
3927 + * TX_STA_CNT0: TX Beacon count
3928 + */
3929 +#define TX_STA_CNT0 0x170c
3930 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
3931 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
3932 +
3933 +/*
3934 + * TX_STA_CNT1: TX tx count
3935 + */
3936 +#define TX_STA_CNT1 0x1710
3937 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
3938 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
3939 +
3940 +/*
3941 + * TX_STA_CNT2: TX tx count
3942 + */
3943 +#define TX_STA_CNT2 0x1714
3944 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
3945 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
3946 +
3947 +/*
3948 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3949 + */
3950 +#define TX_STA_FIFO 0x1718
3951 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
3952 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
3953 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
3954 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
3955 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
3956 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
3957 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
3958 +
3959 +/*
3960 + * TX_AGG_CNT: Debug counter
3961 + */
3962 +#define TX_AGG_CNT 0x171c
3963 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
3964 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
3965 +
3966 +/*
3967 + * TX_AGG_CNT0:
3968 + */
3969 +#define TX_AGG_CNT0 0x1720
3970 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
3971 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
3972 +
3973 +/*
3974 + * TX_AGG_CNT1:
3975 + */
3976 +#define TX_AGG_CNT1 0x1724
3977 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
3978 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
3979 +
3980 +/*
3981 + * TX_AGG_CNT2:
3982 + */
3983 +#define TX_AGG_CNT2 0x1728
3984 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
3985 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
3986 +
3987 +/*
3988 + * TX_AGG_CNT3:
3989 + */
3990 +#define TX_AGG_CNT3 0x172c
3991 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
3992 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
3993 +
3994 +/*
3995 + * TX_AGG_CNT4:
3996 + */
3997 +#define TX_AGG_CNT4 0x1730
3998 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
3999 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4000 +
4001 +/*
4002 + * TX_AGG_CNT5:
4003 + */
4004 +#define TX_AGG_CNT5 0x1734
4005 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4006 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4007 +
4008 +/*
4009 + * TX_AGG_CNT6:
4010 + */
4011 +#define TX_AGG_CNT6 0x1738
4012 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4013 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4014 +
4015 +/*
4016 + * TX_AGG_CNT7:
4017 + */
4018 +#define TX_AGG_CNT7 0x173c
4019 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4020 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4021 +
4022 +/*
4023 + * MPDU_DENSITY_CNT:
4024 + * TX_ZERO_DEL: TX zero length delimiter count
4025 + * RX_ZERO_DEL: RX zero length delimiter count
4026 + */
4027 +#define MPDU_DENSITY_CNT 0x1740
4028 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4029 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4030 +
4031 +/*
4032 + * Security key table memory, base address = 0x1800
4033 + */
4034 +struct hw_pairwise_ta_entry {
4035 + u8 address[6];
4036 + u8 reserved[2];
4037 +} __attribute__ ((packed));
4038 +
4039 +struct wcid_entry {
4040 + u8 rx_ba_bitmat7;
4041 + u8 rx_ba_bitmat0;
4042 + u8 mac[6];
4043 +} __attribute__ ((packed));
4044 +
4045 +struct hw_key_entry {
4046 + u8 key[16];
4047 + u8 tx_mic[8];
4048 + u8 rx_mic[8];
4049 +} __attribute__ ((packed));
4050 +
4051 +/*
4052 + * Security key table memory.
4053 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4054 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4055 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
4056 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4057 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4058 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4059 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
4060 + */
4061 +#define MAC_WCID_BASE 0x1800
4062 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4063 +#define PAIRWISE_IVEIV_TABLE_BASE 0x6000
4064 +#define MAC_IVEIV_TABLE_BASE 0x6000
4065 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4066 +#define SHARED_KEY_TABLE_BASE 0x6c00
4067 +#define SHARED_KEY_MODE_BASE 0x7000
4068 +
4069 +#define SHARED_KEY_ENTRY(__idx) \
4070 + ( SHARED_KEY_TABLE_BASE + \
4071 + ((__idx) * sizeof(struct hw_key_entry)) )
4072 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4073 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4074 +#define PAIRWISE_KEY_ENTRY(__idx) \
4075 + ( PAIRWISE_KEY_TABLE_BASE + \
4076 + ((__idx) * sizeof(struct hw_key_entry)) )
4077 +
4078 +#define MAC_WCID_ENTRY(__idx) \
4079 + ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
4080 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4081 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4082 +
4083 +/*
4084 + * MAC_WCID_ATTRIBUTE:
4085 + * KEYTAB: 0: shared key table, 1: pairwise key table
4086 + * BSS_IDX: multipleBSS index for the WCID
4087 + */
4088 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4089 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE FIELD32(0x0000000e)
4090 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4091 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4092 +
4093 +/*
4094 + * SHARED_KEY_MODE:
4095 + */
4096 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4097 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4098 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4099 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4100 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4101 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4102 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4103 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4104 +
4105 +/*
4106 + * HOST-MCU communication
4107 + */
4108 +
4109 +/*
4110 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4111 + */
4112 +#define H2M_MAILBOX_CSR 0x7010
4113 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4114 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4115 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4116 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4117 +
4118 +/*
4119 + * H2M_MAILBOX_CID:
4120 + */
4121 +#define H2M_MAILBOX_CID 0x7014
4122 +
4123 +/*
4124 + * H2M_MAILBOX_STATUS:
4125 + */
4126 +#define H2M_MAILBOX_STATUS 0x701c
4127 +
4128 +/*
4129 + * H2M_INT_SRC:
4130 + */
4131 +#define H2M_INT_SRC 0x7024
4132 +
4133 +/*
4134 + * H2M_BBP_AGENT:
4135 + */
4136 +#define H2M_BBP_AGENT 0x7028
4137 +
4138 +/*
4139 + * MCU_LEDCS: LED control for MCU Mailbox.
4140 + */
4141 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4142 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4143 +
4144 +/*
4145 + * HW_CS_CTS_BASE:
4146 + * Carrier-sense CTS frame base address.
4147 + * It's where mac stores carrier-sense frame for carrier-sense function.
4148 + */
4149 +#define HW_CS_CTS_BASE 0x7700
4150 +
4151 +/*
4152 + * HW_DFS_CTS_BASE:
4153 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4154 + */
4155 +#define HW_DFS_CTS_BASE 0x7780
4156 +
4157 +/*
4158 + * TXRX control registers - base address 0x3000
4159 + */
4160 +
4161 +/*
4162 + * TXRX_CSR1:
4163 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4164 + */
4165 +#define TXRX_CSR1 0x77d0
4166 +
4167 +/*
4168 + * HW_DEBUG_SETTING_BASE:
4169 + * since NULL frame won't be that long (256 byte)
4170 + * We steal 16 tail bytes to save debugging settings
4171 + */
4172 +#define HW_DEBUG_SETTING_BASE 0x77f0
4173 +#define HW_DEBUG_SETTING_BASE2 0x7770
4174 +
4175 +/*
4176 + * HW_BEACON_BASE
4177 + * In order to support maximum 8 MBSS and its maximum length
4178 + * is 512 bytes for each beacon
4179 + * Three section discontinue memory segments will be used.
4180 + * 1. The original region for BCN 0~3
4181 + * 2. Extract memory from FCE table for BCN 4~5
4182 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4183 + * It occupied those memory of wcid 238~253 for BCN 6
4184 + * and wcid 222~237 for BCN 7
4185 + *
4186 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4187 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4188 + */
4189 +#define HW_BEACON_BASE0 0x7800
4190 +#define HW_BEACON_BASE1 0x7a00
4191 +#define HW_BEACON_BASE2 0x7c00
4192 +#define HW_BEACON_BASE3 0x7e00
4193 +#define HW_BEACON_BASE4 0x7200
4194 +#define HW_BEACON_BASE5 0x7400
4195 +#define HW_BEACON_BASE6 0x5dc0
4196 +#define HW_BEACON_BASE7 0x5bc0
4197 +
4198 +#define HW_BEACON_OFFSET(__index) \
4199 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4200 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4201 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4202 +
4203 +/*
4204 + * 8051 firmware image.
4205 + */
4206 +#define FIRMWARE_RT2860 "rt2860.bin"
4207 +#define FIRMWARE_IMAGE_BASE 0x2000
4208 +
4209 +/*
4210 + * BBP registers.
4211 + * The wordsize of the BBP is 8 bits.
4212 + */
4213 +
4214 +/*
4215 + * BBP 1: TX Antenna
4216 + */
4217 +#define BBP1_TX_POWER FIELD8(0x07)
4218 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4219 +
4220 +/*
4221 + * BBP 3: RX Antenna
4222 + */
4223 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4224 +
4225 +/*
4226 + * RF registers
4227 + */
4228 +
4229 +/*
4230 + * RF 2
4231 + */
4232 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4233 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4234 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4235 +
4236 +/*
4237 + * RF 3
4238 + */
4239 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4240 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4241 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4242 +
4243 +/*
4244 + * RF 4
4245 + */
4246 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4247 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4248 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4249 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4250 +#define RF4_BW40 FIELD32(0x00200000)
4251 +
4252 +/*
4253 + * EEPROM content.
4254 + * The wordsize of the EEPROM is 16 bits.
4255 + */
4256 +
4257 +/*
4258 + * EEPROM Version
4259 + */
4260 +#define EEPROM_VERSION 0x0001
4261 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4262 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4263 +
4264 +/*
4265 + * HW MAC address.
4266 + */
4267 +#define EEPROM_MAC_ADDR_0 0x0002
4268 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4269 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4270 +#define EEPROM_MAC_ADDR_1 0x0003
4271 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4272 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4273 +#define EEPROM_MAC_ADDR_2 0x0004
4274 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4275 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4276 +
4277 +/*
4278 + * EEPROM ANTENNA config
4279 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4280 + * TXPATH: 1: 1T, 2: 2T
4281 + */
4282 +#define EEPROM_ANTENNA 0x001a
4283 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4284 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4285 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4286 +
4287 +/*
4288 + * EEPROM NIC config
4289 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4290 + */
4291 +#define EEPROM_NIC 0x001b
4292 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4293 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4294 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4295 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4296 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4297 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4298 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4299 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4300 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4301 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4302 +
4303 +/*
4304 + * EEPROM frequency
4305 + */
4306 +#define EEPROM_FREQ 0x001d
4307 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4308 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4309 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4310 +
4311 +/*
4312 + * EEPROM LED
4313 + * POLARITY_RDY_G: Polarity RDY_G setting.
4314 + * POLARITY_RDY_A: Polarity RDY_A setting.
4315 + * POLARITY_ACT: Polarity ACT setting.
4316 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4317 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4318 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4319 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4320 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4321 + * LED_MODE: Led mode.
4322 + */
4323 +#define EEPROM_LED1 0x001e
4324 +#define EEPROM_LED2 0x001f
4325 +#define EEPROM_LED3 0x0020
4326 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4327 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4328 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4329 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4330 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4331 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4332 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4333 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4334 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4335 +
4336 +/*
4337 + * EEPROM LNA
4338 + */
4339 +#define EEPROM_LNA 0x0022
4340 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4341 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4342 +
4343 +/*
4344 + * EEPROM RSSI BG offset
4345 + */
4346 +#define EEPROM_RSSI_BG 0x0023
4347 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4348 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4349 +
4350 +/*
4351 + * EEPROM RSSI BG2 offset
4352 + */
4353 +#define EEPROM_RSSI_BG2 0x0024
4354 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4355 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4356 +
4357 +/*
4358 + * EEPROM RSSI A offset
4359 + */
4360 +#define EEPROM_RSSI_A 0x0025
4361 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4362 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4363 +
4364 +/*
4365 + * EEPROM RSSI A2 offset
4366 + */
4367 +#define EEPROM_RSSI_A2 0x0026
4368 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4369 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4370 +
4371 +/*
4372 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4373 + * This is delta in 40MHZ.
4374 + * VALUE: Tx Power dalta value (MAX=4)
4375 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4376 + * TXPOWER: Enable:
4377 + */
4378 +#define EEPROM_TXPOWER_DELTA 0x0028
4379 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4380 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4381 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4382 +
4383 +/*
4384 + * EEPROM TXPOWER 802.11G
4385 + */
4386 +#define EEPROM_TXPOWER_BG1 0x0029
4387 +#define EEPROM_TXPOWER_BG2 0x0030
4388 +#define EEPROM_TXPOWER_BG_SIZE 7
4389 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4390 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4391 +
4392 +/*
4393 + * EEPROM TXPOWER 802.11A
4394 + */
4395 +#define EEPROM_TXPOWER_A1 0x003c
4396 +#define EEPROM_TXPOWER_A2 0x0053
4397 +#define EEPROM_TXPOWER_A_SIZE 6
4398 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4399 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4400 +
4401 +/*
4402 + * EEPROM TXpower byrate: 20MHZ power
4403 + */
4404 +#define EEPROM_TXPOWER_BYRATE 0x006f
4405 +
4406 +/*
4407 + * EEPROM BBP.
4408 + */
4409 +#define EEPROM_BBP_START 0x0078
4410 +#define EEPROM_BBP_SIZE 16
4411 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4412 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4413 +
4414 +/*
4415 + * MCU mailbox commands.
4416 + */
4417 +#define MCU_SLEEP 0x30
4418 +#define MCU_WAKEUP 0x31
4419 +#define MCU_LED 0x50
4420 +#define MCU_LED_STRENGTH 0x51
4421 +#define MCU_LED_1 0x52
4422 +#define MCU_LED_2 0x53
4423 +#define MCU_LED_3 0x54
4424 +#define MCU_RADAR 0x60
4425 +#define MCU_BOOT_SIGNAL 0x72
4426 +
4427 +/*
4428 + * DMA descriptor defines.
4429 + */
4430 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4431 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4432 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
4433 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4434 +
4435 +/*
4436 + * TX descriptor format for TX, PRIO and Beacon Ring.
4437 + */
4438 +
4439 +/*
4440 + * Word0
4441 + */
4442 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4443 +
4444 +/*
4445 + * Word1
4446 + */
4447 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4448 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4449 +#define TXD_W1_BURST FIELD32(0x00008000)
4450 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4451 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4452 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4453 +
4454 +/*
4455 + * Word2
4456 + */
4457 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4458 +
4459 +/*
4460 + * Word3
4461 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4462 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4463 + * 0:MGMT, 1:HCCA 2:EDCA
4464 + */
4465 +#define TXD_W3_WIV FIELD32(0x01000000)
4466 +#define TXD_W3_QSEL FIELD32(0x06000000)
4467 +#define TXD_W3_TCO FIELD32(0x20000000)
4468 +#define TXD_W3_UCO FIELD32(0x40000000)
4469 +#define TXD_W3_ICO FIELD32(0x80000000)
4470 +
4471 +/*
4472 + * TX WI structure
4473 + */
4474 +
4475 +/*
4476 + * Word0
4477 + * FRAG: 1 To inform TKIP engine this is a fragment.
4478 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4479 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4480 + * BW: Channel bandwidth 20MHz or 40 MHz
4481 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4482 + */
4483 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4484 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4485 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4486 +#define TXWI_W0_TS FIELD32(0x00000008)
4487 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4488 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4489 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4490 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4491 +#define TXWI_W0_BW FIELD32(0x00800000)
4492 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4493 +#define TXWI_W0_STBC FIELD32(0x06000000)
4494 +#define TXWI_W0_IFS FIELD32(0x08000000)
4495 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4496 +
4497 +/*
4498 + * Word1
4499 + */
4500 +#define TXWI_W1_ACK FIELD32(0x00000001)
4501 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4502 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4503 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4504 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4505 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4506 +
4507 +/*
4508 + * Word2
4509 + */
4510 +#define TXWI_W2_IV FIELD32(0xffffffff)
4511 +
4512 +/*
4513 + * Word3
4514 + */
4515 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4516 +
4517 +/*
4518 + * RX descriptor format for RX Ring.
4519 + */
4520 +
4521 +/*
4522 + * Word0
4523 + */
4524 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
4525 +
4526 +/*
4527 + * Word1
4528 + */
4529 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
4530 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
4531 +#define RXD_W1_LS0 FIELD32(0x40000000)
4532 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
4533 +
4534 +/*
4535 + * Word2
4536 + */
4537 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
4538 +
4539 +/*
4540 + * Word3
4541 + * AMSDU: RX with 802.3 header, not 802.11 header.
4542 + * DECRYPTED: This frame is being decrypted.
4543 + */
4544 +#define RXD_W3_BA FIELD32(0x00000001)
4545 +#define RXD_W3_DATA FIELD32(0x00000002)
4546 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
4547 +#define RXD_W3_FRAG FIELD32(0x00000008)
4548 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
4549 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
4550 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
4551 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
4552 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
4553 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
4554 +#define RXD_W3_AMSDU FIELD32(0x00000800)
4555 +#define RXD_W3_HTC FIELD32(0x00001000)
4556 +#define RXD_W3_RSSI FIELD32(0x00002000)
4557 +#define RXD_W3_L2PAD FIELD32(0x00004000)
4558 +#define RXD_W3_AMPDU FIELD32(0x00008000)
4559 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
4560 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
4561 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
4562 +
4563 +/*
4564 + * RX WI structure
4565 + */
4566 +
4567 +/*
4568 + * Word0
4569 + */
4570 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4571 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4572 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4573 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4574 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4575 +#define RXWI_W0_TID FIELD32(0xf0000000)
4576 +
4577 +/*
4578 + * Word1
4579 + */
4580 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4581 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4582 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4583 +#define RXWI_W1_BW FIELD32(0x00800000)
4584 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4585 +#define RXWI_W1_STBC FIELD32(0x06000000)
4586 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4587 +
4588 +/*
4589 + * Word2
4590 + */
4591 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4592 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4593 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4594 +
4595 +/*
4596 + * Word3
4597 + */
4598 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4599 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4600 +
4601 +/*
4602 + * Macro's for converting txpower from EEPROM to mac80211 value
4603 + * and from mac80211 value to register value.
4604 + */
4605 +#define MIN_G_TXPOWER 0
4606 +#define MIN_A_TXPOWER -7
4607 +#define MAX_G_TXPOWER 31
4608 +#define MAX_A_TXPOWER 15
4609 +#define DEFAULT_TXPOWER 5
4610 +
4611 +#define TXPOWER_G_FROM_DEV(__txpower) \
4612 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4613 +
4614 +#define TXPOWER_G_TO_DEV(__txpower) \
4615 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4616 +
4617 +#define TXPOWER_A_FROM_DEV(__txpower) \
4618 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4619 +
4620 +#define TXPOWER_A_TO_DEV(__txpower) \
4621 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4622 +
4623 +#endif /* RT2800PCI_H */
4624 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4625 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4626 @@ -139,6 +139,10 @@ struct rt2x00_chip {
4627 #define RT2561 0x0302
4628 #define RT2661 0x0401
4629 #define RT2571 0x1300
4630 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
4631 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4632 +#define RT2890 0x0701 /* 2.4GHz PCIe */
4633 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4634
4635 u16 rf;
4636 u32 rev;
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